Line Coverage for Module :
hmac
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 198 | 198 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| ALWAYS | 150 | 15 | 15 | 100.00 |
| ALWAYS | 192 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 7 | 7 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
| ALWAYS | 231 | 19 | 19 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| ALWAYS | 287 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| ALWAYS | 304 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
| ALWAYS | 310 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 327 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 329 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 330 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 332 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 333 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 335 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 337 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 338 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 340 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 343 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 344 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 351 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 352 | 1 | 1 | 100.00 |
| ALWAYS | 355 | 6 | 6 | 100.00 |
| ALWAYS | 365 | 4 | 4 | 100.00 |
| ALWAYS | 404 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 455 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 462 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 472 | 1 | 1 | 100.00 |
| ALWAYS | 475 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 518 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 527 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 535 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
| ALWAYS | 542 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
| ALWAYS | 622 | 3 | 3 | 100.00 |
| ALWAYS | 630 | 3 | 3 | 100.00 |
| ALWAYS | 635 | 10 | 10 | 100.00 |
| CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 653 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 660 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 661 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 771 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 801 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 802 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 807 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 812 | 1 | 1 | 100.00 |
| ALWAYS | 815 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 831 | 1 | 1 | 100.00 |
| ALWAYS | 837 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 880 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 884 | 1 | 1 | 100.00 |
| ALWAYS | 886 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 892 | 1 | 1 | 100.00 |
| ALWAYS | 914 | 6 | 6 | 100.00 |
| ALWAYS | 921 | 6 | 6 | 100.00 |
134 ///////////////////////
135 1/1 assign hw2reg.status.fifo_full.d = fifo_full;
Tests: T1 T2 T3
136 1/1 assign hw2reg.status.fifo_empty.d = fifo_empty;
Tests: T1 T2 T3
137 1/1 assign hw2reg.status.fifo_depth.d = fifo_depth;
Tests: T1 T2 T3
138 1/1 assign hw2reg.status.hmac_idle.d = idle;
Tests: T1 T2 T3
139
140 typedef enum logic [1:0] {
141 DoneAwaitCmd,
142 DoneAwaitHashDone,
143 DoneAwaitMessageComplete,
144 DoneAwaitHashComplete
145 } done_state_e;
146
147 done_state_e done_state_d, done_state_q;
148
149 always_comb begin
150 1/1 done_state_d = done_state_q;
Tests: T1 T2 T3
151 1/1 hash_done_event = 1'b0;
Tests: T1 T2 T3
152
153 1/1 unique case (done_state_q)
Tests: T1 T2 T3
154 DoneAwaitCmd: begin
155 1/1 if (sha_hash_process) begin
Tests: T1 T2 T3
156 // SHA has been told to process the message, so signal *done* when the hash is done.
157 1/1 done_state_d = DoneAwaitHashDone;
Tests: T1 T4 T5
158 1/1 end else if (reg_hash_stop) begin
Tests: T1 T2 T3
159 // SHA has been told to stop, so first wait for the current message block to be complete.
160 1/1 done_state_d = DoneAwaitMessageComplete;
Tests: T4 T7 T8
161 end
MISSING_ELSE
162 end
163
164 DoneAwaitHashDone: begin
165 1/1 if (reg_hash_done) begin
Tests: T1 T4 T5
166 1/1 hash_done_event = 1'b1;
Tests: T1 T4 T5
167 1/1 done_state_d = DoneAwaitCmd;
Tests: T1 T4 T5
168 end
MISSING_ELSE
169 end
170
171 DoneAwaitMessageComplete: begin
172 1/1 if (digest_on_blk) begin
Tests: T4 T7 T8
173 // Once the digest is being computed for the complete message block, wait for the hash to
174 // complete.
175 // TODO (issue #21710): handle incomplete message size and check against 512 or 1024
176 1/1 done_state_d = DoneAwaitHashComplete;
Tests: T4 T7 T8
177 end
MISSING_ELSE
178 end
179
180 DoneAwaitHashComplete: begin
181 1/1 if (!hash_running) begin
Tests: T4 T7 T8
182 1/1 hash_done_event = 1'b1;
Tests: T4 T7 T8
183 1/1 done_state_d = DoneAwaitCmd;
Tests: T4 T7 T8
184 end
==> MISSING_ELSE
185 end
186
187 default: ;
188 endcase
189 end
190
191 always_ff @(posedge clk_i or negedge rst_ni) begin
192 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
193 1/1 done_state_q <= DoneAwaitCmd;
Tests: T1 T2 T3
194 end else begin
195 1/1 done_state_q <= done_state_d;
Tests: T1 T2 T3
196 end
197 end
198
199 1/1 assign wipe_secret = reg2hw.wipe_secret.qe;
Tests: T9 T12 T14
200 1/1 assign wipe_v = reg2hw.wipe_secret.q;
Tests: T1 T2 T3
201
202 // update secret key
203 always_comb begin : update_secret_key
204 1/1 secret_key_d = secret_key;
Tests: T1 T2 T3
205 1/1 if (wipe_secret) begin
Tests: T1 T2 T3
206 1/1 secret_key_d = {32{wipe_v}};
Tests: T9 T12 T26
207 1/1 end else if (!cfg_block) begin
Tests: T1 T2 T3
208 // Allow updating secret key only when the engine is in Idle.
209 1/1 for (int i = 0; i < 32; i++) begin
Tests: T1 T2 T3
210 1/1 if (reg2hw.key[31-i].qe) begin
Tests: T1 T2 T3
211 // swap byte endianness per secret key word if key_swap = 1
212 1/1 secret_key_d[32*i+:32] = conv_endian32(reg2hw.key[31-i].q, key_swap);
Tests: T1 T4 T5
213 end
MISSING_ELSE
214 end
215 end
MISSING_ELSE
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin
219 2/2 if (!rst_ni) secret_key <= '0;
Tests: T1 T2 T3 | T1 T2 T3
220 1/1 else secret_key <= secret_key_d;
Tests: T1 T2 T3
221 end
222
223 for (genvar i = 0; i < 32; i++) begin : gen_key
224 assign hw2reg.key[31-i].d = '0;
225 end
226
227 // Retain the previous digest in CSRs until HMAC is actually started with a valid configuration
228 always_comb begin : assign_digest_reg
229 // default
230 // digest SW -> HW
231 1/1 digest_sw = '0;
Tests: T1 T2 T3
232 1/1 digest_sw_we = '0;
Tests: T1 T2 T3
233 // digest HW -> SW
234 1/1 hw2reg.digest = '0;
Tests: T1 T2 T3
235
236 1/1 for (int i = 0; i < 8; i++) begin
Tests: T1 T2 T3
237 // digest SW -> HW (depends on digest size configured even before starting/enabling)
238 // capturing the intermediate digests written by SW when restoring context into the SHA-2
239 // engine before it is started
240 1/1 if (digest_size == SHA2_256) begin
Tests: T1 T2 T3
241 // digest SW -> HW
242 1/1 digest_sw[i][31:0] = conv_endian32(reg2hw.digest[i].q, digest_swap);
Tests: T1 T6 T7
243 1/1 digest_sw_we[i] = reg2hw.digest[i].qe;
Tests: T1 T6 T7
244 1/1 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
Tests: T1 T2 T3
245 // digest SW -> HW
246 1/1 digest_sw[i][63:32] = reg2hw.digest[2*i].qe ?
Tests: T1 T4 T5
247 conv_endian32(reg2hw.digest[2*i].q, digest_swap) :
248 digest[i][63:32];
249 1/1 digest_sw[i][31:0] = reg2hw.digest[2*i+1].qe ?
Tests: T1 T4 T5
250 conv_endian32(reg2hw.digest[2*i+1].q, digest_swap) :
251 digest[i][31:0];
252 1/1 digest_sw_we[i] = reg2hw.digest[2*i].qe | reg2hw.digest[2*i+1].qe;
Tests: T1 T4 T5
253 end
MISSING_ELSE
254
255 // digest HW -> SW (depends on configuration that has been started)
256 1/1 if (digest_size_started_q == SHA2_256) begin
Tests: T1 T2 T3
257 1/1 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T6 T7
258 // replicate digest[0..7] into digest[8..15]. Digest[8...15] are irrelevant for SHA2_256,
259 // but this ensures all digest CSRs are wiped out with random value (at wipe_secret)
260 // across different configurations.
261 1/1 hw2reg.digest[i+8].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T6 T7
262 1/1 end else if ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)) begin
Tests: T1 T2 T3
263 // digest HW -> SW
264 // digest swap only within each 32-bit word of the 64-bit digest word, not digest swap
265 // on the entire 64-bit digest word
266 1/1 hw2reg.digest[2*i].d = conv_endian32(digest[i][63:32], digest_swap);
Tests: T1 T4 T5
267 1/1 hw2reg.digest[2*i+1].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T4 T5
268 end else begin // for SHA2_None
269 // to ensure secret wiping is always passed to digest CSRs
270 1/1 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T2 T3
271 1/1 hw2reg.digest[i+8].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T2 T3
272 end
273 end
274 end
275
276 logic unused_cfg_qe;
277 1/1 assign unused_cfg_qe = ^{cfg_reg.sha_en.qe, cfg_reg.hmac_en.qe,
Tests: T1 T2 T3
278 cfg_reg.endian_swap.qe, cfg_reg.digest_swap.qe,
279 cfg_reg.key_swap.qe, cfg_reg.digest_size.qe,
280 cfg_reg.key_length.qe };
281
282 1/1 assign sha_en = cfg_reg.sha_en.q;
Tests: T1 T2 T3
283 1/1 assign hmac_en = cfg_reg.hmac_en.q;
Tests: T1 T2 T3
284
285 1/1 assign digest_size_supplied = digest_mode_e'(cfg_reg.digest_size.q);
Tests: T1 T2 T3
286 always_comb begin : cast_digest_size
287 1/1 digest_size = SHA2_None;
Tests: T1 T2 T3
288
289 1/1 unique case (digest_size_supplied)
Tests: T1 T2 T3
290 1/1 SHA2_256: digest_size = SHA2_256;
Tests: T1 T6 T7
291 1/1 SHA2_384: digest_size = SHA2_384;
Tests: T5 T6 T7
292 1/1 SHA2_512: digest_size = SHA2_512;
Tests: T1 T4 T5
293 // unsupported digest size values are mapped to SHA2_None
294 // if HMAC/SHA-2 is triggered to start with this digest size, it is blocked
295 // and an error is signalled to SW
296 default: digest_size = SHA2_None;
297 endcase
298 end
299
300 // Hold the previous digest size till HMAC is started with the new digest size configured
301 1/1 assign digest_size_started_d = (hash_start_or_continue) ? digest_size : digest_size_started_q;
Tests: T1 T2 T3
302
303 always_ff @(posedge clk_i or negedge rst_ni) begin
304 2/2 if (!rst_ni) digest_size_started_q <= SHA2_None;
Tests: T1 T2 T3 | T1 T2 T3
305 1/1 else digest_size_started_q <= digest_size_started_d;
Tests: T1 T2 T3
306 end
307
308 1/1 assign key_length_supplied = key_length_e'(cfg_reg.key_length.q);
Tests: T1 T2 T3
309 always_comb begin : cast_key_length
310 1/1 key_length = Key_None;
Tests: T1 T2 T3
311
312 1/1 unique case (key_length_supplied)
Tests: T1 T2 T3
313 1/1 Key_128: key_length = Key_128;
Tests: T1 T5 T6
314 1/1 Key_256: key_length = Key_256;
Tests: T1 T5 T6
315 1/1 Key_384: key_length = Key_384;
Tests: T1 T4 T6
316 1/1 Key_512: key_length = Key_512;
Tests: T1 T4 T5
317 1/1 Key_1024: key_length = Key_1024;
Tests: T1 T4 T7
318 // unsupported key length values are mapped to Key_None
319 // if HMAC (not SHA-2) is triggered to start with this key length, it is blocked
320 // and an error is signalled to SW
321 default: key_length = Key_None;
322 endcase
323 end
324
325 1/1 assign endian_swap = cfg_reg.endian_swap.q;
Tests: T1 T2 T3
326 1/1 assign digest_swap = cfg_reg.digest_swap.q;
Tests: T1 T2 T3
327 1/1 assign key_swap = cfg_reg.key_swap.q;
Tests: T1 T2 T3
328
329 1/1 assign hw2reg.cfg.hmac_en.d = cfg_reg.hmac_en.q;
Tests: T1 T2 T3
330 1/1 assign hw2reg.cfg.sha_en.d = cfg_reg.sha_en.q;
Tests: T1 T2 T3
331 1/1 assign hw2reg.cfg.digest_size.d = digest_mode_e'(digest_size);
Tests: T1 T2 T3
332 1/1 assign hw2reg.cfg.key_length.d = key_length_e'(key_length);
Tests: T1 T2 T3
333 1/1 assign hw2reg.cfg.endian_swap.d = cfg_reg.endian_swap.q;
Tests: T1 T2 T3
334 1/1 assign hw2reg.cfg.digest_swap.d = cfg_reg.digest_swap.q;
Tests: T1 T2 T3
335 1/1 assign hw2reg.cfg.key_swap.d = cfg_reg.key_swap.q;
Tests: T1 T2 T3
336
337 1/1 assign reg_hash_start = reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q;
Tests: T1 T2 T3
338 1/1 assign reg_hash_stop = reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q;
Tests: T1 T2 T3
339 1/1 assign reg_hash_continue = reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q;
Tests: T1 T2 T3
340 1/1 assign reg_hash_process = reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q;
Tests: T1 T2 T3
341
342 // Error code register
343 1/1 assign hw2reg.err_code.de = err_valid;
Tests: T1 T2 T3
344 1/1 assign hw2reg.err_code.d = err_code;
Tests: T1 T2 T3
345
346 /////////////////////
347 // Control signals //
348 /////////////////////
349 1/1 assign hash_start = reg_hash_start & sha_en & ~cfg_block & ~invalid_config;
Tests: T1 T2 T3
350 1/1 assign hash_continue = reg_hash_continue & sha_en & ~cfg_block & ~invalid_config;
Tests: T1 T2 T3
351 1/1 assign hash_process = reg_hash_process & sha_en & cfg_block & ~invalid_config;
Tests: T1 T2 T3
352 1/1 assign hash_start_or_continue = hash_start | hash_continue;
Tests: T1 T4 T5
353
354 always_ff @(posedge clk_i or negedge rst_ni) begin
355 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
356 1/1 cfg_block <= '0;
Tests: T1 T2 T3
357 1/1 end else if (hash_start_or_continue) begin
Tests: T1 T2 T3
358 1/1 cfg_block <= 1'b 1;
Tests: T1 T4 T5
359 1/1 end else if (reg_hash_done || reg_hash_stop) begin
Tests: T1 T2 T3
360 1/1 cfg_block <= 1'b 0;
Tests: T1 T4 T5
361 end
MISSING_ELSE
362 end
363 // Hold the configuration during the process
364 always_ff @(posedge clk_i or negedge rst_ni) begin
365 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
366 1/1 cfg_reg <= '{
Tests: T1 T2 T3
367 hmac_en: '{
368 q: 1'b0,
369 qe: 1'b0
370 },
371 sha_en: '{
372 q: 1'b0,
373 qe: 1'b0
374 },
375 endian_swap: '{
376 q: HMAC_CFG_ENDIAN_SWAP_RESVAL,
377 qe: 1'b0
378 },
379 digest_swap: '{
380 q: HMAC_CFG_DIGEST_SWAP_RESVAL,
381 qe: 1'b0
382 },
383 key_swap: '{
384 q: HMAC_CFG_KEY_SWAP_RESVAL,
385 qe: 1'b0
386 },
387 digest_size: '{
388 q: HMAC_CFG_DIGEST_SIZE_RESVAL,
389 qe: 1'b0
390 },
391 key_length: '{
392 q: HMAC_CFG_KEY_LENGTH_RESVAL,
393 qe: 1'b0
394 },
395 default:'0
396 };
397 1/1 end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
Tests: T1 T2 T3
398 1/1 cfg_reg <= reg2hw.cfg ;
Tests: T1 T4 T5
399 end
MISSING_ELSE
400 end
401
402 // Open up the MSG_FIFO from the TL-UL port when it is ready
403 always_ff @(posedge clk_i or negedge rst_ni) begin
404 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
405 1/1 msg_allowed <= '0;
Tests: T1 T2 T3
406 1/1 end else if (hash_start_or_continue) begin
Tests: T1 T2 T3
407 1/1 msg_allowed <= 1'b 1;
Tests: T1 T4 T5
408 1/1 end else if (packer_flush_done) begin
Tests: T1 T2 T3
409 1/1 msg_allowed <= 1'b 0;
Tests: T1 T4 T5
410 end
MISSING_ELSE
411 end
412
413 ////////////////
414 // Interrupts //
415 ////////////////
416
417 // instantiate interrupt hardware primitive
418 prim_intr_hw #(.Width(1)) intr_hw_hmac_done (
419 .clk_i,
420 .rst_ni,
421 .event_intr_i (hash_done_event),
422 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_done.q),
423 .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_done.q),
424 .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_done.qe),
425 .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_done.q),
426 .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_done.de),
427 .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_done.d),
428 .intr_o (intr_hmac_done_o)
429 );
430
431 // FIFO empty interrupt
432 //
433 // The FIFO empty interrupt is **not useful** for software if:
434 // - The HMAC block is running in HMAC mode and performing the second round of computing the
435 // final hash of the outer key as well as the result of the first round using the inner key.
436 // The FIFO is then managed entirely by the hardware.
437 // - The FIFO is currently not writeable by software.
438 // - Software has already written the Process command. The HMAC block will now empty the
439 // FIFO and load its content into the SHA2 core, add the padding and then perfom
440 // the final hashing operation. Software cannot append the message further.
441 // - Software has written the Stop command. The HMAC block will not wait for further input from
442 // software after finishing the current block.
443 //
444 // The FIFO empty interrupt can be **useful** for software in particular if:
445 // - The FIFO was completely full previously. However, unless the HMAC block is currently
446 // processing a block, it always empties the message FIFO faster than software can fill it up,
447 // meaning the message FIFO is empty most of the time. Note, the empty status is signaled only
448 // once after the FIFO was completely full. The FIFO needs to be full again for the empty
449 // status to be signaled again next time it's empty.
450 logic status_fifo_empty, fifo_empty_gate;
451 logic fifo_empty_negedge, fifo_empty_q;
452 logic fifo_full_posedge, fifo_full_q;
453 logic fifo_full_seen_d, fifo_full_seen_q;
454 1/1 assign fifo_empty_negedge = fifo_empty_q & ~fifo_empty;
Tests: T1 T2 T3
455 1/1 assign fifo_full_posedge = ~fifo_full_q & fifo_full;
Tests: T1 T2 T3
456
457 // Track whether the FIFO was full after being empty. We clear the tracking:
458 // - When receiving the Start, Continue, Process or Stop command. This is to start over for the
459 // next message.
460 // - When seeing a negative edge on the empty signal. This signals that software has reacted to
461 // the interrupt and is filling up the FIFO again.
462 1/1 assign fifo_full_seen_d =
Tests: T1 T2 T3
463 reg_hash_start || reg_hash_continue ||
464 reg_hash_process || reg_hash_stop ? 1'b 0 :
465 fifo_empty_negedge ? 1'b 0 :
466 fifo_full_posedge ? 1'b 1 : fifo_full_seen_q;
467
468 // The interrupt is gated unless software is actually allowed to write the FIFO and the FIFO was
469 // full before.
470 1/1 assign fifo_empty_gate = ~msg_allowed || ~fifo_full_seen_q;
Tests: T1 T2 T3
471
472 1/1 assign status_fifo_empty = fifo_empty_gate ? 1'b 0 : fifo_empty;
Tests: T1 T2 T3
473
474 always_ff @(posedge clk_i or negedge rst_ni) begin
475 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
476 1/1 fifo_empty_q <= 1'b 0;
Tests: T1 T2 T3
477 1/1 fifo_full_q <= 1'b 0;
Tests: T1 T2 T3
478 1/1 fifo_full_seen_q <= 1'b 0;
Tests: T1 T2 T3
479 end else begin
480 1/1 fifo_empty_q <= fifo_empty;
Tests: T1 T2 T3
481 1/1 fifo_full_q <= fifo_full;
Tests: T1 T2 T3
482 1/1 fifo_full_seen_q <= fifo_full_seen_d;
Tests: T1 T2 T3
483 end
484 end
485
486 prim_intr_hw #(
487 .Width(1),
488 .IntrT("Status")
489 ) intr_hw_fifo_empty (
490 .clk_i,
491 .rst_ni,
492 .event_intr_i (status_fifo_empty),
493 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q),
494 .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q),
495 .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe),
496 .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q),
497 .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de),
498 .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d),
499 .intr_o (intr_fifo_empty_o)
500 );
501 prim_intr_hw #(.Width(1)) intr_hw_hmac_err (
502 .clk_i,
503 .rst_ni,
504 .event_intr_i (err_valid),
505 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_err.q),
506 .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_err.q),
507 .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_err.qe),
508 .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_err.q),
509 .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_err.de),
510 .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_err.d),
511 .intr_o (intr_hmac_err_o)
512 );
513
514 ///////////////
515 // Instances //
516 ///////////////
517
518 1/1 assign msg_fifo_rvalid = msg_fifo_req & ~msg_fifo_we;
Tests: T1 T2 T3
519 assign msg_fifo_rdata = '1; // Return all F
520 assign msg_fifo_rerror = '1; // Return error for read access
521 1/1 assign msg_fifo_gnt = msg_fifo_req & ~hmac_fifo_wsel & packer_ready;
Tests: T1 T2 T3
522
523 /////////////////////
524 // Unused Signals //
525 /////////////////////
526 logic unused_signals;
527 1/1 assign unused_signals = ^{reg_fifo_wmask[7:1], reg_fifo_wmask[15:9],
Tests: T1 T2 T3
528 reg_fifo_wmask[23:17], reg_fifo_wmask[31:25]};
529
530 // FIFO control: from packer into message FIFO
531 sha_fifo32_t reg_fifo_wentry;
532 1/1 assign reg_fifo_wentry.data = conv_endian32(reg_fifo_wdata, 1'b1); // always convert
Tests: T1 T2 T3
533 1/1 assign reg_fifo_wentry.mask = {reg_fifo_wmask[0], reg_fifo_wmask[8],
Tests: T1 T2 T3
534 reg_fifo_wmask[16], reg_fifo_wmask[24]};
535 1/1 assign fifo_full = ~fifo_wready;
Tests: T1 T2 T3
536 1/1 assign fifo_empty = ~fifo_rvalid;
Tests: T1 T2 T3
537 1/1 assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
Tests: T1 T2 T3
538
539 logic index;
540 always_comb begin : select_fifo_wdata
541 // default when !hmac_fifo_wsel
542 1/1 index = 1'b0;
Tests: T1 T2 T3
543 1/1 fifo_wdata = reg_fifo_wentry;
Tests: T1 T2 T3
544
545 1/1 if (hmac_fifo_wsel) begin
Tests: T1 T2 T3
546 1/1 fifo_wdata = '0;
Tests: T1 T4 T5
547 1/1 if (digest_size == SHA2_256) begin
Tests: T1 T4 T5
548 // only reads out lower 32 bits of each digest word and discards upper 32-bit zero padding
549 1/1 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel[2:0]][31:0], mask: '1};
Tests: T6 T8 T10
550 1/1 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
Tests: T1 T4 T5
551 // reads out first upper 32 bits then lower 32 bits of each digest word
552 1/1 index = !hmac_fifo_wdata_sel[0];
Tests: T1 T4 T5
553 1/1 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel >> 1][32*index+:32], mask: '1};
Tests: T1 T4 T5
554 end
==> MISSING_ELSE
555 end
MISSING_ELSE
556 end
557
558 // Extended for 1024-bit block
559 localparam int MsgFifoDepth = 32;
560 prim_fifo_sync #(
561 .Width ($bits(sha_fifo32_t)),
562 .Pass (1'b1),
563 .Depth (MsgFifoDepth)
564 ) u_msg_fifo (
565 .clk_i,
566 .rst_ni,
567 .clr_i (1'b0),
568
569 .wvalid_i(fifo_wvalid & sha_en),
570 .wready_o(fifo_wready),
571 .wdata_i (fifo_wdata),
572
573 .depth_o (fifo_depth),
574 .full_o (),
575
576 .rvalid_o(fifo_rvalid),
577 .rready_i(fifo_rready),
578 .rdata_o (fifo_rdata),
579 .err_o ()
580 );
581
582 // TL ADAPTER SRAM
583 tlul_adapter_sram #(
584 .SramAw (9),
585 .SramDw (32),
586 .Outstanding (1),
587 .ByteAccess (1),
588 .ErrOnRead (1)
589 ) u_tlul_adapter (
590 .clk_i,
591 .rst_ni,
592 .tl_i (tl_win_h2d),
593 .tl_o (tl_win_d2h),
594 .en_ifetch_i (prim_mubi_pkg::MuBi4False),
595 .req_o (msg_fifo_req ),
596 .req_type_o ( ),
597 .gnt_i (msg_fifo_gnt ),
598 .we_o (msg_fifo_we ),
599 .addr_o ( ), // Doesn't care the address
600 // other than sub-word
601 .wdata_o (msg_fifo_wdata ),
602 .wmask_o (msg_fifo_wmask ),
603 .intg_error_o ( ),
604 .rdata_i (msg_fifo_rdata ),
605 .rvalid_i (msg_fifo_rvalid),
606 .rerror_i (msg_fifo_rerror),
607 .compound_txn_in_progress_o (),
608 .readback_en_i (prim_mubi_pkg::MuBi4False),
609 .readback_error_o (),
610 .wr_collision_i (1'b0),
611 .write_pending_i (1'b0)
612 );
613
614 // TL-UL to MSG_FIFO byte write handling
615 logic msg_write;
616
617 1/1 assign msg_write = msg_fifo_req & msg_fifo_we & ~hmac_fifo_wsel & msg_allowed;
Tests: T1 T2 T3
618
619 logic [$clog2(32+1)-1:0] wmask_ones;
620
621 always_comb begin
622 1/1 wmask_ones = '0;
Tests: T1 T2 T3
623 1/1 for (int i = 0 ; i < 32 ; i++) begin
Tests: T1 T2 T3
624 1/1 wmask_ones = wmask_ones + msg_fifo_wmask[i];
Tests: T1 T2 T3
625 end
626 end
627
628 // Calculate written message
629 always_ff @(posedge clk_i or negedge rst_ni) begin
630 2/2 if (!rst_ni) message_length <= '0;
Tests: T1 T2 T3 | T1 T2 T3
631 1/1 else message_length <= message_length_d;
Tests: T1 T2 T3
632 end
633
634 always_comb begin
635 1/1 message_length_d = message_length;
Tests: T1 T2 T3
636 1/1 if (!cfg_block) begin
Tests: T1 T2 T3
637 1/1 if (reg2hw.msg_length_lower.qe) begin
Tests: T1 T2 T3
638 1/1 message_length_d[31:0] = reg2hw.msg_length_lower.q;
Tests: T7 T8 T10
639 end
MISSING_ELSE
640 1/1 if (reg2hw.msg_length_upper.qe) begin
Tests: T1 T2 T3
641 1/1 message_length_d[63:32] = reg2hw.msg_length_upper.q;
Tests: T7 T8 T10
642 end
MISSING_ELSE
643 end
MISSING_ELSE
644
645 1/1 if (hash_start) begin
Tests: T1 T2 T3
646 1/1 message_length_d = '0;
Tests: T1 T4 T5
647 1/1 end else if (msg_write && sha_en && packer_ready) begin
Tests: T1 T2 T3
648 1/1 message_length_d = message_length + 64'(wmask_ones);
Tests: T1 T4 T5
649 end
MISSING_ELSE
650 end
651
652 1/1 assign hw2reg.msg_length_upper.d = message_length[63:32];
Tests: T1 T2 T3
653 1/1 assign hw2reg.msg_length_lower.d = message_length[31:0];
Tests: T1 T2 T3
654
655 // Convert endian here
656 // prim_packer always packs to the right, but SHA engine assumes incoming
657 // to be big-endian, [31:24] comes first. So, the data is reverted after
658 // prim_packer before the message fifo. here to reverse if not big-endian
659 // before pushing to the packer.
660 1/1 assign msg_fifo_wdata_endian = conv_endian32(msg_fifo_wdata, endian_swap);
Tests: T1 T2 T3
661 1/1 assign msg_fifo_wmask_endian = conv_endian32(msg_fifo_wmask, endian_swap);
Tests: T1 T2 T3
662
663 prim_packer #(
664 .InW (32),
665 .OutW (32),
666 .EnProtection (1'b 0)
667 ) u_packer (
668 .clk_i,
669 .rst_ni,
670
671 .valid_i (msg_write & sha_en),
672 .data_i (msg_fifo_wdata_endian),
673 .mask_i (msg_fifo_wmask_endian),
674 .ready_o (packer_ready),
675
676 .valid_o (reg_fifo_wvalid),
677 .data_o (reg_fifo_wdata),
678 .mask_o (reg_fifo_wmask),
679 .ready_i (fifo_wready & ~hmac_fifo_wsel),
680
681 .flush_i (hash_process),
682 .flush_done_o (packer_flush_done), // ignore at this moment
683
684 .err_o () // Not used
685 );
686
687 hmac_core u_hmac (
688 .clk_i,
689 .rst_ni,
690 .secret_key_i (secret_key),
691 .hmac_en_i (hmac_en),
692 .digest_size_i (digest_size),
693 .key_length_i (key_length),
694
695 .reg_hash_start_i (hash_start),
696 .reg_hash_stop_i (reg_hash_stop),
697 .reg_hash_continue_i (hash_continue),
698 .reg_hash_process_i (packer_flush_done), // Trigger after all msg written
699 .hash_done_o (reg_hash_done),
700 .sha_hash_start_o (sha_hash_start),
701 .sha_hash_continue_o (sha_hash_continue),
702 .sha_hash_process_o (sha_hash_process),
703 .sha_hash_done_i (sha_hash_done),
704
705 .sha_rvalid_o (shaf_rvalid),
706 .sha_rdata_o (shaf_rdata),
707 .sha_rready_i (shaf_rready),
708
709 .fifo_rvalid_i (fifo_rvalid),
710 .fifo_rdata_i (fifo_rdata),
711 .fifo_rready_o (fifo_rready),
712
713 .fifo_wsel_o (hmac_fifo_wsel),
714 .fifo_wvalid_o (hmac_fifo_wvalid),
715 .fifo_wdata_sel_o (hmac_fifo_wdata_sel),
716 .fifo_wready_i (fifo_wready),
717
718 .message_length_i (message_length),
719 .sha_message_length_o (sha_message_length),
720
721 .idle_o (hmac_core_idle)
722 );
723
724 // Instantiate SHA-2 256/384/512 engine
725 prim_sha2_32 #(
726 .MultimodeEn(1)
727 ) u_prim_sha2_512 (
728 .clk_i,
729 .rst_ni,
730 .wipe_secret_i (wipe_secret),
731 .wipe_v_i (wipe_v),
732 .fifo_rvalid_i (shaf_rvalid),
733 .fifo_rdata_i (shaf_rdata),
734 .fifo_rready_o (shaf_rready),
735 .sha_en_i (sha_en),
736 .hash_start_i (sha_hash_start),
737 .hash_stop_i (reg_hash_stop),
738 .hash_continue_i (sha_hash_continue),
739 .digest_mode_i (digest_size),
740 .hash_process_i (sha_hash_process),
741 .message_length_i (sha_message_length),
742 .digest_i (digest_sw),
743 .digest_we_i (digest_sw_we),
744 .digest_o (digest),
745 .hash_running_o (hash_running),
746 .digest_on_blk_o (digest_on_blk),
747 .hash_done_o (sha_hash_done),
748 .idle_o (sha_core_idle)
749 );
750
751 // Register top
752 logic [NumAlerts-1:0] alert_test, alerts;
753 hmac_reg_top u_reg (
754 .clk_i,
755 .rst_ni,
756
757 .tl_i,
758 .tl_o,
759
760 .tl_win_o (tl_win_h2d),
761 .tl_win_i (tl_win_d2h),
762
763 .reg2hw,
764 .hw2reg,
765
766 // SEC_CM: BUS.INTEGRITY
767 .intg_err_o (alerts[0])
768 );
769
770 // Alerts
771 1/1 assign alert_test = {
Tests: T1 T2 T3
772 reg2hw.alert_test.q &
773 reg2hw.alert_test.qe
774 };
775
776 localparam logic [NumAlerts-1:0] AlertIsFatal = {1'b1};
777 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
778 prim_alert_sender #(
779 .AsyncOn(AlertAsyncOn[i]),
780 .IsFatal(AlertIsFatal[i])
781 ) u_prim_alert_sender (
782 .clk_i,
783 .rst_ni,
784 .alert_test_i ( alert_test[i] ),
785 .alert_req_i ( alerts[0] ),
786 .alert_ack_o ( ),
787 .alert_state_o ( ),
788 .alert_rx_i ( alert_rx_i[i] ),
789 .alert_tx_o ( alert_tx_o[i] )
790 );
791 end
792
793 /////////////////////////
794 // HMAC Error Handling //
795 /////////////////////////
796 logic hash_start_sha_disabled, update_seckey_inprocess;
797 logic hash_start_active; // `reg_hash_start` or `reg_hash_continue` set when hash already active
798 logic msg_push_not_allowed; // Message is received when `hash_start_or_continue` isn't set
799
800 1/1 assign hash_start_sha_disabled = (reg_hash_start | reg_hash_continue) & ~sha_en;
Tests: T1 T2 T3
801 1/1 assign hash_start_active = (reg_hash_start | reg_hash_continue) & cfg_block;
Tests: T1 T2 T3
802 1/1 assign msg_push_not_allowed = msg_fifo_req & ~msg_allowed;
Tests: T1 T2 T3
803
804 // Invalid/unconfigured HMAC/SHA-2: not configured/invalid digest size or
805 // not configured/invalid key length for HMAC mode or
806 // key_length = 1024-bit for digest_size = SHA2_256 (max 512-bit is supported for SHA-2 256)
807 1/1 assign invalid_config = ((digest_size == SHA2_None) |
Tests: T1 T2 T3
808 ((key_length == Key_None) && hmac_en) |
809 ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en));
810
811 // invalid_config at reg_hash_start or reg_hash_continue will signal an error to the SW
812 1/1 assign invalid_config_atstart = (reg_hash_start || reg_hash_continue) & invalid_config;
Tests: T1 T2 T3
813
814 always_comb begin
815 1/1 update_seckey_inprocess = 1'b0;
Tests: T1 T2 T3
816 1/1 if (cfg_block) begin
Tests: T1 T2 T3
817 1/1 for (int i = 0 ; i < 32 ; i++) begin
Tests: T1 T4 T5
818 1/1 if (reg2hw.key[i].qe) begin
Tests: T1 T4 T5
819 1/1 update_seckey_inprocess = update_seckey_inprocess | 1'b1;
Tests: T42 T43 T44
820 end
MISSING_ELSE
821 end
822 end else begin
823 1/1 update_seckey_inprocess = 1'b0;
Tests: T1 T2 T3
824 end
825 end
826
827 // Update ERR_CODE register and interrupt only when no pending interrupt.
828 // This ensures only the first event of the series of events can be seen to sw.
829 // It is recommended that the software reads ERR_CODE register when interrupt
830 // is pending to avoid any race conditions.
831 1/1 assign err_valid = ~reg2hw.intr_state.hmac_err.q &
Tests: T1 T2 T3
832 ( hash_start_sha_disabled | update_seckey_inprocess
833 | hash_start_active | msg_push_not_allowed | invalid_config_atstart);
834
835 always_comb begin
836 // default
837 1/1 err_code = NoError;
Tests: T1 T2 T3
838
839 1/1 priority case (1'b1)
Tests: T1 T2 T3
840 // SwInvalidConfig has the highest priority: SW configures HMAC incorrectly
841 invalid_config_atstart: begin
842 1/1 err_code = SwInvalidConfig;
Tests: T1 T4 T5
843 end
844
845 hash_start_sha_disabled: begin
846 1/1 err_code = SwHashStartWhenShaDisabled;
Tests: T45 T46 T47
847 end
848
849 hash_start_active: begin
850 1/1 err_code = SwHashStartWhenActive;
Tests: T46 T47 T48
851 end
852
853 msg_push_not_allowed: begin
854 1/1 err_code = SwPushMsgWhenDisallowed;
Tests: T1 T4 T5
855 end
856
857 update_seckey_inprocess: begin
858 1/1 err_code = SwUpdateSecretKeyInProcess;
Tests: T42 T43 T44
859 end
860
861 default: begin
862 err_code = NoError;
863 end
864 endcase
865 end
866
867 /////////////////////
868 // Idle output //
869 /////////////////////
870 // TBD this should be connected later
871 // Idle: AND condition of:
872 // - packer empty: Currently no way to guarantee the packer is empty.
873 // temporary, the logic uses packer output (reg_fifo_wvalid)
874 // - MSG_FIFO --> fifo_rvalid
875 // - HMAC_CORE --> hmac_core_idle
876 // - SHA2_CORE --> sha_core_idle
877 // - Clean interrupt status
878 // ICEBOX(#12958): Revise prim_packer and replace `reg_fifo_wvalid` to the
879 // empty status.
880 1/1 assign idle = !reg_fifo_wvalid && !fifo_rvalid
Tests: T1 T2 T3
881 && hmac_core_idle && sha_core_idle;
882
883 prim_mubi_pkg::mubi4_t idle_q, idle_d;
884 1/1 assign idle_d = prim_mubi_pkg::mubi4_bool_to_mubi(idle);
Tests: T1 T2 T3
885 always_ff @(posedge clk_i or negedge rst_ni) begin
886 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
887 1/1 idle_q <= prim_mubi_pkg::MuBi4False;
Tests: T1 T2 T3
888 end else begin
889 1/1 idle_q <= idle_d;
Tests: T1 T2 T3
890 end
891 end
892 1/1 assign idle_o = idle_q;
Tests: T1 T2 T3
893
894 //////////////////////////////////////////////
895 // Assertions, Assumptions, and Coverpoints //
896 //////////////////////////////////////////////
897
898 `ifndef VERILATOR
899 `ifndef SYNTHESIS
900 // HMAC assumes TL-UL mask is byte-aligned.
901 property wmask_bytealign_p(wmask_byte, clk, rst_n);
902 @(posedge clk) disable iff (rst_n == 0)
903 msg_fifo_req & msg_fifo_we |-> wmask_byte inside {'0, '1};
904 endproperty
905
906 for (genvar i = 0 ; i < 4; i++) begin: gen_assert_wmask_bytealign
907 assert property (wmask_bytealign_p(msg_fifo_wmask[8*i+:8], clk_i, rst_ni));
908 end
909
910 // To pass FPV, this shouldn't add pragma translate_off even these two signals
911 // are used in Assertion only
912 logic in_process;
913 always_ff @(posedge clk_i or negedge rst_ni) begin
914 2/2 if (!rst_ni) in_process <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
915 2/2 else if (hash_process || reg_hash_stop) in_process <= 1'b1;
Tests: T1 T2 T3 | T1 T4 T5
916 2/2 else if (reg_hash_done) in_process <= 1'b0;
Tests: T1 T2 T3 | T1 T4 T5
MISSING_ELSE
917 end
918
919 logic initiated;
920 always_ff @(posedge clk_i or negedge rst_ni) begin
921 2/2 if (!rst_ni) initiated <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
922 2/2 else if (hash_start_or_continue) initiated <= 1'b1;
Tests: T1 T2 T3 | T1 T4 T5
923 2/2 else if (hash_process || reg_hash_stop) initiated <= 1'b0;
Tests: T1 T2 T3 | T1 T4 T5
MISSING_ELSE
Cond Coverage for Module :
hmac
| Total | Covered | Percent |
|---|
| Conditions | 185 | 168 | 90.81 |
| Logical | 185 | 168 | 90.81 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 240
EXPRESSION (digest_size == SHA2_256)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T7 |
LINE 244
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T5,T6,T7 |
LINE 244
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 244
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 246
EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T8,T13,T49 |
LINE 249
EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T8,T13,T49 |
LINE 252
EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
------------1------------ ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T4,T5 |
| 0 | 1 | Covered | T8,T13,T49 |
| 1 | 0 | Covered | T8,T13,T49 |
LINE 256
EXPRESSION (digest_size_started_q == SHA2_256)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T7 |
LINE 262
EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
-----------------1----------------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T6,T7,T10 |
LINE 262
SUB-EXPRESSION (digest_size_started_q == SHA2_384)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T7,T10 |
LINE 262
SUB-EXPRESSION (digest_size_started_q == SHA2_512)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 301
EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 337
EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 338
EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T4,T7,T8 |
LINE 339
EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
-------------1------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T4,T7,T8 |
LINE 340
EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
-------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 349
EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
-------1------ ---2-- -------3------ ---------4---------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Covered | T45,T46,T47 |
| 1 | 1 | 0 | 1 | Covered | T46,T47,T48 |
| 1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 350
EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
--------1-------- ---2-- -------3------ ---------4---------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T4,T7,T8 |
LINE 351
EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
--------1------- ---2-- ----3---- ---------4---------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 352
EXPRESSION (hash_start | hash_continue)
-----1---- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 359
EXPRESSION (reg_hash_done || reg_hash_stop)
------1------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 397
EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T50,T51 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 454
EXPRESSION (fifo_empty_q & ((~fifo_empty)))
------1----- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 455
EXPRESSION (((~fifo_full_q)) & fifo_full)
--------1------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T13,T17 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 462
EXPRESSION
Number Term
1 (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 462
SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
-------1------ --------2-------- --------3------- ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T4,T7,T8 |
| 0 | 0 | 1 | 0 | Covered | T1,T4,T5 |
| 0 | 1 | 0 | 0 | Covered | T4,T7,T8 |
| 1 | 0 | 0 | 0 | Covered | T1,T4,T5 |
LINE 462
SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 462
SUB-EXPRESSION (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 470
EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
--------1------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T13,T17 |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 472
EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T11,T13,T17 |
| 1 | Covered | T1,T2,T3 |
LINE 518
EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Not Covered | |
LINE 521
EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
------1----- ---------2--------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Unreachable | T21,T22,T23 |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 537
EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 537
SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
-------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 547
EXPRESSION (digest_size == SHA2_256)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T6,T8,T10 |
LINE 550
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T6,T10,T9 |
LINE 550
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T6,T10,T9 |
LINE 550
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T10,T9 |
| 1 | Covered | T1,T4,T5 |
LINE 564
EXPRESSION (fifo_wvalid & sha_en)
-----1----- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 617
EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
------1----- -----2----- ---------3--------- -----4-----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 647
EXPRESSION (msg_write && sha_en && packer_ready)
----1---- ---2-- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Unreachable | T21,T22,T23 |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 667
EXPRESSION (msg_write & sha_en)
----1---- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 667
EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
-----1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 771
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T25,T52 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T25,T52 |
LINE 800
EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
------------------1----------------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T42,T45,T46 |
LINE 800
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 801
EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
------------------1----------------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T46,T47,T48 |
LINE 801
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 802
EXPRESSION (msg_fifo_req & ((~msg_allowed)))
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 807
EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
-------------1------------ ------------------2------------------ ---------------------------------3--------------------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 1 | Covered | T1,T8,T9 |
| 0 | 1 | 0 | Covered | T1,T5,T6 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 807
SUB-EXPRESSION (digest_size == SHA2_None)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 807
SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
------------1----------- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 807
SUB-EXPRESSION (key_length == Key_None)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 807
SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
------------1----------- ------------2------------ ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T6,T8 |
| 1 | 0 | 1 | Covered | T1,T7,T10 |
| 1 | 1 | 0 | Covered | T7,T9,T11 |
| 1 | 1 | 1 | Covered | T1,T8,T9 |
LINE 807
SUB-EXPRESSION (key_length == Key_1024)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T7 |
LINE 807
SUB-EXPRESSION (digest_size == SHA2_256)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T7 |
LINE 812
EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
------------------1------------------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 812
SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 831
EXPRESSION
Number Term
1 ((~reg2hw.intr_state.hmac_err.q)) &
2 (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 831
SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
-----------1----------- -----------2----------- --------3-------- ----------4--------- -----------5----------
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 1 | Covered | T1,T4,T5 |
| 0 | 0 | 0 | 1 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 1 | 0 | 0 | Covered | T46,T47,T48 |
| 0 | 1 | 0 | 0 | 0 | Covered | T42,T43,T44 |
| 1 | 0 | 0 | 0 | 0 | Covered | T45,T46,T47 |
LINE 880
EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
----------1--------- --------2------- -------3------ ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 915
EXPRESSION (hash_process || reg_hash_stop)
------1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 923
EXPRESSION (hash_process || reg_hash_stop)
------1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
Toggle Coverage for Module :
hmac
| Total | Covered | Percent |
| Totals |
30 |
30 |
100.00 |
| Total Bits |
346 |
346 |
100.00 |
| Total Bits 0->1 |
173 |
173 |
100.00 |
| Total Bits 1->0 |
173 |
173 |
100.00 |
| | | |
| Ports |
30 |
30 |
100.00 |
| Port Bits |
346 |
346 |
100.00 |
| Port Bits 0->1 |
173 |
173 |
100.00 |
| Port Bits 1->0 |
173 |
173 |
100.00 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_ni |
Yes |
Yes |
T3,T24,T53 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.d_ready |
Yes |
Yes |
T3,T24,T4 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T25,T6 |
Yes |
T1,T25,T6 |
INPUT |
| tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
| tl_i.a_address[31:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
| tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_size[1:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
| tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_error |
Yes |
Yes |
T14,T18,T19 |
Yes |
T14,T18,T19 |
OUTPUT |
| tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T4 |
OUTPUT |
| tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T4,T5 |
OUTPUT |
| tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_size[1:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T4 |
Yes |
T1,T2,T4 |
OUTPUT |
| tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T3,T24 |
Yes |
T2,T3,T24 |
INPUT |
| alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T3,T24 |
Yes |
T2,T3,T24 |
OUTPUT |
| intr_hmac_done_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| intr_fifo_empty_o |
Yes |
Yes |
T11,T13,T14 |
Yes |
T11,T13,T14 |
OUTPUT |
| intr_hmac_err_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T24 |
OUTPUT |
*Tests covering at least one bit in the range
FSM Coverage for Module :
hmac
Summary for FSM :: done_state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
5 |
5 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: done_state_q
| states | Line No. | Covered | Tests |
| DoneAwaitCmd |
167 |
Covered |
T1,T2,T3 |
| DoneAwaitHashComplete |
176 |
Covered |
T4,T7,T8 |
| DoneAwaitHashDone |
157 |
Covered |
T1,T4,T5 |
| DoneAwaitMessageComplete |
160 |
Covered |
T4,T7,T8 |
| transitions | Line No. | Covered | Tests |
| DoneAwaitCmd->DoneAwaitHashDone |
157 |
Covered |
T1,T4,T5 |
| DoneAwaitCmd->DoneAwaitMessageComplete |
160 |
Covered |
T4,T7,T8 |
| DoneAwaitHashComplete->DoneAwaitCmd |
183 |
Covered |
T4,T7,T8 |
| DoneAwaitHashDone->DoneAwaitCmd |
167 |
Covered |
T1,T4,T5 |
| DoneAwaitMessageComplete->DoneAwaitHashComplete |
176 |
Covered |
T4,T7,T8 |
Branch Coverage for Module :
hmac
| Line No. | Total | Covered | Percent |
| Branches |
|
93 |
90 |
96.77 |
| TERNARY |
301 |
2 |
2 |
100.00 |
| TERNARY |
462 |
4 |
4 |
100.00 |
| TERNARY |
472 |
2 |
2 |
100.00 |
| TERNARY |
537 |
2 |
2 |
100.00 |
| CASE |
153 |
10 |
8 |
80.00 |
| IF |
192 |
2 |
2 |
100.00 |
| IF |
205 |
3 |
3 |
100.00 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
240 |
6 |
6 |
100.00 |
| IF |
256 |
3 |
3 |
100.00 |
| CASE |
289 |
4 |
4 |
100.00 |
| IF |
304 |
2 |
2 |
100.00 |
| CASE |
312 |
6 |
6 |
100.00 |
| IF |
355 |
4 |
4 |
100.00 |
| IF |
365 |
3 |
3 |
100.00 |
| IF |
404 |
4 |
4 |
100.00 |
| IF |
475 |
2 |
2 |
100.00 |
| IF |
545 |
4 |
3 |
75.00 |
| IF |
630 |
2 |
2 |
100.00 |
| IF |
636 |
5 |
5 |
100.00 |
| IF |
645 |
3 |
3 |
100.00 |
| IF |
816 |
2 |
2 |
100.00 |
| CASE |
839 |
6 |
6 |
100.00 |
| IF |
886 |
2 |
2 |
100.00 |
| IF |
914 |
4 |
4 |
100.00 |
| IF |
921 |
4 |
4 |
100.00 |
301 assign digest_size_started_d = (hash_start_or_continue) ? digest_size : digest_size_started_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
462 assign fifo_full_seen_d =
463 reg_hash_start || reg_hash_continue ||
464 reg_hash_process || reg_hash_stop ? 1'b 0 :
-1-
==>
465 fifo_empty_negedge ? 1'b 0 :
-2-
==>
466 fifo_full_posedge ? 1'b 1 : fifo_full_seen_q;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
472 assign status_fifo_empty = fifo_empty_gate ? 1'b 0 : fifo_empty;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T11,T13,T17 |
537 assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
153 unique case (done_state_q)
-1-
154 DoneAwaitCmd: begin
155 if (sha_hash_process) begin
-2-
156 // SHA has been told to process the message, so signal *done* when the hash is done.
157 done_state_d = DoneAwaitHashDone;
==>
158 end else if (reg_hash_stop) begin
-3-
159 // SHA has been told to stop, so first wait for the current message block to be complete.
160 done_state_d = DoneAwaitMessageComplete;
==>
161 end
MISSING_ELSE
==>
162 end
163
164 DoneAwaitHashDone: begin
165 if (reg_hash_done) begin
-4-
166 hash_done_event = 1'b1;
==>
167 done_state_d = DoneAwaitCmd;
168 end
MISSING_ELSE
==>
169 end
170
171 DoneAwaitMessageComplete: begin
172 if (digest_on_blk) begin
-5-
173 // Once the digest is being computed for the complete message block, wait for the hash to
174 // complete.
175 // TODO (issue #21710): handle incomplete message size and check against 512 or 1024
176 done_state_d = DoneAwaitHashComplete;
==>
177 end
MISSING_ELSE
==>
178 end
179
180 DoneAwaitHashComplete: begin
181 if (!hash_running) begin
-6-
182 hash_done_event = 1'b1;
==>
183 done_state_d = DoneAwaitCmd;
184 end
MISSING_ELSE
==>
185 end
186
187 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| DoneAwaitCmd |
1 |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
| DoneAwaitCmd |
0 |
1 |
- |
- |
- |
Covered |
T4,T7,T8 |
| DoneAwaitCmd |
0 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| DoneAwaitHashDone |
- |
- |
1 |
- |
- |
Covered |
T1,T4,T5 |
| DoneAwaitHashDone |
- |
- |
0 |
- |
- |
Covered |
T1,T4,T5 |
| DoneAwaitMessageComplete |
- |
- |
- |
1 |
- |
Covered |
T4,T7,T8 |
| DoneAwaitMessageComplete |
- |
- |
- |
0 |
- |
Covered |
T4,T7,T8 |
| DoneAwaitHashComplete |
- |
- |
- |
- |
1 |
Covered |
T4,T7,T8 |
| DoneAwaitHashComplete |
- |
- |
- |
- |
0 |
Not Covered |
|
| default |
- |
- |
- |
- |
- |
Not Covered |
|
192 if (!rst_ni) begin
-1-
193 done_state_q <= DoneAwaitCmd;
==>
194 end else begin
195 done_state_q <= done_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
205 if (wipe_secret) begin
-1-
206 secret_key_d = {32{wipe_v}};
==>
207 end else if (!cfg_block) begin
-2-
208 // Allow updating secret key only when the engine is in Idle.
209 for (int i = 0; i < 32; i++) begin
==>
210 if (reg2hw.key[31-i].qe) begin
211 // swap byte endianness per secret key word if key_swap = 1
212 secret_key_d[32*i+:32] = conv_endian32(reg2hw.key[31-i].q, key_swap);
213 end
214 end
215 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T9,T12,T26 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T4,T5 |
219 if (!rst_ni) secret_key <= '0;
-1-
==>
220 else secret_key <= secret_key_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
240 if (digest_size == SHA2_256) begin
-1-
241 // digest SW -> HW
242 digest_sw[i][31:0] = conv_endian32(reg2hw.digest[i].q, digest_swap);
==>
243 digest_sw_we[i] = reg2hw.digest[i].qe;
244 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
-2-
245 // digest SW -> HW
246 digest_sw[i][63:32] = reg2hw.digest[2*i].qe ?
-3-
==>
==>
247 conv_endian32(reg2hw.digest[2*i].q, digest_swap) :
248 digest[i][63:32];
249 digest_sw[i][31:0] = reg2hw.digest[2*i+1].qe ?
-4-
==>
==>
250 conv_endian32(reg2hw.digest[2*i+1].q, digest_swap) :
251 digest[i][31:0];
252 digest_sw_we[i] = reg2hw.digest[2*i].qe | reg2hw.digest[2*i+1].qe;
253 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T6,T7 |
| 0 |
1 |
1 |
- |
Covered |
T8,T13,T49 |
| 0 |
1 |
0 |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
- |
1 |
Covered |
T8,T13,T49 |
| 0 |
1 |
- |
0 |
Covered |
T1,T4,T5 |
| 0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
256 if (digest_size_started_q == SHA2_256) begin
-1-
257 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
==>
258 // replicate digest[0..7] into digest[8..15]. Digest[8...15] are irrelevant for SHA2_256,
259 // but this ensures all digest CSRs are wiped out with random value (at wipe_secret)
260 // across different configurations.
261 hw2reg.digest[i+8].d = conv_endian32(digest[i][31:0], digest_swap);
262 end else if ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)) begin
-2-
263 // digest HW -> SW
264 // digest swap only within each 32-bit word of the 64-bit digest word, not digest swap
265 // on the entire 64-bit digest word
266 hw2reg.digest[2*i].d = conv_endian32(digest[i][63:32], digest_swap);
==>
267 hw2reg.digest[2*i+1].d = conv_endian32(digest[i][31:0], digest_swap);
268 end else begin // for SHA2_None
269 // to ensure secret wiping is always passed to digest CSRs
270 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T6,T7 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
289 unique case (digest_size_supplied)
-1-
290 SHA2_256: digest_size = SHA2_256;
==>
291 SHA2_384: digest_size = SHA2_384;
==>
292 SHA2_512: digest_size = SHA2_512;
==>
293 // unsupported digest size values are mapped to SHA2_None
294 // if HMAC/SHA-2 is triggered to start with this digest size, it is blocked
295 // and an error is signalled to SW
296 default: digest_size = SHA2_None;
==>
Branches:
| -1- | Status | Tests |
| SHA2_256 |
Covered |
T1,T6,T7 |
| SHA2_384 |
Covered |
T5,T6,T7 |
| SHA2_512 |
Covered |
T1,T4,T5 |
| default |
Covered |
T1,T2,T3 |
304 if (!rst_ni) digest_size_started_q <= SHA2_None;
-1-
==>
305 else digest_size_started_q <= digest_size_started_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
312 unique case (key_length_supplied)
-1-
313 Key_128: key_length = Key_128;
==>
314 Key_256: key_length = Key_256;
==>
315 Key_384: key_length = Key_384;
==>
316 Key_512: key_length = Key_512;
==>
317 Key_1024: key_length = Key_1024;
==>
318 // unsupported key length values are mapped to Key_None
319 // if HMAC (not SHA-2) is triggered to start with this key length, it is blocked
320 // and an error is signalled to SW
321 default: key_length = Key_None;
==>
Branches:
| -1- | Status | Tests |
| Key_128 |
Covered |
T1,T5,T6 |
| Key_256 |
Covered |
T1,T5,T6 |
| Key_384 |
Covered |
T1,T4,T6 |
| Key_512 |
Covered |
T1,T4,T5 |
| Key_1024 |
Covered |
T1,T4,T7 |
| default |
Covered |
T1,T2,T3 |
355 if (!rst_ni) begin
-1-
356 cfg_block <= '0;
==>
357 end else if (hash_start_or_continue) begin
-2-
358 cfg_block <= 1'b 1;
==>
359 end else if (reg_hash_done || reg_hash_stop) begin
-3-
360 cfg_block <= 1'b 0;
==>
361 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
365 if (!rst_ni) begin
-1-
366 cfg_reg <= '{
==>
367 hmac_en: '{
368 q: 1'b0,
369 qe: 1'b0
370 },
371 sha_en: '{
372 q: 1'b0,
373 qe: 1'b0
374 },
375 endian_swap: '{
376 q: HMAC_CFG_ENDIAN_SWAP_RESVAL,
377 qe: 1'b0
378 },
379 digest_swap: '{
380 q: HMAC_CFG_DIGEST_SWAP_RESVAL,
381 qe: 1'b0
382 },
383 key_swap: '{
384 q: HMAC_CFG_KEY_SWAP_RESVAL,
385 qe: 1'b0
386 },
387 digest_size: '{
388 q: HMAC_CFG_DIGEST_SIZE_RESVAL,
389 qe: 1'b0
390 },
391 key_length: '{
392 q: HMAC_CFG_KEY_LENGTH_RESVAL,
393 qe: 1'b0
394 },
395 default:'0
396 };
397 end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
-2-
398 cfg_reg <= reg2hw.cfg ;
==>
399 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
404 if (!rst_ni) begin
-1-
405 msg_allowed <= '0;
==>
406 end else if (hash_start_or_continue) begin
-2-
407 msg_allowed <= 1'b 1;
==>
408 end else if (packer_flush_done) begin
-3-
409 msg_allowed <= 1'b 0;
==>
410 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
475 if (!rst_ni) begin
-1-
476 fifo_empty_q <= 1'b 0;
==>
477 fifo_full_q <= 1'b 0;
478 fifo_full_seen_q <= 1'b 0;
479 end else begin
480 fifo_empty_q <= fifo_empty;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
545 if (hmac_fifo_wsel) begin
-1-
546 fifo_wdata = '0;
547 if (digest_size == SHA2_256) begin
-2-
548 // only reads out lower 32 bits of each digest word and discards upper 32-bit zero padding
549 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel[2:0]][31:0], mask: '1};
==>
550 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
-3-
551 // reads out first upper 32 bits then lower 32 bits of each digest word
552 index = !hmac_fifo_wdata_sel[0];
==>
553 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel >> 1][32*index+:32], mask: '1};
554 end
MISSING_ELSE
==>
555 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T6,T8,T10 |
| 1 |
0 |
1 |
Covered |
T1,T4,T5 |
| 1 |
0 |
0 |
Not Covered |
|
| 0 |
- |
- |
Covered |
T1,T2,T3 |
630 if (!rst_ni) message_length <= '0;
-1-
==>
631 else message_length <= message_length_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
636 if (!cfg_block) begin
-1-
637 if (reg2hw.msg_length_lower.qe) begin
-2-
638 message_length_d[31:0] = reg2hw.msg_length_lower.q;
==>
639 end
MISSING_ELSE
==>
640 if (reg2hw.msg_length_upper.qe) begin
-3-
641 message_length_d[63:32] = reg2hw.msg_length_upper.q;
==>
642 end
MISSING_ELSE
==>
643 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T7,T8,T10 |
| 1 |
0 |
- |
Covered |
T1,T2,T3 |
| 1 |
- |
1 |
Covered |
T7,T8,T10 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T4,T5 |
645 if (hash_start) begin
-1-
646 message_length_d = '0;
==>
647 end else if (msg_write && sha_en && packer_ready) begin
-2-
648 message_length_d = message_length + 64'(wmask_ones);
==>
649 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
816 if (cfg_block) begin
-1-
817 for (int i = 0 ; i < 32 ; i++) begin
==>
818 if (reg2hw.key[i].qe) begin
819 update_seckey_inprocess = update_seckey_inprocess | 1'b1;
820 end
821 end
822 end else begin
823 update_seckey_inprocess = 1'b0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
839 priority case (1'b1)
-1-
840 // SwInvalidConfig has the highest priority: SW configures HMAC incorrectly
841 invalid_config_atstart: begin
842 err_code = SwInvalidConfig;
==>
843 end
844
845 hash_start_sha_disabled: begin
846 err_code = SwHashStartWhenShaDisabled;
==>
847 end
848
849 hash_start_active: begin
850 err_code = SwHashStartWhenActive;
==>
851 end
852
853 msg_push_not_allowed: begin
854 err_code = SwPushMsgWhenDisallowed;
==>
855 end
856
857 update_seckey_inprocess: begin
858 err_code = SwUpdateSecretKeyInProcess;
==>
859 end
860
861 default: begin
862 err_code = NoError;
==>
Branches:
| -1- | Status | Tests |
| invalid_config_atstart |
Covered |
T1,T4,T5 |
| hash_start_sha_disabled |
Covered |
T45,T46,T47 |
| hash_start_active |
Covered |
T46,T47,T48 |
| msg_push_not_allowed |
Covered |
T1,T4,T5 |
| update_seckey_inprocess |
Covered |
T42,T43,T44 |
| default |
Covered |
T1,T2,T3 |
886 if (!rst_ni) begin
-1-
887 idle_q <= prim_mubi_pkg::MuBi4False;
==>
888 end else begin
889 idle_q <= idle_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
914 if (!rst_ni) in_process <= 1'b0;
-1-
==>
915 else if (hash_process || reg_hash_stop) in_process <= 1'b1;
-2-
==>
916 else if (reg_hash_done) in_process <= 1'b0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
921 if (!rst_ni) initiated <= 1'b0;
-1-
==>
922 else if (hash_start_or_continue) initiated <= 1'b1;
-2-
==>
923 else if (hash_process || reg_hash_stop) initiated <= 1'b0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
hmac
Assertion Details
AlertKnownO_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
80 |
0 |
0 |
| T3 |
3260 |
10 |
0 |
0 |
| T4 |
125683 |
0 |
0 |
0 |
| T5 |
21905 |
0 |
0 |
0 |
| T6 |
39136 |
0 |
0 |
0 |
| T7 |
10326 |
0 |
0 |
0 |
| T8 |
39861 |
0 |
0 |
0 |
| T9 |
64603 |
0 |
0 |
0 |
| T10 |
140485 |
0 |
0 |
0 |
| T24 |
7506 |
30 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
| T53 |
0 |
10 |
0 |
0 |
| T54 |
0 |
10 |
0 |
0 |
| T55 |
0 |
20 |
0 |
0 |
IntrFifoEmptyOKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
IntrHmacDoneOKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
TlOAReadyKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
TlODValidKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
ValidHashProcessAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17261 |
0 |
0 |
| T1 |
13682 |
7 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
4 |
0 |
0 |
| T5 |
21905 |
4 |
0 |
0 |
| T6 |
39136 |
10 |
0 |
0 |
| T7 |
10326 |
9 |
0 |
0 |
| T8 |
39861 |
10 |
0 |
0 |
| T9 |
0 |
8 |
0 |
0 |
| T10 |
0 |
11 |
0 |
0 |
| T11 |
0 |
18 |
0 |
0 |
| T12 |
0 |
3 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
ValidHmacEnConditionAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
9723 |
0 |
0 |
| T1 |
13682 |
11 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2 |
0 |
0 |
| T5 |
21905 |
2 |
0 |
0 |
| T6 |
39136 |
9 |
0 |
0 |
| T7 |
10326 |
8 |
0 |
0 |
| T8 |
39861 |
6 |
0 |
0 |
| T9 |
0 |
9 |
0 |
0 |
| T10 |
0 |
7 |
0 |
0 |
| T11 |
0 |
14 |
0 |
0 |
| T12 |
0 |
4 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
ValidWriteAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[0].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[1].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[2].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[3].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 198 | 198 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| ALWAYS | 150 | 15 | 15 | 100.00 |
| ALWAYS | 192 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 7 | 7 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
| ALWAYS | 231 | 19 | 19 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| ALWAYS | 287 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| ALWAYS | 304 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
| ALWAYS | 310 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 327 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 329 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 330 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 332 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 333 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 335 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 337 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 338 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 339 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 340 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 343 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 344 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 351 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 352 | 1 | 1 | 100.00 |
| ALWAYS | 355 | 6 | 6 | 100.00 |
| ALWAYS | 365 | 4 | 4 | 100.00 |
| ALWAYS | 404 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 455 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 462 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 472 | 1 | 1 | 100.00 |
| ALWAYS | 475 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 518 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 527 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 535 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
| ALWAYS | 542 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
| ALWAYS | 622 | 3 | 3 | 100.00 |
| ALWAYS | 630 | 3 | 3 | 100.00 |
| ALWAYS | 635 | 10 | 10 | 100.00 |
| CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 653 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 660 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 661 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 771 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 801 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 802 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 807 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 812 | 1 | 1 | 100.00 |
| ALWAYS | 815 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 831 | 1 | 1 | 100.00 |
| ALWAYS | 837 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 880 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 884 | 1 | 1 | 100.00 |
| ALWAYS | 886 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 892 | 1 | 1 | 100.00 |
| ALWAYS | 914 | 6 | 6 | 100.00 |
| ALWAYS | 921 | 6 | 6 | 100.00 |
134 ///////////////////////
135 1/1 assign hw2reg.status.fifo_full.d = fifo_full;
Tests: T1 T2 T3
136 1/1 assign hw2reg.status.fifo_empty.d = fifo_empty;
Tests: T1 T2 T3
137 1/1 assign hw2reg.status.fifo_depth.d = fifo_depth;
Tests: T1 T2 T3
138 1/1 assign hw2reg.status.hmac_idle.d = idle;
Tests: T1 T2 T3
139
140 typedef enum logic [1:0] {
141 DoneAwaitCmd,
142 DoneAwaitHashDone,
143 DoneAwaitMessageComplete,
144 DoneAwaitHashComplete
145 } done_state_e;
146
147 done_state_e done_state_d, done_state_q;
148
149 always_comb begin
150 1/1 done_state_d = done_state_q;
Tests: T1 T2 T3
151 1/1 hash_done_event = 1'b0;
Tests: T1 T2 T3
152
153 1/1 unique case (done_state_q)
Tests: T1 T2 T3
154 DoneAwaitCmd: begin
155 1/1 if (sha_hash_process) begin
Tests: T1 T2 T3
156 // SHA has been told to process the message, so signal *done* when the hash is done.
157 1/1 done_state_d = DoneAwaitHashDone;
Tests: T1 T4 T5
158 1/1 end else if (reg_hash_stop) begin
Tests: T1 T2 T3
159 // SHA has been told to stop, so first wait for the current message block to be complete.
160 1/1 done_state_d = DoneAwaitMessageComplete;
Tests: T4 T7 T8
161 end
MISSING_ELSE
162 end
163
164 DoneAwaitHashDone: begin
165 1/1 if (reg_hash_done) begin
Tests: T1 T4 T5
166 1/1 hash_done_event = 1'b1;
Tests: T1 T4 T5
167 1/1 done_state_d = DoneAwaitCmd;
Tests: T1 T4 T5
168 end
MISSING_ELSE
169 end
170
171 DoneAwaitMessageComplete: begin
172 1/1 if (digest_on_blk) begin
Tests: T4 T7 T8
173 // Once the digest is being computed for the complete message block, wait for the hash to
174 // complete.
175 // TODO (issue #21710): handle incomplete message size and check against 512 or 1024
176 1/1 done_state_d = DoneAwaitHashComplete;
Tests: T4 T7 T8
177 end
MISSING_ELSE
178 end
179
180 DoneAwaitHashComplete: begin
181 1/1 if (!hash_running) begin
Tests: T4 T7 T8
182 1/1 hash_done_event = 1'b1;
Tests: T4 T7 T8
183 1/1 done_state_d = DoneAwaitCmd;
Tests: T4 T7 T8
184 end
==> MISSING_ELSE
185 end
186
187 default: ;
Exclude Annotation: VC_COV_UNR
188 endcase
189 end
190
191 always_ff @(posedge clk_i or negedge rst_ni) begin
192 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
193 1/1 done_state_q <= DoneAwaitCmd;
Tests: T1 T2 T3
194 end else begin
195 1/1 done_state_q <= done_state_d;
Tests: T1 T2 T3
196 end
197 end
198
199 1/1 assign wipe_secret = reg2hw.wipe_secret.qe;
Tests: T9 T12 T14
200 1/1 assign wipe_v = reg2hw.wipe_secret.q;
Tests: T1 T2 T3
201
202 // update secret key
203 always_comb begin : update_secret_key
204 1/1 secret_key_d = secret_key;
Tests: T1 T2 T3
205 1/1 if (wipe_secret) begin
Tests: T1 T2 T3
206 1/1 secret_key_d = {32{wipe_v}};
Tests: T9 T12 T26
207 1/1 end else if (!cfg_block) begin
Tests: T1 T2 T3
208 // Allow updating secret key only when the engine is in Idle.
209 1/1 for (int i = 0; i < 32; i++) begin
Tests: T1 T2 T3
210 1/1 if (reg2hw.key[31-i].qe) begin
Tests: T1 T2 T3
211 // swap byte endianness per secret key word if key_swap = 1
212 1/1 secret_key_d[32*i+:32] = conv_endian32(reg2hw.key[31-i].q, key_swap);
Tests: T1 T4 T5
213 end
MISSING_ELSE
214 end
215 end
MISSING_ELSE
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin
219 2/2 if (!rst_ni) secret_key <= '0;
Tests: T1 T2 T3 | T1 T2 T3
220 1/1 else secret_key <= secret_key_d;
Tests: T1 T2 T3
221 end
222
223 for (genvar i = 0; i < 32; i++) begin : gen_key
224 assign hw2reg.key[31-i].d = '0;
225 end
226
227 // Retain the previous digest in CSRs until HMAC is actually started with a valid configuration
228 always_comb begin : assign_digest_reg
229 // default
230 // digest SW -> HW
231 1/1 digest_sw = '0;
Tests: T1 T2 T3
232 1/1 digest_sw_we = '0;
Tests: T1 T2 T3
233 // digest HW -> SW
234 1/1 hw2reg.digest = '0;
Tests: T1 T2 T3
235
236 1/1 for (int i = 0; i < 8; i++) begin
Tests: T1 T2 T3
237 // digest SW -> HW (depends on digest size configured even before starting/enabling)
238 // capturing the intermediate digests written by SW when restoring context into the SHA-2
239 // engine before it is started
240 1/1 if (digest_size == SHA2_256) begin
Tests: T1 T2 T3
241 // digest SW -> HW
242 1/1 digest_sw[i][31:0] = conv_endian32(reg2hw.digest[i].q, digest_swap);
Tests: T1 T6 T7
243 1/1 digest_sw_we[i] = reg2hw.digest[i].qe;
Tests: T1 T6 T7
244 1/1 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
Tests: T1 T2 T3
245 // digest SW -> HW
246 1/1 digest_sw[i][63:32] = reg2hw.digest[2*i].qe ?
Tests: T1 T4 T5
247 conv_endian32(reg2hw.digest[2*i].q, digest_swap) :
248 digest[i][63:32];
249 1/1 digest_sw[i][31:0] = reg2hw.digest[2*i+1].qe ?
Tests: T1 T4 T5
250 conv_endian32(reg2hw.digest[2*i+1].q, digest_swap) :
251 digest[i][31:0];
252 1/1 digest_sw_we[i] = reg2hw.digest[2*i].qe | reg2hw.digest[2*i+1].qe;
Tests: T1 T4 T5
253 end
MISSING_ELSE
254
255 // digest HW -> SW (depends on configuration that has been started)
256 1/1 if (digest_size_started_q == SHA2_256) begin
Tests: T1 T2 T3
257 1/1 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T6 T7
258 // replicate digest[0..7] into digest[8..15]. Digest[8...15] are irrelevant for SHA2_256,
259 // but this ensures all digest CSRs are wiped out with random value (at wipe_secret)
260 // across different configurations.
261 1/1 hw2reg.digest[i+8].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T6 T7
262 1/1 end else if ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)) begin
Tests: T1 T2 T3
263 // digest HW -> SW
264 // digest swap only within each 32-bit word of the 64-bit digest word, not digest swap
265 // on the entire 64-bit digest word
266 1/1 hw2reg.digest[2*i].d = conv_endian32(digest[i][63:32], digest_swap);
Tests: T1 T4 T5
267 1/1 hw2reg.digest[2*i+1].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T4 T5
268 end else begin // for SHA2_None
269 // to ensure secret wiping is always passed to digest CSRs
270 1/1 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T2 T3
271 1/1 hw2reg.digest[i+8].d = conv_endian32(digest[i][31:0], digest_swap);
Tests: T1 T2 T3
272 end
273 end
274 end
275
276 logic unused_cfg_qe;
277 1/1 assign unused_cfg_qe = ^{cfg_reg.sha_en.qe, cfg_reg.hmac_en.qe,
Tests: T1 T2 T3
278 cfg_reg.endian_swap.qe, cfg_reg.digest_swap.qe,
279 cfg_reg.key_swap.qe, cfg_reg.digest_size.qe,
280 cfg_reg.key_length.qe };
281
282 1/1 assign sha_en = cfg_reg.sha_en.q;
Tests: T1 T2 T3
283 1/1 assign hmac_en = cfg_reg.hmac_en.q;
Tests: T1 T2 T3
284
285 1/1 assign digest_size_supplied = digest_mode_e'(cfg_reg.digest_size.q);
Tests: T1 T2 T3
286 always_comb begin : cast_digest_size
287 1/1 digest_size = SHA2_None;
Tests: T1 T2 T3
288
289 1/1 unique case (digest_size_supplied)
Tests: T1 T2 T3
290 1/1 SHA2_256: digest_size = SHA2_256;
Tests: T1 T6 T7
291 1/1 SHA2_384: digest_size = SHA2_384;
Tests: T5 T6 T7
292 1/1 SHA2_512: digest_size = SHA2_512;
Tests: T1 T4 T5
293 // unsupported digest size values are mapped to SHA2_None
294 // if HMAC/SHA-2 is triggered to start with this digest size, it is blocked
295 // and an error is signalled to SW
296 default: digest_size = SHA2_None;
297 endcase
298 end
299
300 // Hold the previous digest size till HMAC is started with the new digest size configured
301 1/1 assign digest_size_started_d = (hash_start_or_continue) ? digest_size : digest_size_started_q;
Tests: T1 T2 T3
302
303 always_ff @(posedge clk_i or negedge rst_ni) begin
304 2/2 if (!rst_ni) digest_size_started_q <= SHA2_None;
Tests: T1 T2 T3 | T1 T2 T3
305 1/1 else digest_size_started_q <= digest_size_started_d;
Tests: T1 T2 T3
306 end
307
308 1/1 assign key_length_supplied = key_length_e'(cfg_reg.key_length.q);
Tests: T1 T2 T3
309 always_comb begin : cast_key_length
310 1/1 key_length = Key_None;
Tests: T1 T2 T3
311
312 1/1 unique case (key_length_supplied)
Tests: T1 T2 T3
313 1/1 Key_128: key_length = Key_128;
Tests: T1 T5 T6
314 1/1 Key_256: key_length = Key_256;
Tests: T1 T5 T6
315 1/1 Key_384: key_length = Key_384;
Tests: T1 T4 T6
316 1/1 Key_512: key_length = Key_512;
Tests: T1 T4 T5
317 1/1 Key_1024: key_length = Key_1024;
Tests: T1 T4 T7
318 // unsupported key length values are mapped to Key_None
319 // if HMAC (not SHA-2) is triggered to start with this key length, it is blocked
320 // and an error is signalled to SW
321 default: key_length = Key_None;
322 endcase
323 end
324
325 1/1 assign endian_swap = cfg_reg.endian_swap.q;
Tests: T1 T2 T3
326 1/1 assign digest_swap = cfg_reg.digest_swap.q;
Tests: T1 T2 T3
327 1/1 assign key_swap = cfg_reg.key_swap.q;
Tests: T1 T2 T3
328
329 1/1 assign hw2reg.cfg.hmac_en.d = cfg_reg.hmac_en.q;
Tests: T1 T2 T3
330 1/1 assign hw2reg.cfg.sha_en.d = cfg_reg.sha_en.q;
Tests: T1 T2 T3
331 1/1 assign hw2reg.cfg.digest_size.d = digest_mode_e'(digest_size);
Tests: T1 T2 T3
332 1/1 assign hw2reg.cfg.key_length.d = key_length_e'(key_length);
Tests: T1 T2 T3
333 1/1 assign hw2reg.cfg.endian_swap.d = cfg_reg.endian_swap.q;
Tests: T1 T2 T3
334 1/1 assign hw2reg.cfg.digest_swap.d = cfg_reg.digest_swap.q;
Tests: T1 T2 T3
335 1/1 assign hw2reg.cfg.key_swap.d = cfg_reg.key_swap.q;
Tests: T1 T2 T3
336
337 1/1 assign reg_hash_start = reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q;
Tests: T1 T2 T3
338 1/1 assign reg_hash_stop = reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q;
Tests: T1 T2 T3
339 1/1 assign reg_hash_continue = reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q;
Tests: T1 T2 T3
340 1/1 assign reg_hash_process = reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q;
Tests: T1 T2 T3
341
342 // Error code register
343 1/1 assign hw2reg.err_code.de = err_valid;
Tests: T1 T2 T3
344 1/1 assign hw2reg.err_code.d = err_code;
Tests: T1 T2 T3
345
346 /////////////////////
347 // Control signals //
348 /////////////////////
349 1/1 assign hash_start = reg_hash_start & sha_en & ~cfg_block & ~invalid_config;
Tests: T1 T2 T3
350 1/1 assign hash_continue = reg_hash_continue & sha_en & ~cfg_block & ~invalid_config;
Tests: T1 T2 T3
351 1/1 assign hash_process = reg_hash_process & sha_en & cfg_block & ~invalid_config;
Tests: T1 T2 T3
352 1/1 assign hash_start_or_continue = hash_start | hash_continue;
Tests: T1 T4 T5
353
354 always_ff @(posedge clk_i or negedge rst_ni) begin
355 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
356 1/1 cfg_block <= '0;
Tests: T1 T2 T3
357 1/1 end else if (hash_start_or_continue) begin
Tests: T1 T2 T3
358 1/1 cfg_block <= 1'b 1;
Tests: T1 T4 T5
359 1/1 end else if (reg_hash_done || reg_hash_stop) begin
Tests: T1 T2 T3
360 1/1 cfg_block <= 1'b 0;
Tests: T1 T4 T5
361 end
MISSING_ELSE
362 end
363 // Hold the configuration during the process
364 always_ff @(posedge clk_i or negedge rst_ni) begin
365 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
366 1/1 cfg_reg <= '{
Tests: T1 T2 T3
367 hmac_en: '{
368 q: 1'b0,
369 qe: 1'b0
370 },
371 sha_en: '{
372 q: 1'b0,
373 qe: 1'b0
374 },
375 endian_swap: '{
376 q: HMAC_CFG_ENDIAN_SWAP_RESVAL,
377 qe: 1'b0
378 },
379 digest_swap: '{
380 q: HMAC_CFG_DIGEST_SWAP_RESVAL,
381 qe: 1'b0
382 },
383 key_swap: '{
384 q: HMAC_CFG_KEY_SWAP_RESVAL,
385 qe: 1'b0
386 },
387 digest_size: '{
388 q: HMAC_CFG_DIGEST_SIZE_RESVAL,
389 qe: 1'b0
390 },
391 key_length: '{
392 q: HMAC_CFG_KEY_LENGTH_RESVAL,
393 qe: 1'b0
394 },
395 default:'0
396 };
397 1/1 end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
Tests: T1 T2 T3
398 1/1 cfg_reg <= reg2hw.cfg ;
Tests: T1 T4 T5
399 end
MISSING_ELSE
400 end
401
402 // Open up the MSG_FIFO from the TL-UL port when it is ready
403 always_ff @(posedge clk_i or negedge rst_ni) begin
404 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
405 1/1 msg_allowed <= '0;
Tests: T1 T2 T3
406 1/1 end else if (hash_start_or_continue) begin
Tests: T1 T2 T3
407 1/1 msg_allowed <= 1'b 1;
Tests: T1 T4 T5
408 1/1 end else if (packer_flush_done) begin
Tests: T1 T2 T3
409 1/1 msg_allowed <= 1'b 0;
Tests: T1 T4 T5
410 end
MISSING_ELSE
411 end
412
413 ////////////////
414 // Interrupts //
415 ////////////////
416
417 // instantiate interrupt hardware primitive
418 prim_intr_hw #(.Width(1)) intr_hw_hmac_done (
419 .clk_i,
420 .rst_ni,
421 .event_intr_i (hash_done_event),
422 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_done.q),
423 .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_done.q),
424 .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_done.qe),
425 .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_done.q),
426 .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_done.de),
427 .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_done.d),
428 .intr_o (intr_hmac_done_o)
429 );
430
431 // FIFO empty interrupt
432 //
433 // The FIFO empty interrupt is **not useful** for software if:
434 // - The HMAC block is running in HMAC mode and performing the second round of computing the
435 // final hash of the outer key as well as the result of the first round using the inner key.
436 // The FIFO is then managed entirely by the hardware.
437 // - The FIFO is currently not writeable by software.
438 // - Software has already written the Process command. The HMAC block will now empty the
439 // FIFO and load its content into the SHA2 core, add the padding and then perfom
440 // the final hashing operation. Software cannot append the message further.
441 // - Software has written the Stop command. The HMAC block will not wait for further input from
442 // software after finishing the current block.
443 //
444 // The FIFO empty interrupt can be **useful** for software in particular if:
445 // - The FIFO was completely full previously. However, unless the HMAC block is currently
446 // processing a block, it always empties the message FIFO faster than software can fill it up,
447 // meaning the message FIFO is empty most of the time. Note, the empty status is signaled only
448 // once after the FIFO was completely full. The FIFO needs to be full again for the empty
449 // status to be signaled again next time it's empty.
450 logic status_fifo_empty, fifo_empty_gate;
451 logic fifo_empty_negedge, fifo_empty_q;
452 logic fifo_full_posedge, fifo_full_q;
453 logic fifo_full_seen_d, fifo_full_seen_q;
454 1/1 assign fifo_empty_negedge = fifo_empty_q & ~fifo_empty;
Tests: T1 T2 T3
455 1/1 assign fifo_full_posedge = ~fifo_full_q & fifo_full;
Tests: T1 T2 T3
456
457 // Track whether the FIFO was full after being empty. We clear the tracking:
458 // - When receiving the Start, Continue, Process or Stop command. This is to start over for the
459 // next message.
460 // - When seeing a negative edge on the empty signal. This signals that software has reacted to
461 // the interrupt and is filling up the FIFO again.
462 1/1 assign fifo_full_seen_d =
Tests: T1 T2 T3
463 reg_hash_start || reg_hash_continue ||
464 reg_hash_process || reg_hash_stop ? 1'b 0 :
465 fifo_empty_negedge ? 1'b 0 :
466 fifo_full_posedge ? 1'b 1 : fifo_full_seen_q;
467
468 // The interrupt is gated unless software is actually allowed to write the FIFO and the FIFO was
469 // full before.
470 1/1 assign fifo_empty_gate = ~msg_allowed || ~fifo_full_seen_q;
Tests: T1 T2 T3
471
472 1/1 assign status_fifo_empty = fifo_empty_gate ? 1'b 0 : fifo_empty;
Tests: T1 T2 T3
473
474 always_ff @(posedge clk_i or negedge rst_ni) begin
475 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
476 1/1 fifo_empty_q <= 1'b 0;
Tests: T1 T2 T3
477 1/1 fifo_full_q <= 1'b 0;
Tests: T1 T2 T3
478 1/1 fifo_full_seen_q <= 1'b 0;
Tests: T1 T2 T3
479 end else begin
480 1/1 fifo_empty_q <= fifo_empty;
Tests: T1 T2 T3
481 1/1 fifo_full_q <= fifo_full;
Tests: T1 T2 T3
482 1/1 fifo_full_seen_q <= fifo_full_seen_d;
Tests: T1 T2 T3
483 end
484 end
485
486 prim_intr_hw #(
487 .Width(1),
488 .IntrT("Status")
489 ) intr_hw_fifo_empty (
490 .clk_i,
491 .rst_ni,
492 .event_intr_i (status_fifo_empty),
493 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.fifo_empty.q),
494 .reg2hw_intr_test_q_i (reg2hw.intr_test.fifo_empty.q),
495 .reg2hw_intr_test_qe_i (reg2hw.intr_test.fifo_empty.qe),
496 .reg2hw_intr_state_q_i (reg2hw.intr_state.fifo_empty.q),
497 .hw2reg_intr_state_de_o (hw2reg.intr_state.fifo_empty.de),
498 .hw2reg_intr_state_d_o (hw2reg.intr_state.fifo_empty.d),
499 .intr_o (intr_fifo_empty_o)
500 );
501 prim_intr_hw #(.Width(1)) intr_hw_hmac_err (
502 .clk_i,
503 .rst_ni,
504 .event_intr_i (err_valid),
505 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.hmac_err.q),
506 .reg2hw_intr_test_q_i (reg2hw.intr_test.hmac_err.q),
507 .reg2hw_intr_test_qe_i (reg2hw.intr_test.hmac_err.qe),
508 .reg2hw_intr_state_q_i (reg2hw.intr_state.hmac_err.q),
509 .hw2reg_intr_state_de_o (hw2reg.intr_state.hmac_err.de),
510 .hw2reg_intr_state_d_o (hw2reg.intr_state.hmac_err.d),
511 .intr_o (intr_hmac_err_o)
512 );
513
514 ///////////////
515 // Instances //
516 ///////////////
517
518 1/1 assign msg_fifo_rvalid = msg_fifo_req & ~msg_fifo_we;
Tests: T1 T2 T3
519 assign msg_fifo_rdata = '1; // Return all F
520 assign msg_fifo_rerror = '1; // Return error for read access
521 1/1 assign msg_fifo_gnt = msg_fifo_req & ~hmac_fifo_wsel & packer_ready;
Tests: T1 T2 T3
522
523 /////////////////////
524 // Unused Signals //
525 /////////////////////
526 logic unused_signals;
527 1/1 assign unused_signals = ^{reg_fifo_wmask[7:1], reg_fifo_wmask[15:9],
Tests: T1 T2 T3
528 reg_fifo_wmask[23:17], reg_fifo_wmask[31:25]};
529
530 // FIFO control: from packer into message FIFO
531 sha_fifo32_t reg_fifo_wentry;
532 1/1 assign reg_fifo_wentry.data = conv_endian32(reg_fifo_wdata, 1'b1); // always convert
Tests: T1 T2 T3
533 1/1 assign reg_fifo_wentry.mask = {reg_fifo_wmask[0], reg_fifo_wmask[8],
Tests: T1 T2 T3
534 reg_fifo_wmask[16], reg_fifo_wmask[24]};
535 1/1 assign fifo_full = ~fifo_wready;
Tests: T1 T2 T3
536 1/1 assign fifo_empty = ~fifo_rvalid;
Tests: T1 T2 T3
537 1/1 assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
Tests: T1 T2 T3
538
539 logic index;
540 always_comb begin : select_fifo_wdata
541 // default when !hmac_fifo_wsel
542 1/1 index = 1'b0;
Tests: T1 T2 T3
543 1/1 fifo_wdata = reg_fifo_wentry;
Tests: T1 T2 T3
544
545 1/1 if (hmac_fifo_wsel) begin
Tests: T1 T2 T3
546 1/1 fifo_wdata = '0;
Tests: T1 T4 T5
547 1/1 if (digest_size == SHA2_256) begin
Tests: T1 T4 T5
548 // only reads out lower 32 bits of each digest word and discards upper 32-bit zero padding
549 1/1 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel[2:0]][31:0], mask: '1};
Tests: T6 T8 T10
550 1/1 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
Tests: T1 T4 T5
551 // reads out first upper 32 bits then lower 32 bits of each digest word
552 1/1 index = !hmac_fifo_wdata_sel[0];
Tests: T1 T4 T5
553 1/1 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel >> 1][32*index+:32], mask: '1};
Tests: T1 T4 T5
554 end
==> MISSING_ELSE
555 end
MISSING_ELSE
556 end
557
558 // Extended for 1024-bit block
559 localparam int MsgFifoDepth = 32;
560 prim_fifo_sync #(
561 .Width ($bits(sha_fifo32_t)),
562 .Pass (1'b1),
563 .Depth (MsgFifoDepth)
564 ) u_msg_fifo (
565 .clk_i,
566 .rst_ni,
567 .clr_i (1'b0),
568
569 .wvalid_i(fifo_wvalid & sha_en),
570 .wready_o(fifo_wready),
571 .wdata_i (fifo_wdata),
572
573 .depth_o (fifo_depth),
574 .full_o (),
575
576 .rvalid_o(fifo_rvalid),
577 .rready_i(fifo_rready),
578 .rdata_o (fifo_rdata),
579 .err_o ()
580 );
581
582 // TL ADAPTER SRAM
583 tlul_adapter_sram #(
584 .SramAw (9),
585 .SramDw (32),
586 .Outstanding (1),
587 .ByteAccess (1),
588 .ErrOnRead (1)
589 ) u_tlul_adapter (
590 .clk_i,
591 .rst_ni,
592 .tl_i (tl_win_h2d),
593 .tl_o (tl_win_d2h),
594 .en_ifetch_i (prim_mubi_pkg::MuBi4False),
595 .req_o (msg_fifo_req ),
596 .req_type_o ( ),
597 .gnt_i (msg_fifo_gnt ),
598 .we_o (msg_fifo_we ),
599 .addr_o ( ), // Doesn't care the address
600 // other than sub-word
601 .wdata_o (msg_fifo_wdata ),
602 .wmask_o (msg_fifo_wmask ),
603 .intg_error_o ( ),
604 .rdata_i (msg_fifo_rdata ),
605 .rvalid_i (msg_fifo_rvalid),
606 .rerror_i (msg_fifo_rerror),
607 .compound_txn_in_progress_o (),
608 .readback_en_i (prim_mubi_pkg::MuBi4False),
609 .readback_error_o (),
610 .wr_collision_i (1'b0),
611 .write_pending_i (1'b0)
612 );
613
614 // TL-UL to MSG_FIFO byte write handling
615 logic msg_write;
616
617 1/1 assign msg_write = msg_fifo_req & msg_fifo_we & ~hmac_fifo_wsel & msg_allowed;
Tests: T1 T2 T3
618
619 logic [$clog2(32+1)-1:0] wmask_ones;
620
621 always_comb begin
622 1/1 wmask_ones = '0;
Tests: T1 T2 T3
623 1/1 for (int i = 0 ; i < 32 ; i++) begin
Tests: T1 T2 T3
624 1/1 wmask_ones = wmask_ones + msg_fifo_wmask[i];
Tests: T1 T2 T3
625 end
626 end
627
628 // Calculate written message
629 always_ff @(posedge clk_i or negedge rst_ni) begin
630 2/2 if (!rst_ni) message_length <= '0;
Tests: T1 T2 T3 | T1 T2 T3
631 1/1 else message_length <= message_length_d;
Tests: T1 T2 T3
632 end
633
634 always_comb begin
635 1/1 message_length_d = message_length;
Tests: T1 T2 T3
636 1/1 if (!cfg_block) begin
Tests: T1 T2 T3
637 1/1 if (reg2hw.msg_length_lower.qe) begin
Tests: T1 T2 T3
638 1/1 message_length_d[31:0] = reg2hw.msg_length_lower.q;
Tests: T7 T8 T10
639 end
MISSING_ELSE
640 1/1 if (reg2hw.msg_length_upper.qe) begin
Tests: T1 T2 T3
641 1/1 message_length_d[63:32] = reg2hw.msg_length_upper.q;
Tests: T7 T8 T10
642 end
MISSING_ELSE
643 end
MISSING_ELSE
644
645 1/1 if (hash_start) begin
Tests: T1 T2 T3
646 1/1 message_length_d = '0;
Tests: T1 T4 T5
647 1/1 end else if (msg_write && sha_en && packer_ready) begin
Tests: T1 T2 T3
648 1/1 message_length_d = message_length + 64'(wmask_ones);
Tests: T1 T4 T5
649 end
MISSING_ELSE
650 end
651
652 1/1 assign hw2reg.msg_length_upper.d = message_length[63:32];
Tests: T1 T2 T3
653 1/1 assign hw2reg.msg_length_lower.d = message_length[31:0];
Tests: T1 T2 T3
654
655 // Convert endian here
656 // prim_packer always packs to the right, but SHA engine assumes incoming
657 // to be big-endian, [31:24] comes first. So, the data is reverted after
658 // prim_packer before the message fifo. here to reverse if not big-endian
659 // before pushing to the packer.
660 1/1 assign msg_fifo_wdata_endian = conv_endian32(msg_fifo_wdata, endian_swap);
Tests: T1 T2 T3
661 1/1 assign msg_fifo_wmask_endian = conv_endian32(msg_fifo_wmask, endian_swap);
Tests: T1 T2 T3
662
663 prim_packer #(
664 .InW (32),
665 .OutW (32),
666 .EnProtection (1'b 0)
667 ) u_packer (
668 .clk_i,
669 .rst_ni,
670
671 .valid_i (msg_write & sha_en),
672 .data_i (msg_fifo_wdata_endian),
673 .mask_i (msg_fifo_wmask_endian),
674 .ready_o (packer_ready),
675
676 .valid_o (reg_fifo_wvalid),
677 .data_o (reg_fifo_wdata),
678 .mask_o (reg_fifo_wmask),
679 .ready_i (fifo_wready & ~hmac_fifo_wsel),
680
681 .flush_i (hash_process),
682 .flush_done_o (packer_flush_done), // ignore at this moment
683
684 .err_o () // Not used
685 );
686
687 hmac_core u_hmac (
688 .clk_i,
689 .rst_ni,
690 .secret_key_i (secret_key),
691 .hmac_en_i (hmac_en),
692 .digest_size_i (digest_size),
693 .key_length_i (key_length),
694
695 .reg_hash_start_i (hash_start),
696 .reg_hash_stop_i (reg_hash_stop),
697 .reg_hash_continue_i (hash_continue),
698 .reg_hash_process_i (packer_flush_done), // Trigger after all msg written
699 .hash_done_o (reg_hash_done),
700 .sha_hash_start_o (sha_hash_start),
701 .sha_hash_continue_o (sha_hash_continue),
702 .sha_hash_process_o (sha_hash_process),
703 .sha_hash_done_i (sha_hash_done),
704
705 .sha_rvalid_o (shaf_rvalid),
706 .sha_rdata_o (shaf_rdata),
707 .sha_rready_i (shaf_rready),
708
709 .fifo_rvalid_i (fifo_rvalid),
710 .fifo_rdata_i (fifo_rdata),
711 .fifo_rready_o (fifo_rready),
712
713 .fifo_wsel_o (hmac_fifo_wsel),
714 .fifo_wvalid_o (hmac_fifo_wvalid),
715 .fifo_wdata_sel_o (hmac_fifo_wdata_sel),
716 .fifo_wready_i (fifo_wready),
717
718 .message_length_i (message_length),
719 .sha_message_length_o (sha_message_length),
720
721 .idle_o (hmac_core_idle)
722 );
723
724 // Instantiate SHA-2 256/384/512 engine
725 prim_sha2_32 #(
726 .MultimodeEn(1)
727 ) u_prim_sha2_512 (
728 .clk_i,
729 .rst_ni,
730 .wipe_secret_i (wipe_secret),
731 .wipe_v_i (wipe_v),
732 .fifo_rvalid_i (shaf_rvalid),
733 .fifo_rdata_i (shaf_rdata),
734 .fifo_rready_o (shaf_rready),
735 .sha_en_i (sha_en),
736 .hash_start_i (sha_hash_start),
737 .hash_stop_i (reg_hash_stop),
738 .hash_continue_i (sha_hash_continue),
739 .digest_mode_i (digest_size),
740 .hash_process_i (sha_hash_process),
741 .message_length_i (sha_message_length),
742 .digest_i (digest_sw),
743 .digest_we_i (digest_sw_we),
744 .digest_o (digest),
745 .hash_running_o (hash_running),
746 .digest_on_blk_o (digest_on_blk),
747 .hash_done_o (sha_hash_done),
748 .idle_o (sha_core_idle)
749 );
750
751 // Register top
752 logic [NumAlerts-1:0] alert_test, alerts;
753 hmac_reg_top u_reg (
754 .clk_i,
755 .rst_ni,
756
757 .tl_i,
758 .tl_o,
759
760 .tl_win_o (tl_win_h2d),
761 .tl_win_i (tl_win_d2h),
762
763 .reg2hw,
764 .hw2reg,
765
766 // SEC_CM: BUS.INTEGRITY
767 .intg_err_o (alerts[0])
768 );
769
770 // Alerts
771 1/1 assign alert_test = {
Tests: T1 T2 T3
772 reg2hw.alert_test.q &
773 reg2hw.alert_test.qe
774 };
775
776 localparam logic [NumAlerts-1:0] AlertIsFatal = {1'b1};
777 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
778 prim_alert_sender #(
779 .AsyncOn(AlertAsyncOn[i]),
780 .IsFatal(AlertIsFatal[i])
781 ) u_prim_alert_sender (
782 .clk_i,
783 .rst_ni,
784 .alert_test_i ( alert_test[i] ),
785 .alert_req_i ( alerts[0] ),
786 .alert_ack_o ( ),
787 .alert_state_o ( ),
788 .alert_rx_i ( alert_rx_i[i] ),
789 .alert_tx_o ( alert_tx_o[i] )
790 );
791 end
792
793 /////////////////////////
794 // HMAC Error Handling //
795 /////////////////////////
796 logic hash_start_sha_disabled, update_seckey_inprocess;
797 logic hash_start_active; // `reg_hash_start` or `reg_hash_continue` set when hash already active
798 logic msg_push_not_allowed; // Message is received when `hash_start_or_continue` isn't set
799
800 1/1 assign hash_start_sha_disabled = (reg_hash_start | reg_hash_continue) & ~sha_en;
Tests: T1 T2 T3
801 1/1 assign hash_start_active = (reg_hash_start | reg_hash_continue) & cfg_block;
Tests: T1 T2 T3
802 1/1 assign msg_push_not_allowed = msg_fifo_req & ~msg_allowed;
Tests: T1 T2 T3
803
804 // Invalid/unconfigured HMAC/SHA-2: not configured/invalid digest size or
805 // not configured/invalid key length for HMAC mode or
806 // key_length = 1024-bit for digest_size = SHA2_256 (max 512-bit is supported for SHA-2 256)
807 1/1 assign invalid_config = ((digest_size == SHA2_None) |
Tests: T1 T2 T3
808 ((key_length == Key_None) && hmac_en) |
809 ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en));
810
811 // invalid_config at reg_hash_start or reg_hash_continue will signal an error to the SW
812 1/1 assign invalid_config_atstart = (reg_hash_start || reg_hash_continue) & invalid_config;
Tests: T1 T2 T3
813
814 always_comb begin
815 1/1 update_seckey_inprocess = 1'b0;
Tests: T1 T2 T3
816 1/1 if (cfg_block) begin
Tests: T1 T2 T3
817 1/1 for (int i = 0 ; i < 32 ; i++) begin
Tests: T1 T4 T5
818 1/1 if (reg2hw.key[i].qe) begin
Tests: T1 T4 T5
819 1/1 update_seckey_inprocess = update_seckey_inprocess | 1'b1;
Tests: T42 T43 T44
820 end
MISSING_ELSE
821 end
822 end else begin
823 1/1 update_seckey_inprocess = 1'b0;
Tests: T1 T2 T3
824 end
825 end
826
827 // Update ERR_CODE register and interrupt only when no pending interrupt.
828 // This ensures only the first event of the series of events can be seen to sw.
829 // It is recommended that the software reads ERR_CODE register when interrupt
830 // is pending to avoid any race conditions.
831 1/1 assign err_valid = ~reg2hw.intr_state.hmac_err.q &
Tests: T1 T2 T3
832 ( hash_start_sha_disabled | update_seckey_inprocess
833 | hash_start_active | msg_push_not_allowed | invalid_config_atstart);
834
835 always_comb begin
836 // default
837 1/1 err_code = NoError;
Tests: T1 T2 T3
838
839 1/1 priority case (1'b1)
Tests: T1 T2 T3
840 // SwInvalidConfig has the highest priority: SW configures HMAC incorrectly
841 invalid_config_atstart: begin
842 1/1 err_code = SwInvalidConfig;
Tests: T1 T4 T5
843 end
844
845 hash_start_sha_disabled: begin
846 1/1 err_code = SwHashStartWhenShaDisabled;
Tests: T45 T46 T47
847 end
848
849 hash_start_active: begin
850 1/1 err_code = SwHashStartWhenActive;
Tests: T46 T47 T48
851 end
852
853 msg_push_not_allowed: begin
854 1/1 err_code = SwPushMsgWhenDisallowed;
Tests: T1 T4 T5
855 end
856
857 update_seckey_inprocess: begin
858 1/1 err_code = SwUpdateSecretKeyInProcess;
Tests: T42 T43 T44
859 end
860
861 default: begin
862 err_code = NoError;
863 end
864 endcase
865 end
866
867 /////////////////////
868 // Idle output //
869 /////////////////////
870 // TBD this should be connected later
871 // Idle: AND condition of:
872 // - packer empty: Currently no way to guarantee the packer is empty.
873 // temporary, the logic uses packer output (reg_fifo_wvalid)
874 // - MSG_FIFO --> fifo_rvalid
875 // - HMAC_CORE --> hmac_core_idle
876 // - SHA2_CORE --> sha_core_idle
877 // - Clean interrupt status
878 // ICEBOX(#12958): Revise prim_packer and replace `reg_fifo_wvalid` to the
879 // empty status.
880 1/1 assign idle = !reg_fifo_wvalid && !fifo_rvalid
Tests: T1 T2 T3
881 && hmac_core_idle && sha_core_idle;
882
883 prim_mubi_pkg::mubi4_t idle_q, idle_d;
884 1/1 assign idle_d = prim_mubi_pkg::mubi4_bool_to_mubi(idle);
Tests: T1 T2 T3
885 always_ff @(posedge clk_i or negedge rst_ni) begin
886 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
887 1/1 idle_q <= prim_mubi_pkg::MuBi4False;
Tests: T1 T2 T3
888 end else begin
889 1/1 idle_q <= idle_d;
Tests: T1 T2 T3
890 end
891 end
892 1/1 assign idle_o = idle_q;
Tests: T1 T2 T3
893
894 //////////////////////////////////////////////
895 // Assertions, Assumptions, and Coverpoints //
896 //////////////////////////////////////////////
897
898 `ifndef VERILATOR
899 `ifndef SYNTHESIS
900 // HMAC assumes TL-UL mask is byte-aligned.
901 property wmask_bytealign_p(wmask_byte, clk, rst_n);
902 @(posedge clk) disable iff (rst_n == 0)
903 msg_fifo_req & msg_fifo_we |-> wmask_byte inside {'0, '1};
904 endproperty
905
906 for (genvar i = 0 ; i < 4; i++) begin: gen_assert_wmask_bytealign
907 assert property (wmask_bytealign_p(msg_fifo_wmask[8*i+:8], clk_i, rst_ni));
908 end
909
910 // To pass FPV, this shouldn't add pragma translate_off even these two signals
911 // are used in Assertion only
912 logic in_process;
913 always_ff @(posedge clk_i or negedge rst_ni) begin
914 2/2 if (!rst_ni) in_process <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
915 2/2 else if (hash_process || reg_hash_stop) in_process <= 1'b1;
Tests: T1 T2 T3 | T1 T4 T5
916 2/2 else if (reg_hash_done) in_process <= 1'b0;
Tests: T1 T2 T3 | T1 T4 T5
MISSING_ELSE
917 end
918
919 logic initiated;
920 always_ff @(posedge clk_i or negedge rst_ni) begin
921 2/2 if (!rst_ni) initiated <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
922 2/2 else if (hash_start_or_continue) initiated <= 1'b1;
Tests: T1 T2 T3 | T1 T4 T5
923 2/2 else if (hash_process || reg_hash_stop) initiated <= 1'b0;
Tests: T1 T2 T3 | T1 T4 T5
MISSING_ELSE
Cond Coverage for Instance : tb.dut
| Total | Covered | Percent |
|---|
| Conditions | 180 | 168 | 93.33 |
| Logical | 180 | 168 | 93.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 240
EXPRESSION (digest_size == SHA2_256)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T7 |
LINE 244
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T5,T6,T7 |
LINE 244
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 244
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 246
EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T8,T13,T49 |
LINE 249
EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T8,T13,T49 |
LINE 252
EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
------------1------------ ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T4,T5 |
| 0 | 1 | Covered | T8,T13,T49 |
| 1 | 0 | Covered | T8,T13,T49 |
LINE 256
EXPRESSION (digest_size_started_q == SHA2_256)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T7 |
LINE 262
EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
-----------------1----------------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T6,T7,T10 |
LINE 262
SUB-EXPRESSION (digest_size_started_q == SHA2_384)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T7,T10 |
LINE 262
SUB-EXPRESSION (digest_size_started_q == SHA2_512)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 301
EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 337
EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 338
EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T4,T7,T8 |
LINE 339
EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
-------------1------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T4,T7,T8 |
LINE 340
EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
-------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 349
EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
-------1------ ---2-- -------3------ ---------4---------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Covered | T45,T46,T47 |
| 1 | 1 | 0 | 1 | Covered | T46,T47,T48 |
| 1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 350
EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
--------1-------- ---2-- -------3------ ---------4---------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T4,T7,T8 |
LINE 351
EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
--------1------- ---2-- ----3---- ---------4---------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 352
EXPRESSION (hash_start | hash_continue)
-----1---- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 359
EXPRESSION (reg_hash_done || reg_hash_stop)
------1------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 397
EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T50,T51 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 454
EXPRESSION (fifo_empty_q & ((~fifo_empty)))
------1----- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 455
EXPRESSION (((~fifo_full_q)) & fifo_full)
--------1------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T13,T17 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 462
EXPRESSION
Number Term
1 (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 462
SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
-------1------ --------2-------- --------3------- ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T4,T7,T8 |
| 0 | 0 | 1 | 0 | Covered | T1,T4,T5 |
| 0 | 1 | 0 | 0 | Covered | T4,T7,T8 |
| 1 | 0 | 0 | 0 | Covered | T1,T4,T5 |
LINE 462
SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 462
SUB-EXPRESSION (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 470
EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
--------1------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T13,T17 |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 472
EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T11,T13,T17 |
| 1 | Covered | T1,T2,T3 |
LINE 518
EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
------1----- --------2-------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 521
EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
------1----- ---------2--------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Unreachable | T21,T22,T23 |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 537
EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 537
SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
-------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 547
EXPRESSION (digest_size == SHA2_256)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T6,T8,T10 |
LINE 550
EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T6,T10,T9 |
LINE 550
SUB-EXPRESSION (digest_size == SHA2_384)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T6,T10,T9 |
LINE 550
SUB-EXPRESSION (digest_size == SHA2_512)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T10,T9 |
| 1 | Covered | T1,T4,T5 |
LINE 564
EXPRESSION (fifo_wvalid & sha_en)
-----1----- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 617
EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
------1----- -----2----- ---------3--------- -----4-----
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 647
EXPRESSION (msg_write && sha_en && packer_ready)
----1---- ---2-- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Unreachable | T21,T22,T23 |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 667
EXPRESSION (msg_write & sha_en)
----1---- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 667
EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
-----1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 771
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T25,T52 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T25,T52 |
LINE 800
EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
------------------1----------------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T42,T45,T46 |
LINE 800
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 801
EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
------------------1----------------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T46,T47,T48 |
LINE 801
SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 802
EXPRESSION (msg_fifo_req & ((~msg_allowed)))
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 807
EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
-------------1------------ ------------------2------------------ ---------------------------------3--------------------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 1 | Covered | T1,T8,T9 |
| 0 | 1 | 0 | Covered | T1,T5,T6 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 807
SUB-EXPRESSION (digest_size == SHA2_None)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 807
SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
------------1----------- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 807
SUB-EXPRESSION (key_length == Key_None)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 807
SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
------------1----------- ------------2------------ ---3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T6,T8 |
| 1 | 0 | 1 | Covered | T1,T7,T10 |
| 1 | 1 | 0 | Covered | T7,T9,T11 |
| 1 | 1 | 1 | Covered | T1,T8,T9 |
LINE 807
SUB-EXPRESSION (key_length == Key_1024)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T7 |
LINE 807
SUB-EXPRESSION (digest_size == SHA2_256)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T7 |
LINE 812
EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
------------------1------------------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 812
SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 831
EXPRESSION
Number Term
1 ((~reg2hw.intr_state.hmac_err.q)) &
2 (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 831
SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
-----------1----------- -----------2----------- --------3-------- ----------4--------- -----------5----------
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 1 | Covered | T1,T4,T5 |
| 0 | 0 | 0 | 1 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 1 | 0 | 0 | Covered | T46,T47,T48 |
| 0 | 1 | 0 | 0 | 0 | Covered | T42,T43,T44 |
| 1 | 0 | 0 | 0 | 0 | Covered | T45,T46,T47 |
LINE 880
EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
----------1--------- --------2------- -------3------ ------4------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 915
EXPRESSION (hash_process || reg_hash_stop)
------1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
LINE 923
EXPRESSION (hash_process || reg_hash_stop)
------1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T4,T7,T8 |
| 1 | 0 | Covered | T1,T4,T5 |
Toggle Coverage for Instance : tb.dut
| Total | Covered | Percent |
| Totals |
30 |
30 |
100.00 |
| Total Bits |
346 |
346 |
100.00 |
| Total Bits 0->1 |
173 |
173 |
100.00 |
| Total Bits 1->0 |
173 |
173 |
100.00 |
| | | |
| Ports |
30 |
30 |
100.00 |
| Port Bits |
346 |
346 |
100.00 |
| Port Bits 0->1 |
173 |
173 |
100.00 |
| Port Bits 1->0 |
173 |
173 |
100.00 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_ni |
Yes |
Yes |
T3,T24,T53 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.d_ready |
Yes |
Yes |
T3,T24,T4 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T25,T6 |
Yes |
T1,T25,T6 |
INPUT |
| tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
| tl_i.a_address[31:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
| tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_size[1:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
| tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
| tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_error |
Yes |
Yes |
T14,T18,T19 |
Yes |
T14,T18,T19 |
OUTPUT |
| tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T4 |
OUTPUT |
| tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T4,T5 |
OUTPUT |
| tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_size[1:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T4 |
Yes |
T1,T2,T4 |
OUTPUT |
| tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T3,T24 |
Yes |
T2,T3,T24 |
INPUT |
| alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T3,T24 |
Yes |
T2,T3,T24 |
OUTPUT |
| intr_hmac_done_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| intr_fifo_empty_o |
Yes |
Yes |
T11,T13,T14 |
Yes |
T11,T13,T14 |
OUTPUT |
| intr_hmac_err_o |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
OUTPUT |
| idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T24 |
OUTPUT |
*Tests covering at least one bit in the range
FSM Coverage for Instance : tb.dut
Summary for FSM :: done_state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
5 |
5 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: done_state_q
| states | Line No. | Covered | Tests |
| DoneAwaitCmd |
167 |
Covered |
T1,T2,T3 |
| DoneAwaitHashComplete |
176 |
Covered |
T4,T7,T8 |
| DoneAwaitHashDone |
157 |
Covered |
T1,T4,T5 |
| DoneAwaitMessageComplete |
160 |
Covered |
T4,T7,T8 |
| transitions | Line No. | Covered | Tests |
| DoneAwaitCmd->DoneAwaitHashDone |
157 |
Covered |
T1,T4,T5 |
| DoneAwaitCmd->DoneAwaitMessageComplete |
160 |
Covered |
T4,T7,T8 |
| DoneAwaitHashComplete->DoneAwaitCmd |
183 |
Covered |
T4,T7,T8 |
| DoneAwaitHashDone->DoneAwaitCmd |
167 |
Covered |
T1,T4,T5 |
| DoneAwaitMessageComplete->DoneAwaitHashComplete |
176 |
Covered |
T4,T7,T8 |
Branch Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
| Branches |
|
91 |
90 |
98.90 |
| TERNARY |
301 |
2 |
2 |
100.00 |
| TERNARY |
462 |
4 |
4 |
100.00 |
| TERNARY |
472 |
2 |
2 |
100.00 |
| TERNARY |
537 |
2 |
2 |
100.00 |
| CASE |
153 |
8 |
8 |
100.00 |
| IF |
192 |
2 |
2 |
100.00 |
| IF |
205 |
3 |
3 |
100.00 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
240 |
6 |
6 |
100.00 |
| IF |
256 |
3 |
3 |
100.00 |
| CASE |
289 |
4 |
4 |
100.00 |
| IF |
304 |
2 |
2 |
100.00 |
| CASE |
312 |
6 |
6 |
100.00 |
| IF |
355 |
4 |
4 |
100.00 |
| IF |
365 |
3 |
3 |
100.00 |
| IF |
404 |
4 |
4 |
100.00 |
| IF |
475 |
2 |
2 |
100.00 |
| IF |
545 |
4 |
3 |
75.00 |
| IF |
630 |
2 |
2 |
100.00 |
| IF |
636 |
5 |
5 |
100.00 |
| IF |
645 |
3 |
3 |
100.00 |
| IF |
816 |
2 |
2 |
100.00 |
| CASE |
839 |
6 |
6 |
100.00 |
| IF |
886 |
2 |
2 |
100.00 |
| IF |
914 |
4 |
4 |
100.00 |
| IF |
921 |
4 |
4 |
100.00 |
301 assign digest_size_started_d = (hash_start_or_continue) ? digest_size : digest_size_started_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
462 assign fifo_full_seen_d =
463 reg_hash_start || reg_hash_continue ||
464 reg_hash_process || reg_hash_stop ? 1'b 0 :
-1-
==>
465 fifo_empty_negedge ? 1'b 0 :
-2-
==>
466 fifo_full_posedge ? 1'b 1 : fifo_full_seen_q;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
472 assign status_fifo_empty = fifo_empty_gate ? 1'b 0 : fifo_empty;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T11,T13,T17 |
537 assign fifo_wvalid = (hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
153 unique case (done_state_q)
-1-
154 DoneAwaitCmd: begin
155 if (sha_hash_process) begin
-2-
156 // SHA has been told to process the message, so signal *done* when the hash is done.
157 done_state_d = DoneAwaitHashDone;
==>
158 end else if (reg_hash_stop) begin
-3-
159 // SHA has been told to stop, so first wait for the current message block to be complete.
160 done_state_d = DoneAwaitMessageComplete;
==>
161 end
MISSING_ELSE
==>
162 end
163
164 DoneAwaitHashDone: begin
165 if (reg_hash_done) begin
-4-
166 hash_done_event = 1'b1;
==>
167 done_state_d = DoneAwaitCmd;
168 end
MISSING_ELSE
==>
169 end
170
171 DoneAwaitMessageComplete: begin
172 if (digest_on_blk) begin
-5-
173 // Once the digest is being computed for the complete message block, wait for the hash to
174 // complete.
175 // TODO (issue #21710): handle incomplete message size and check against 512 or 1024
176 done_state_d = DoneAwaitHashComplete;
==>
177 end
MISSING_ELSE
==>
178 end
179
180 DoneAwaitHashComplete: begin
181 if (!hash_running) begin
-6-
182 hash_done_event = 1'b1;
==>
183 done_state_d = DoneAwaitCmd;
184 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
185 end
186
187 default: ;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
| DoneAwaitCmd |
1 |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
| DoneAwaitCmd |
0 |
1 |
- |
- |
- |
Covered |
T4,T7,T8 |
|
| DoneAwaitCmd |
0 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| DoneAwaitHashDone |
- |
- |
1 |
- |
- |
Covered |
T1,T4,T5 |
|
| DoneAwaitHashDone |
- |
- |
0 |
- |
- |
Covered |
T1,T4,T5 |
|
| DoneAwaitMessageComplete |
- |
- |
- |
1 |
- |
Covered |
T4,T7,T8 |
|
| DoneAwaitMessageComplete |
- |
- |
- |
0 |
- |
Covered |
T4,T7,T8 |
|
| DoneAwaitHashComplete |
- |
- |
- |
- |
1 |
Covered |
T4,T7,T8 |
|
| DoneAwaitHashComplete |
- |
- |
- |
- |
0 |
Excluded |
|
VC_COV_UNR |
| default |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
192 if (!rst_ni) begin
-1-
193 done_state_q <= DoneAwaitCmd;
==>
194 end else begin
195 done_state_q <= done_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
205 if (wipe_secret) begin
-1-
206 secret_key_d = {32{wipe_v}};
==>
207 end else if (!cfg_block) begin
-2-
208 // Allow updating secret key only when the engine is in Idle.
209 for (int i = 0; i < 32; i++) begin
==>
210 if (reg2hw.key[31-i].qe) begin
211 // swap byte endianness per secret key word if key_swap = 1
212 secret_key_d[32*i+:32] = conv_endian32(reg2hw.key[31-i].q, key_swap);
213 end
214 end
215 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T9,T12,T26 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T4,T5 |
219 if (!rst_ni) secret_key <= '0;
-1-
==>
220 else secret_key <= secret_key_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
240 if (digest_size == SHA2_256) begin
-1-
241 // digest SW -> HW
242 digest_sw[i][31:0] = conv_endian32(reg2hw.digest[i].q, digest_swap);
==>
243 digest_sw_we[i] = reg2hw.digest[i].qe;
244 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
-2-
245 // digest SW -> HW
246 digest_sw[i][63:32] = reg2hw.digest[2*i].qe ?
-3-
==>
==>
247 conv_endian32(reg2hw.digest[2*i].q, digest_swap) :
248 digest[i][63:32];
249 digest_sw[i][31:0] = reg2hw.digest[2*i+1].qe ?
-4-
==>
==>
250 conv_endian32(reg2hw.digest[2*i+1].q, digest_swap) :
251 digest[i][31:0];
252 digest_sw_we[i] = reg2hw.digest[2*i].qe | reg2hw.digest[2*i+1].qe;
253 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T6,T7 |
| 0 |
1 |
1 |
- |
Covered |
T8,T13,T49 |
| 0 |
1 |
0 |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
- |
1 |
Covered |
T8,T13,T49 |
| 0 |
1 |
- |
0 |
Covered |
T1,T4,T5 |
| 0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
256 if (digest_size_started_q == SHA2_256) begin
-1-
257 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
==>
258 // replicate digest[0..7] into digest[8..15]. Digest[8...15] are irrelevant for SHA2_256,
259 // but this ensures all digest CSRs are wiped out with random value (at wipe_secret)
260 // across different configurations.
261 hw2reg.digest[i+8].d = conv_endian32(digest[i][31:0], digest_swap);
262 end else if ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)) begin
-2-
263 // digest HW -> SW
264 // digest swap only within each 32-bit word of the 64-bit digest word, not digest swap
265 // on the entire 64-bit digest word
266 hw2reg.digest[2*i].d = conv_endian32(digest[i][63:32], digest_swap);
==>
267 hw2reg.digest[2*i+1].d = conv_endian32(digest[i][31:0], digest_swap);
268 end else begin // for SHA2_None
269 // to ensure secret wiping is always passed to digest CSRs
270 hw2reg.digest[i].d = conv_endian32(digest[i][31:0], digest_swap);
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T6,T7 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
289 unique case (digest_size_supplied)
-1-
290 SHA2_256: digest_size = SHA2_256;
==>
291 SHA2_384: digest_size = SHA2_384;
==>
292 SHA2_512: digest_size = SHA2_512;
==>
293 // unsupported digest size values are mapped to SHA2_None
294 // if HMAC/SHA-2 is triggered to start with this digest size, it is blocked
295 // and an error is signalled to SW
296 default: digest_size = SHA2_None;
==>
Branches:
| -1- | Status | Tests |
| SHA2_256 |
Covered |
T1,T6,T7 |
| SHA2_384 |
Covered |
T5,T6,T7 |
| SHA2_512 |
Covered |
T1,T4,T5 |
| default |
Covered |
T1,T2,T3 |
304 if (!rst_ni) digest_size_started_q <= SHA2_None;
-1-
==>
305 else digest_size_started_q <= digest_size_started_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
312 unique case (key_length_supplied)
-1-
313 Key_128: key_length = Key_128;
==>
314 Key_256: key_length = Key_256;
==>
315 Key_384: key_length = Key_384;
==>
316 Key_512: key_length = Key_512;
==>
317 Key_1024: key_length = Key_1024;
==>
318 // unsupported key length values are mapped to Key_None
319 // if HMAC (not SHA-2) is triggered to start with this key length, it is blocked
320 // and an error is signalled to SW
321 default: key_length = Key_None;
==>
Branches:
| -1- | Status | Tests |
| Key_128 |
Covered |
T1,T5,T6 |
| Key_256 |
Covered |
T1,T5,T6 |
| Key_384 |
Covered |
T1,T4,T6 |
| Key_512 |
Covered |
T1,T4,T5 |
| Key_1024 |
Covered |
T1,T4,T7 |
| default |
Covered |
T1,T2,T3 |
355 if (!rst_ni) begin
-1-
356 cfg_block <= '0;
==>
357 end else if (hash_start_or_continue) begin
-2-
358 cfg_block <= 1'b 1;
==>
359 end else if (reg_hash_done || reg_hash_stop) begin
-3-
360 cfg_block <= 1'b 0;
==>
361 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
365 if (!rst_ni) begin
-1-
366 cfg_reg <= '{
==>
367 hmac_en: '{
368 q: 1'b0,
369 qe: 1'b0
370 },
371 sha_en: '{
372 q: 1'b0,
373 qe: 1'b0
374 },
375 endian_swap: '{
376 q: HMAC_CFG_ENDIAN_SWAP_RESVAL,
377 qe: 1'b0
378 },
379 digest_swap: '{
380 q: HMAC_CFG_DIGEST_SWAP_RESVAL,
381 qe: 1'b0
382 },
383 key_swap: '{
384 q: HMAC_CFG_KEY_SWAP_RESVAL,
385 qe: 1'b0
386 },
387 digest_size: '{
388 q: HMAC_CFG_DIGEST_SIZE_RESVAL,
389 qe: 1'b0
390 },
391 key_length: '{
392 q: HMAC_CFG_KEY_LENGTH_RESVAL,
393 qe: 1'b0
394 },
395 default:'0
396 };
397 end else if (!cfg_block && reg2hw.cfg.hmac_en.qe) begin
-2-
398 cfg_reg <= reg2hw.cfg ;
==>
399 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
404 if (!rst_ni) begin
-1-
405 msg_allowed <= '0;
==>
406 end else if (hash_start_or_continue) begin
-2-
407 msg_allowed <= 1'b 1;
==>
408 end else if (packer_flush_done) begin
-3-
409 msg_allowed <= 1'b 0;
==>
410 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
475 if (!rst_ni) begin
-1-
476 fifo_empty_q <= 1'b 0;
==>
477 fifo_full_q <= 1'b 0;
478 fifo_full_seen_q <= 1'b 0;
479 end else begin
480 fifo_empty_q <= fifo_empty;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
545 if (hmac_fifo_wsel) begin
-1-
546 fifo_wdata = '0;
547 if (digest_size == SHA2_256) begin
-2-
548 // only reads out lower 32 bits of each digest word and discards upper 32-bit zero padding
549 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel[2:0]][31:0], mask: '1};
==>
550 end else if ((digest_size == SHA2_384) || (digest_size == SHA2_512)) begin
-3-
551 // reads out first upper 32 bits then lower 32 bits of each digest word
552 index = !hmac_fifo_wdata_sel[0];
==>
553 fifo_wdata = '{data: digest[hmac_fifo_wdata_sel >> 1][32*index+:32], mask: '1};
554 end
MISSING_ELSE
==>
555 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T6,T8,T10 |
| 1 |
0 |
1 |
Covered |
T1,T4,T5 |
| 1 |
0 |
0 |
Not Covered |
|
| 0 |
- |
- |
Covered |
T1,T2,T3 |
630 if (!rst_ni) message_length <= '0;
-1-
==>
631 else message_length <= message_length_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
636 if (!cfg_block) begin
-1-
637 if (reg2hw.msg_length_lower.qe) begin
-2-
638 message_length_d[31:0] = reg2hw.msg_length_lower.q;
==>
639 end
MISSING_ELSE
==>
640 if (reg2hw.msg_length_upper.qe) begin
-3-
641 message_length_d[63:32] = reg2hw.msg_length_upper.q;
==>
642 end
MISSING_ELSE
==>
643 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T7,T8,T10 |
| 1 |
0 |
- |
Covered |
T1,T2,T3 |
| 1 |
- |
1 |
Covered |
T7,T8,T10 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T4,T5 |
645 if (hash_start) begin
-1-
646 message_length_d = '0;
==>
647 end else if (msg_write && sha_en && packer_ready) begin
-2-
648 message_length_d = message_length + 64'(wmask_ones);
==>
649 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
816 if (cfg_block) begin
-1-
817 for (int i = 0 ; i < 32 ; i++) begin
==>
818 if (reg2hw.key[i].qe) begin
819 update_seckey_inprocess = update_seckey_inprocess | 1'b1;
820 end
821 end
822 end else begin
823 update_seckey_inprocess = 1'b0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
839 priority case (1'b1)
-1-
840 // SwInvalidConfig has the highest priority: SW configures HMAC incorrectly
841 invalid_config_atstart: begin
842 err_code = SwInvalidConfig;
==>
843 end
844
845 hash_start_sha_disabled: begin
846 err_code = SwHashStartWhenShaDisabled;
==>
847 end
848
849 hash_start_active: begin
850 err_code = SwHashStartWhenActive;
==>
851 end
852
853 msg_push_not_allowed: begin
854 err_code = SwPushMsgWhenDisallowed;
==>
855 end
856
857 update_seckey_inprocess: begin
858 err_code = SwUpdateSecretKeyInProcess;
==>
859 end
860
861 default: begin
862 err_code = NoError;
==>
Branches:
| -1- | Status | Tests |
| invalid_config_atstart |
Covered |
T1,T4,T5 |
| hash_start_sha_disabled |
Covered |
T45,T46,T47 |
| hash_start_active |
Covered |
T46,T47,T48 |
| msg_push_not_allowed |
Covered |
T1,T4,T5 |
| update_seckey_inprocess |
Covered |
T42,T43,T44 |
| default |
Covered |
T1,T2,T3 |
886 if (!rst_ni) begin
-1-
887 idle_q <= prim_mubi_pkg::MuBi4False;
==>
888 end else begin
889 idle_q <= idle_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
914 if (!rst_ni) in_process <= 1'b0;
-1-
==>
915 else if (hash_process || reg_hash_stop) in_process <= 1'b1;
-2-
==>
916 else if (reg_hash_done) in_process <= 1'b0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
921 if (!rst_ni) initiated <= 1'b0;
-1-
==>
922 else if (hash_start_or_continue) initiated <= 1'b1;
-2-
==>
923 else if (hash_process || reg_hash_stop) initiated <= 1'b0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut
Assertion Details
AlertKnownO_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
80 |
0 |
0 |
| T3 |
3260 |
10 |
0 |
0 |
| T4 |
125683 |
0 |
0 |
0 |
| T5 |
21905 |
0 |
0 |
0 |
| T6 |
39136 |
0 |
0 |
0 |
| T7 |
10326 |
0 |
0 |
0 |
| T8 |
39861 |
0 |
0 |
0 |
| T9 |
64603 |
0 |
0 |
0 |
| T10 |
140485 |
0 |
0 |
0 |
| T24 |
7506 |
30 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
| T53 |
0 |
10 |
0 |
0 |
| T54 |
0 |
10 |
0 |
0 |
| T55 |
0 |
20 |
0 |
0 |
IntrFifoEmptyOKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
IntrHmacDoneOKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
TlOAReadyKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
TlODValidKnown
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
428367977 |
0 |
0 |
| T1 |
13682 |
13616 |
0 |
0 |
| T2 |
1174 |
1117 |
0 |
0 |
| T3 |
3260 |
2428 |
0 |
0 |
| T4 |
125683 |
125604 |
0 |
0 |
| T5 |
21905 |
21850 |
0 |
0 |
| T6 |
39136 |
39077 |
0 |
0 |
| T7 |
10326 |
10269 |
0 |
0 |
| T8 |
39861 |
39800 |
0 |
0 |
| T24 |
7506 |
5152 |
0 |
0 |
| T25 |
1404 |
1318 |
0 |
0 |
ValidHashProcessAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17261 |
0 |
0 |
| T1 |
13682 |
7 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
4 |
0 |
0 |
| T5 |
21905 |
4 |
0 |
0 |
| T6 |
39136 |
10 |
0 |
0 |
| T7 |
10326 |
9 |
0 |
0 |
| T8 |
39861 |
10 |
0 |
0 |
| T9 |
0 |
8 |
0 |
0 |
| T10 |
0 |
11 |
0 |
0 |
| T11 |
0 |
18 |
0 |
0 |
| T12 |
0 |
3 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
ValidHmacEnConditionAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
9723 |
0 |
0 |
| T1 |
13682 |
11 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2 |
0 |
0 |
| T5 |
21905 |
2 |
0 |
0 |
| T6 |
39136 |
9 |
0 |
0 |
| T7 |
10326 |
8 |
0 |
0 |
| T8 |
39861 |
6 |
0 |
0 |
| T9 |
0 |
9 |
0 |
0 |
| T10 |
0 |
7 |
0 |
0 |
| T11 |
0 |
14 |
0 |
0 |
| T12 |
0 |
4 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
ValidWriteAssert
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[0].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[1].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[2].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
gen_assert_wmask_bytealign[3].unnamed$$_0
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
428433184 |
17276207 |
0 |
0 |
| T1 |
13682 |
848 |
0 |
0 |
| T2 |
1174 |
0 |
0 |
0 |
| T3 |
3260 |
0 |
0 |
0 |
| T4 |
125683 |
2857 |
0 |
0 |
| T5 |
21905 |
287 |
0 |
0 |
| T6 |
39136 |
859 |
0 |
0 |
| T7 |
10326 |
625 |
0 |
0 |
| T8 |
39861 |
6893 |
0 |
0 |
| T9 |
0 |
4784 |
0 |
0 |
| T10 |
0 |
7735 |
0 |
0 |
| T11 |
0 |
18100 |
0 |
0 |
| T12 |
0 |
5658 |
0 |
0 |
| T24 |
7506 |
0 |
0 |
0 |
| T25 |
1404 |
0 |
0 |
0 |
