Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	440830738	411133	0	0
intr_enable_rd_A	440830738	2417	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440830738	411133	0	0
T14	89767	3551	0	0
T15	108188	0	0	0
T17	35514	0	0	0
T18	0	3600	0	0
T19	0	14246	0	0
T20	0	16603	0	0
T27	0	16160	0	0
T42	88939	0	0	0
T43	431524	0	0	0
T45	518716	0	0	0
T54	3358	0	0	0
T56	0	5	0	0
T57	0	3	0	0
T61	0	293	0	0
T62	0	14	0	0
T63	0	426	0	0
T64	1361	0	0	0
T65	82992	0	0	0
T66	1931	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440830738	2417	0	0
T18	507146	25	0	0
T20	0	142	0	0
T67	0	24	0	0
T68	0	16	0	0
T69	0	56	0	0
T70	0	7	0	0
T71	0	82	0	0
T72	0	26	0	0
T73	0	89	0	0
T74	0	20	0	0
T75	19825	0	0	0
T76	478050	0	0	0
T77	6619	0	0	0
T78	567500	0	0	0
T79	65976	0	0	0
T80	96507	0	0	0
T81	40765	0	0	0
T82	46898	0	0	0
T83	1054	0	0	0