9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 0 | 50 | 0.00 | ||
| V1 | target_smoke | i2c_target_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.720s | 23.010us | 4 | 5 | 80.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 26.686us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.950s | 1.063ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.130s | 147.157us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.440s | 31.229us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 26.686us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.130s | 147.157us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 54 | 155 | 34.84 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0 | 50 | 0.00 | ||
| V2 | host_stress_all | i2c_host_stress_all | 0 | 50 | 0.00 | ||
| V2 | host_perf | i2c_host_perf | 0 | 50 | 0.00 | ||
| V2 | host_override | i2c_host_override | 0 | 50 | 0.00 | ||
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 0 | 50 | 0.00 | ||
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 0 | 50 | 0.00 | ||
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0 | 50 | 0.00 | ||
| i2c_host_fifo_fmt_empty | 0 | 50 | 0.00 | ||||
| i2c_host_fifo_reset_rx | 0 | 50 | 0.00 | ||||
| V2 | host_fifo_full | i2c_host_fifo_full | 0 | 50 | 0.00 | ||
| V2 | host_timeout | i2c_host_stretch_timeout | 0 | 50 | 0.00 | ||
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 50 | 0.00 | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 0 | 50 | 0.00 | ||
| V2 | target_error_intr | i2c_target_unexp_stop | 0 | 50 | 0.00 | ||
| V2 | target_glitch | i2c_target_glitch | 0 | 2 | 0.00 | ||
| V2 | target_stress_all | i2c_target_stress_all | 0 | 50 | 0.00 | ||
| V2 | target_perf | i2c_target_perf | 0 | 50 | 0.00 | ||
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 0 | 50 | 0.00 | ||
| V2 | target_fifo_empty | i2c_target_stress_rd | 0 | 50 | 0.00 | ||
| i2c_target_intr_smoke | 0 | 50 | 0.00 | ||||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0 | 50 | 0.00 | ||
| i2c_target_fifo_reset_tx | 0 | 50 | 0.00 | ||||
| V2 | target_fifo_full | i2c_target_stress_wr | 0 | 50 | 0.00 | ||
| i2c_target_stress_rd | 0 | 50 | 0.00 | ||||
| i2c_target_intr_stress_wr | 0 | 50 | 0.00 | ||||
| V2 | target_timeout | i2c_target_timeout | 0 | 50 | 0.00 | ||
| V2 | target_clock_stretch | i2c_target_stretch | 0 | 50 | 0.00 | ||
| V2 | bad_address | i2c_target_bad_addr | 0 | 50 | 0.00 | ||
| V2 | target_mode_glitch | i2c_target_hrst | 0 | 50 | 0.00 | ||
| V2 | alert_test | i2c_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | i2c_intr_test | 0.790s | 137.991us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.420s | 548.087us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.420s | 548.087us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.720s | 23.010us | 4 | 5 | 80.00 |
| i2c_csr_rw | 0.820s | 26.686us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.130s | 147.157us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.980s | 41.298us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.720s | 23.010us | 4 | 5 | 80.00 |
| i2c_csr_rw | 0.820s | 26.686us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.130s | 147.157us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.980s | 41.298us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 89 | 1492 | 5.97 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.870s | 979.805us | 19 | 20 | 95.00 |
| i2c_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.870s | 979.805us | 19 | 20 | 95.00 |
| V2S | TOTAL | 19 | 25 | 76.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 162 | 1772 | 9.14 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 32 | 32 | 2 | 6.25 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 3 | 2 | 0 | 0.00 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 804 failures:
0.i2c_host_smoke.50112765426068689825966471011566613735230908499375273824441322829818585286282
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_smoke/latest/run.log
1.i2c_host_smoke.14075588801862479769394201539287609817267723584929538049573036125111485743743
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_smoke/latest/run.log
... and 2 more failures.
0.i2c_host_rx_oversample.106204253256813694994007421218516452327577263317371291034712624443045684738971
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_rx_oversample/latest/run.log
1.i2c_host_rx_oversample.50399762395523558020045824290278664758435297967453883338690806657836204373947
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_rx_oversample/latest/run.log
... and 2 more failures.
0.i2c_host_fifo_overflow.77110711010564361205639915586174569394900052057675660701183141144469229177831
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest/run.log
1.i2c_host_fifo_overflow.12557353544339852366516471334936919355349266424904277836203447988877762224298
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest/run.log
... and 2 more failures.
0.i2c_host_fifo_fmt_empty.60920018838789568162728505150773837117014517037790343521488013370063399720647
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest/run.log
1.i2c_host_fifo_fmt_empty.27567500199304379640305947873147381953910268630492255799744224703611883647731
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest/run.log
... and 2 more failures.
0.i2c_host_fifo_full.75737145004889238465466931268158183199442102610713097793171715865125046541944
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_full/latest/run.log
1.i2c_host_fifo_full.106907706117952691490364753143375812088401633208267716708031984897856765773907
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_full/latest/run.log
... and 2 more failures.
Job killed most likely because its dependent job failed. has 803 failures:
0.i2c_host_override.112903392768890698712217931547850700661766593129881351799710436735161150515064
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_override/latest/run.log
1.i2c_host_override.108683888145788822028185282756870759141007899457058705031036784664932639148419
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_override/latest/run.log
... and 2 more failures.
0.i2c_host_fifo_watermark.3136584049843637895957429258898387867567889409839503210498588372118956087105
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest/run.log
1.i2c_host_fifo_watermark.38296391519916991710732959189027566571139780345892851739930483577078014021366
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest/run.log
... and 2 more failures.
0.i2c_host_fifo_reset_fmt.39383152275345560167958583425794426177644754227001058192268152110969279568431
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest/run.log
1.i2c_host_fifo_reset_fmt.51223694456457115800383713446500988975442628144347928587359040479285508350862
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest/run.log
... and 2 more failures.
0.i2c_host_fifo_reset_rx.72891522239030962502334501006735502723499547707875883174576989959427671530354
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest/run.log
1.i2c_host_fifo_reset_rx.81132039343061695648618861958441211681595078417232641530155007340818166948285
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest/run.log
... and 2 more failures.
0.i2c_host_perf.58250851216270564086795910051563800246403790532126107964663095351397283392677
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf/latest/run.log
1.i2c_host_perf.16344920222963248987855171522015800988385915340605148483809444736505513935141
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_perf/latest/run.log
... and 2 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
1.i2c_csr_hw_reset.78671877005925379821240638295531896708389396194521599668687077598945410967537
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/1.i2c_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859179505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3859179505
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:24 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Offending 'scl_i' has 1 failures:
2.i2c_same_csr_outstanding.1287236631559401588063817655784877446375200788399119673924317655836776059565
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 6311591 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 6311591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))' has 1 failures:
3.i2c_tl_intg_err.74812197442577787872551742140494416252906846788678092952633333483339930184643
Line 327, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_intg_err/latest/run.log
Offending '(!((host_enable_i && (scl_d != scl_q)) && (sda_d != sda_q)))'
UVM_ERROR @ 66618762 ps: (i2c_fsm.sv:1366) [ASSERT FAILED] SclSdaChangeNotSimultaneous_A
UVM_INFO @ 66618762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = *:Bad Gateway has 1 failures: