Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7072170	1			T19	8		T20	5		T22	1
all_values[1]	7072170	1			T19	8		T20	5		T22	1
all_values[2]	7072170	1			T19	8		T20	5		T22	1
all_values[3]	7072170	1			T19	8		T20	5		T22	1
all_values[4]	7072170	1			T19	8		T20	5		T22	1
all_values[5]	7072170	1			T19	8		T20	5		T22	1
all_values[6]	7072170	1			T19	8		T20	5		T22	1
all_values[7]	7072170	1			T19	8		T20	5		T22	1
all_values[8]	7072170	1			T19	8		T20	5		T22	1
all_values[9]	7072170	1			T19	8		T20	5		T22	1
all_values[10]	7072170	1			T19	8		T20	5		T22	1
all_values[11]	7072170	1			T19	8		T20	5		T22	1
all_values[12]	7072170	1			T19	8		T20	5		T22	1
all_values[13]	7072170	1			T19	8		T20	5		T22	1
all_values[14]	7072170	1			T19	8		T20	5		T22	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101563948

1

T19

69

T20

53

T22

15

auto[1]

4518602

1

T19

51

T20

22

T24

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98150106

1

T19

14

T20

21

T22

15

auto[1]

7932444

1

T19

106

T20

54

T24

57

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6013802	1			T20	2		T22	1		T28	1
all_values[0]	auto[0]	auto[1]	399011	1			T19	6		T20	1		T24	2
all_values[0]	auto[1]	auto[0]	600187	1			T9	8		T11	1		T65	4672
all_values[0]	auto[1]	auto[1]	59170	1			T19	2		T20	2		T24	3
all_values[1]	auto[0]	auto[0]	6109033	1			T20	1		T22	1		T24	5
all_values[1]	auto[0]	auto[1]	483772	1			T19	5		T20	3		T27	4
all_values[1]	auto[1]	auto[0]	425464	1			T9	56		T11	1		T65	3452
all_values[1]	auto[1]	auto[1]	53901	1			T19	3		T20	1		T61	3
all_values[2]	auto[0]	auto[0]	6559062	1			T19	1		T20	2		T22	1
all_values[2]	auto[0]	auto[1]	512898	1			T19	6		T20	3		T24	2
all_values[2]	auto[1]	auto[1]	210	1			T19	1		T24	3		T27	3
all_values[3]	auto[0]	auto[0]	6534489	1			T19	8		T22	1		T24	5
all_values[3]	auto[0]	auto[1]	537460	1			T20	1		T27	1		T61	4
all_values[3]	auto[1]	auto[1]	221	1			T20	4		T27	3		T61	1
all_values[4]	auto[0]	auto[0]	6530739	1			T22	1		T28	1		T61	2
all_values[4]	auto[0]	auto[1]	541193	1			T19	6		T20	4		T24	5
all_values[4]	auto[1]	auto[0]	20	1			T143	20		-	-		-	-
all_values[4]	auto[1]	auto[1]	218	1			T19	2		T20	1		T61	2
all_values[5]	auto[0]	auto[0]	6541828	1			T20	1		T22	1		T28	1
all_values[5]	auto[0]	auto[1]	530140	1			T19	4		T20	3		T24	4
all_values[5]	auto[1]	auto[1]	202	1			T19	4		T20	1		T24	1
all_values[6]	auto[0]	auto[0]	5902933	1			T19	1		T20	1		T22	1
all_values[6]	auto[0]	auto[1]	456864	1			T19	2		T20	3		T24	1
all_values[6]	auto[1]	auto[0]	643022	1			T1	1		T9	40		T11	1
all_values[6]	auto[1]	auto[1]	69351	1			T19	5		T20	1		T24	2
all_values[7]	auto[0]	auto[0]	6254088	1			T19	1		T20	1		T22	1
all_values[7]	auto[0]	auto[1]	508271	1			T19	4		T20	1		T24	4
all_values[7]	auto[1]	auto[0]	288835	1			T1	1		T10	1		T9	1256
all_values[7]	auto[1]	auto[1]	20976	1			T19	3		T20	3		T61	4
all_values[8]	auto[0]	auto[0]	5735040	1			T22	1		T28	1		T69	1
all_values[8]	auto[0]	auto[1]	441673	1			T19	5		T20	5		T24	3
all_values[8]	auto[1]	auto[0]	803947	1			T1	1		T10	1		T9	530
all_values[8]	auto[1]	auto[1]	91510	1			T19	3		T24	2		T61	4
all_values[9]	auto[0]	auto[0]	5749069	1			T20	1		T22	1		T24	1
all_values[9]	auto[0]	auto[1]	458178	1			T19	4		T20	1		T24	1
all_values[9]	auto[1]	auto[0]	781709	1			T1	1		T51	1		T52	1
all_values[9]	auto[1]	auto[1]	83214	1			T19	4		T20	3		T24	3
all_values[10]	auto[0]	auto[0]	6388199	1			T20	5		T22	1		T28	1
all_values[10]	auto[0]	auto[1]	537089	1			T19	4		T24	3		T27	4
all_values[10]	auto[1]	auto[0]	146711	1			T15	3064		T16	1774		T162	913
all_values[10]	auto[1]	auto[1]	171	1			T19	4		T24	2		T27	1
all_values[11]	auto[0]	auto[0]	6082070	1			T19	1		T20	5		T22	1
all_values[11]	auto[0]	auto[1]	541194	1			T19	1		T24	4		T61	3
all_values[11]	auto[1]	auto[0]	448712	1			T14	2371		T15	7578		T16	6145
all_values[11]	auto[1]	auto[1]	194	1			T19	6		T90	3		T163	2
all_values[12]	auto[0]	auto[0]	6541816	1			T19	1		T20	2		T22	1
all_values[12]	auto[0]	auto[1]	530146	1			T19	3		T20	2		T24	2
all_values[12]	auto[1]	auto[1]	208	1			T19	4		T20	1		T24	1
all_values[13]	auto[0]	auto[0]	6530736	1			T22	1		T24	1		T28	1
all_values[13]	auto[0]	auto[1]	541198	1			T19	3		T20	1		T24	3
all_values[13]	auto[1]	auto[0]	8	1			T156	1		T164	1		T165	1
all_values[13]	auto[1]	auto[1]	228	1			T19	5		T20	4		T24	1
all_values[14]	auto[0]	auto[0]	6538587	1			T19	1		T22	1		T27	5
all_values[14]	auto[0]	auto[1]	533370	1			T19	2		T20	4		T24	2
all_values[14]	auto[1]	auto[1]	213	1			T19	5		T20	1		T24	3