Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 99.07 96.59 100.00 96.52 98.13 100.00 92.86


Total tests in report: 1626
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.66 59.66 45.17 45.17 42.18 42.18 88.11 88.11 96.52 96.52 40.18 40.18 76.68 76.68 28.78 28.78 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1687719928
81.64 21.98 84.38 39.21 71.72 29.55 92.96 4.85 96.52 0.00 73.11 32.93 91.96 15.28 60.82 32.04 /workspace/coverage/default/40.i2c_host_stress_all.2982015404
88.14 6.51 90.97 6.59 86.30 14.57 96.60 3.64 96.52 0.00 85.95 12.84 93.03 1.07 67.65 6.83 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3440357503
93.17 5.03 98.05 7.08 92.78 6.48 97.33 0.73 96.52 0.00 96.38 10.43 94.37 1.34 76.79 9.14 /workspace/coverage/default/3.i2c_target_stress_all.233859340
94.23 1.06 98.05 0.00 94.39 1.60 97.82 0.49 96.52 0.00 96.49 0.11 97.59 3.22 78.78 2.00 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.710740462
94.71 0.47 98.24 0.20 94.65 0.27 97.82 0.00 96.52 0.00 96.82 0.33 97.59 0.00 81.30 2.52 /workspace/coverage/default/2.i2c_host_stress_all.2581441133
95.09 0.39 98.58 0.34 94.72 0.07 99.27 1.46 96.52 0.00 97.26 0.44 97.59 0.00 81.72 0.42 /workspace/coverage/default/43.i2c_target_intr_stress_wr.793473056
95.48 0.38 98.58 0.00 94.72 0.00 99.27 0.00 96.52 0.00 97.26 0.00 97.86 0.27 84.14 2.42 /workspace/coverage/default/46.i2c_host_fifo_watermark.742520126
95.77 0.30 98.58 0.00 94.85 0.13 99.51 0.24 96.52 0.00 97.48 0.22 97.86 0.00 85.61 1.47 /workspace/coverage/default/14.i2c_host_override.4219333717
96.06 0.28 98.58 0.00 94.85 0.00 99.51 0.00 96.52 0.00 97.48 0.00 99.73 1.88 85.71 0.11 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1942861927
96.24 0.18 98.58 0.00 95.05 0.20 99.51 0.00 96.52 0.00 97.48 0.00 99.73 0.00 86.76 1.05 /workspace/coverage/default/0.i2c_target_glitch.3948419262
96.40 0.17 98.58 0.00 95.05 0.00 99.51 0.00 96.52 0.00 97.48 0.00 99.73 0.00 87.92 1.16 /workspace/coverage/default/49.i2c_host_stress_all.932395342
96.56 0.16 98.58 0.00 95.19 0.13 100.00 0.49 96.52 0.00 97.48 0.00 100.00 0.27 88.13 0.21 /workspace/coverage/default/0.i2c_sec_cm.3965614860
96.67 0.11 98.93 0.34 95.32 0.13 100.00 0.00 96.52 0.00 97.80 0.33 100.00 0.00 88.13 0.00 /workspace/coverage/default/23.i2c_host_mode_toggle.95918166
96.78 0.11 98.93 0.00 95.32 0.00 100.00 0.00 96.52 0.00 97.80 0.00 100.00 0.00 88.87 0.74 /workspace/coverage/default/16.i2c_host_stress_all.4133162831
96.86 0.08 98.97 0.05 95.52 0.20 100.00 0.00 96.52 0.00 97.91 0.11 100.00 0.00 89.08 0.21 /workspace/coverage/default/40.i2c_host_perf.1681054531
96.94 0.08 98.97 0.00 95.66 0.13 100.00 0.00 96.52 0.00 97.91 0.00 100.00 0.00 89.50 0.42 /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.607987899
97.01 0.07 98.97 0.00 95.72 0.07 100.00 0.00 96.52 0.00 97.91 0.00 100.00 0.00 89.92 0.42 /workspace/coverage/default/47.i2c_target_stress_all.1319014404
97.07 0.06 98.97 0.00 95.72 0.00 100.00 0.00 96.52 0.00 97.91 0.00 100.00 0.00 90.34 0.42 /workspace/coverage/default/44.i2c_target_hrst.953065970
97.13 0.06 98.97 0.00 95.72 0.00 100.00 0.00 96.52 0.00 97.91 0.00 100.00 0.00 90.76 0.42 /workspace/coverage/default/46.i2c_host_stress_all.4134955367
97.18 0.05 98.97 0.00 95.79 0.07 100.00 0.00 96.52 0.00 97.91 0.00 100.00 0.00 91.07 0.32 /workspace/coverage/default/38.i2c_host_stress_all.4190299487
97.23 0.05 98.97 0.00 95.79 0.00 100.00 0.00 96.52 0.00 97.91 0.00 100.00 0.00 91.39 0.32 /workspace/coverage/default/4.i2c_host_stress_all.226839439
97.27 0.04 99.02 0.05 95.92 0.13 100.00 0.00 96.52 0.00 98.02 0.11 100.00 0.00 91.39 0.00 /workspace/coverage/default/10.i2c_target_bad_addr.616950029
97.30 0.03 99.02 0.00 95.92 0.00 100.00 0.00 96.52 0.00 98.02 0.00 100.00 0.00 91.60 0.21 /workspace/coverage/default/13.i2c_host_rx_oversample.2092801303
97.33 0.03 99.02 0.00 95.92 0.00 100.00 0.00 96.52 0.00 98.02 0.00 100.00 0.00 91.81 0.21 /workspace/coverage/default/17.i2c_host_override.1445306599
97.36 0.03 99.02 0.00 96.12 0.20 100.00 0.00 96.52 0.00 98.02 0.00 100.00 0.00 91.81 0.00 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3040779405
97.38 0.03 99.07 0.05 96.26 0.13 100.00 0.00 96.52 0.00 98.02 0.00 100.00 0.00 91.81 0.00 /workspace/coverage/default/1.i2c_alert_test.1272285380
97.41 0.03 99.07 0.00 96.32 0.07 100.00 0.00 96.52 0.00 98.13 0.11 100.00 0.00 91.81 0.00 /workspace/coverage/default/10.i2c_target_stretch.1376957444
97.43 0.02 99.07 0.00 96.46 0.13 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 91.81 0.00 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.159756790
97.44 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 91.91 0.11 /workspace/coverage/default/1.i2c_host_stress_all.3707867788
97.46 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.02 0.11 /workspace/coverage/default/10.i2c_host_rx_oversample.2702668626
97.47 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.12 0.11 /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1440278583
97.49 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.23 0.11 /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.555983392
97.50 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.33 0.11 /workspace/coverage/default/13.i2c_host_mode_toggle.3429260883
97.52 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.44 0.11 /workspace/coverage/default/15.i2c_host_stress_all.2541877183
97.53 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.54 0.11 /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2627399000
97.55 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.65 0.11 /workspace/coverage/default/20.i2c_target_unexp_stop.1625949180
97.56 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.75 0.11 /workspace/coverage/default/22.i2c_host_stress_all.1328099261
97.58 0.02 99.07 0.00 96.46 0.00 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.86 0.11 /workspace/coverage/default/32.i2c_host_stretch_timeout.2731467343
97.59 0.01 99.07 0.00 96.52 0.07 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4033826144
97.60 0.01 99.07 0.00 96.59 0.07 100.00 0.00 96.52 0.00 98.13 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1091479656


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.86258409
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3679042709
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3820703461
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4281571418
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.3758663520
/workspace/coverage/cover_reg_top/0.i2c_intr_test.965190113
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.646527561
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.966489307
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.331649024
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1668263647
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1150984676
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2886676583
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4154783779
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.876825441
/workspace/coverage/cover_reg_top/1.i2c_intr_test.85633055
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.454298315
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.138100801
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3710428251
/workspace/coverage/cover_reg_top/10.i2c_intr_test.22831435
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.959075118
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2270955130
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1605788095
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.2509198574
/workspace/coverage/cover_reg_top/11.i2c_intr_test.3193399426
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.30334504
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.3854925243
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4199717335
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4197107593
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.1136090766
/workspace/coverage/cover_reg_top/12.i2c_intr_test.2548314594
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3138372011
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3272434953
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3072997565
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.2094398670
/workspace/coverage/cover_reg_top/13.i2c_intr_test.3983162212
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1347317993
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.1545134512
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.605253276
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3852914968
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.4196964775
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3910620782
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.265114177
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3507819605
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2829558917
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1312832177
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.51595246
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1252978369
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1146531615
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.1377794029
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1192459322
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.515483000
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.893095631
/workspace/coverage/cover_reg_top/16.i2c_intr_test.3552772853
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2801596206
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.1877889844
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3184527155
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2320374064
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.809860159
/workspace/coverage/cover_reg_top/17.i2c_intr_test.299212281
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2099282483
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.1755597290
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.689646292
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3582865214
/workspace/coverage/cover_reg_top/18.i2c_intr_test.925156635
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1918957054
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.227037665
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4235538316
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.298903201
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3191280311
/workspace/coverage/cover_reg_top/19.i2c_intr_test.3892030077
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2033221993
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3128086482
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1008597806
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2541041892
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2123367863
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2027662336
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1911823076
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.405429384
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1641575477
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.512030801
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2308155488
/workspace/coverage/cover_reg_top/20.i2c_intr_test.830183673
/workspace/coverage/cover_reg_top/21.i2c_intr_test.1106666882
/workspace/coverage/cover_reg_top/22.i2c_intr_test.322435303
/workspace/coverage/cover_reg_top/23.i2c_intr_test.3490354682
/workspace/coverage/cover_reg_top/24.i2c_intr_test.3781399810
/workspace/coverage/cover_reg_top/25.i2c_intr_test.1507069842
/workspace/coverage/cover_reg_top/26.i2c_intr_test.2399042736
/workspace/coverage/cover_reg_top/27.i2c_intr_test.2092561812
/workspace/coverage/cover_reg_top/28.i2c_intr_test.161366678
/workspace/coverage/cover_reg_top/29.i2c_intr_test.128615440
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1657928602
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.629197096
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3308349916
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1255774390
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.844879649
/workspace/coverage/cover_reg_top/3.i2c_intr_test.2701413105
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3571509304
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2114811994
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1073329682
/workspace/coverage/cover_reg_top/30.i2c_intr_test.3172087015
/workspace/coverage/cover_reg_top/31.i2c_intr_test.4159148833
/workspace/coverage/cover_reg_top/32.i2c_intr_test.658267406
/workspace/coverage/cover_reg_top/33.i2c_intr_test.512771272
/workspace/coverage/cover_reg_top/34.i2c_intr_test.3713168710
/workspace/coverage/cover_reg_top/35.i2c_intr_test.2241909898
/workspace/coverage/cover_reg_top/36.i2c_intr_test.3509212459
/workspace/coverage/cover_reg_top/37.i2c_intr_test.2018933484
/workspace/coverage/cover_reg_top/38.i2c_intr_test.1328894422
/workspace/coverage/cover_reg_top/39.i2c_intr_test.1863437361
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3416792497
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2109479867
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.49935720
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2539891667
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.904356399
/workspace/coverage/cover_reg_top/4.i2c_intr_test.1988118300
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2613434844
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3108191417
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2656182453
/workspace/coverage/cover_reg_top/40.i2c_intr_test.515943817
/workspace/coverage/cover_reg_top/41.i2c_intr_test.4101755196
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3742912367
/workspace/coverage/cover_reg_top/43.i2c_intr_test.190077248
/workspace/coverage/cover_reg_top/44.i2c_intr_test.4009640858
/workspace/coverage/cover_reg_top/45.i2c_intr_test.3450076693
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3377108458
/workspace/coverage/cover_reg_top/47.i2c_intr_test.1955591228
/workspace/coverage/cover_reg_top/48.i2c_intr_test.564637378
/workspace/coverage/cover_reg_top/49.i2c_intr_test.1537212727
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2511856630
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.4010178012
/workspace/coverage/cover_reg_top/5.i2c_intr_test.441347510
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.125505958
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.2905146903
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4263415422
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3159971762
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.998357470
/workspace/coverage/cover_reg_top/6.i2c_intr_test.1528335003
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1881833744
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3648854796
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.391491754
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3358337797
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.566249132
/workspace/coverage/cover_reg_top/7.i2c_intr_test.1523200087
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3143332150
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.1589373589
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2946559217
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3810126678
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2539546130
/workspace/coverage/cover_reg_top/8.i2c_intr_test.3680904148
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.535343593
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.3753418125
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3885696657
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1572077957
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/workspace/coverage/default/9.i2c_host_error_intr.2923476036
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/workspace/coverage/default/9.i2c_target_timeout.3188604601
/workspace/coverage/default/9.i2c_target_tx_ovf.2021023161
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Total test records in report: 1626
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T19 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1687719928 Dec 27 12:44:11 PM PST 23 Dec 27 12:44:22 PM PST 23 18125113 ps
T20 /workspace/coverage/cover_reg_top/48.i2c_intr_test.564637378 Dec 27 12:44:31 PM PST 23 Dec 27 12:44:40 PM PST 23 18988482 ps
T21 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3440357503 Dec 27 12:44:00 PM PST 23 Dec 27 12:44:15 PM PST 23 84700887 ps
T22 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.710740462 Dec 27 12:44:06 PM PST 23 Dec 27 12:44:21 PM PST 23 147969103 ps
T23 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.636657264 Dec 27 12:44:05 PM PST 23 Dec 27 12:44:18 PM PST 23 45124648 ps
T24 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1955591228 Dec 27 12:44:24 PM PST 23 Dec 27 12:44:34 PM PST 23 55911354 ps
T25 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1641575477 Dec 27 12:44:03 PM PST 23 Dec 27 12:44:17 PM PST 23 28719890 ps
T26 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1942861927 Dec 27 12:44:01 PM PST 23 Dec 27 12:44:15 PM PST 23 21317415 ps
T27 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3172087015 Dec 27 12:44:19 PM PST 23 Dec 27 12:44:29 PM PST 23 28470328 ps
T28 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1377794029 Dec 27 12:43:54 PM PST 23 Dec 27 12:44:10 PM PST 23 195325850 ps
T61 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3377108458 Dec 27 12:44:18 PM PST 23 Dec 27 12:44:29 PM PST 23 27565607 ps
T73 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2829558917 Dec 27 12:43:50 PM PST 23 Dec 27 12:44:08 PM PST 23 70082483 ps
T103 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3416792497 Dec 27 12:43:57 PM PST 23 Dec 27 12:44:12 PM PST 23 71770259 ps
T81 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4199717335 Dec 27 12:44:04 PM PST 23 Dec 27 12:44:18 PM PST 23 228881241 ps
T80 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2027662336 Dec 27 12:43:55 PM PST 23 Dec 27 12:44:10 PM PST 23 43834281 ps
T104 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.844879649 Dec 27 12:43:44 PM PST 23 Dec 27 12:44:04 PM PST 23 24970181 ps
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