Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7072170	1			T19	8		T20	5		T22	1
all_pins[1]	7072170	1			T19	8		T20	5		T22	1
all_pins[2]	7072170	1			T19	8		T20	5		T22	1
all_pins[3]	7072170	1			T19	8		T20	5		T22	1
all_pins[4]	7072170	1			T19	8		T20	5		T22	1
all_pins[5]	7072170	1			T19	8		T20	5		T22	1
all_pins[6]	7072170	1			T19	8		T20	5		T22	1
all_pins[7]	7072170	1			T19	8		T20	5		T22	1
all_pins[8]	7072170	1			T19	8		T20	5		T22	1
all_pins[9]	7072170	1			T19	8		T20	5		T22	1
all_pins[10]	7072170	1			T19	8		T20	5		T22	1
all_pins[11]	7072170	1			T19	8		T20	5		T22	1
all_pins[12]	7072170	1			T19	8		T20	5		T22	1
all_pins[13]	7072170	1			T19	8		T20	5		T22	1
all_pins[14]	7072170	1			T19	8		T20	5		T22	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	101494839	1			T19	102		T20	58		T22	15
values[0x1]	4587711	1			T19	18		T20	17		T24	11
transitions[0x0=>0x1]	3151401	1			T19	16		T20	15		T24	10
transitions[0x1=>0x0]	3151410	1			T19	16		T20	15		T24	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6412554	1			T19	8		T20	5		T22	1
all_pins[0]	values[0x1]	659616	1			T24	3		T27	2		T89	2
all_pins[0]	transitions[0x0=>0x1]	206015	1			T24	3		T27	2		T89	2
all_pins[0]	transitions[0x1=>0x0]	28619	1			T19	1		T20	1		T181	3
all_pins[1]	values[0x0]	6589950	1			T19	7		T20	4		T22	1
all_pins[1]	values[0x1]	482220	1			T19	1		T20	1		T90	1
all_pins[1]	transitions[0x0=>0x1]	482208	1			T19	1		T20	1		T90	1
all_pins[1]	transitions[0x1=>0x0]	95	1			T24	3		T27	1		T89	3
all_pins[2]	values[0x0]	7072063	1			T19	8		T20	5		T22	1
all_pins[2]	values[0x1]	107	1			T24	3		T27	1		T89	3
all_pins[2]	transitions[0x0=>0x1]	81	1			T24	3		T89	3		T90	1
all_pins[2]	transitions[0x1=>0x0]	80	1			T20	3		T61	1		T90	1
all_pins[3]	values[0x0]	7072064	1			T19	8		T20	2		T22	1
all_pins[3]	values[0x1]	106	1			T20	3		T27	1		T61	1
all_pins[3]	transitions[0x0=>0x1]	79	1			T20	3		T27	1		T61	1
all_pins[3]	transitions[0x1=>0x0]	135	1			T19	2		T20	1		T163	2
all_pins[4]	values[0x0]	7072008	1			T19	6		T20	4		T22	1
all_pins[4]	values[0x1]	162	1			T19	2		T20	1		T163	2
all_pins[4]	transitions[0x0=>0x1]	136	1			T19	2		T20	1		T181	2
all_pins[4]	transitions[0x1=>0x0]	63	1			T20	1		T27	1		T61	1
all_pins[5]	values[0x0]	7072081	1			T19	8		T20	4		T22	1
all_pins[5]	values[0x1]	89	1			T20	1		T27	1		T61	1
all_pins[5]	transitions[0x0=>0x1]	72	1			T27	1		T61	1		T163	2
all_pins[5]	transitions[0x1=>0x0]	715870	1			T19	1		T89	1		T163	1
all_pins[6]	values[0x0]	6356283	1			T19	7		T20	4		T22	1
all_pins[6]	values[0x1]	715887	1			T19	1		T20	1		T89	1
all_pins[6]	transitions[0x0=>0x1]	696871	1			T19	1		T20	1		T89	1
all_pins[6]	transitions[0x1=>0x0]	327880	1			T20	2		T61	2		T90	1
all_pins[7]	values[0x0]	6725274	1			T19	8		T20	3		T22	1
all_pins[7]	values[0x1]	346896	1			T20	2		T61	2		T90	1
all_pins[7]	transitions[0x0=>0x1]	282243	1			T20	2		T61	1		T90	1
all_pins[7]	transitions[0x1=>0x0]	855844	1			T19	2		T24	1		T163	1
all_pins[8]	values[0x0]	6151673	1			T19	6		T20	5		T22	1
all_pins[8]	values[0x1]	920497	1			T19	2		T24	1		T61	1
all_pins[8]	transitions[0x0=>0x1]	238876	1			T19	2		T24	1		T163	1
all_pins[8]	transitions[0x1=>0x0]	184282	1			T19	1		T20	3		T90	1
all_pins[9]	values[0x0]	6206267	1			T19	7		T20	2		T22	1
all_pins[9]	values[0x1]	865903	1			T19	1		T20	3		T61	1
all_pins[9]	transitions[0x0=>0x1]	792098	1			T20	3		T61	1		T90	1
all_pins[9]	transitions[0x1=>0x0]	73298	1			T19	1		T24	2		T27	1
all_pins[10]	values[0x0]	6925067	1			T19	6		T20	5		T22	1
all_pins[10]	values[0x1]	147103	1			T19	2		T24	2		T27	1
all_pins[10]	transitions[0x0=>0x1]	3680	1			T19	2		T24	2		T27	1
all_pins[10]	transitions[0x1=>0x0]	305389	1			T19	4		T90	2		T163	2
all_pins[11]	values[0x0]	6623358	1			T19	4		T20	5		T22	1
all_pins[11]	values[0x1]	448812	1			T19	4		T90	2		T163	2
all_pins[11]	transitions[0x0=>0x1]	448797	1			T19	4		T90	2		T163	2
all_pins[11]	transitions[0x1=>0x0]	84	1			T19	2		T20	1		T27	1
all_pins[12]	values[0x0]	7072071	1			T19	6		T20	4		T22	1
all_pins[12]	values[0x1]	99	1			T19	2		T20	1		T27	1
all_pins[12]	transitions[0x0=>0x1]	76	1			T19	1		T27	1		T163	2
all_pins[12]	transitions[0x1=>0x0]	102	1			T19	1		T20	3		T24	1
all_pins[13]	values[0x0]	7072045	1			T19	6		T20	1		T22	1
all_pins[13]	values[0x1]	125	1			T19	2		T20	4		T24	1
all_pins[13]	transitions[0x0=>0x1]	107	1			T19	2		T20	4		T24	1
all_pins[13]	transitions[0x1=>0x0]	71	1			T19	1		T24	1		T89	1
all_pins[14]	values[0x0]	7072081	1			T19	7		T20	5		T22	1
all_pins[14]	values[0x1]	89	1			T19	1		T24	1		T89	1
all_pins[14]	transitions[0x0=>0x1]	62	1			T19	1		T90	1		T163	1
all_pins[14]	transitions[0x1=>0x0]	659598	1			T24	3		T27	2		T89	2