Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T19	7		T20	4		T24	4
all_values[1]	468	1			T19	7		T20	4		T24	4
all_values[2]	468	1			T19	7		T20	4		T24	4
all_values[3]	468	1			T19	7		T20	4		T24	4
all_values[4]	468	1			T19	7		T20	4		T24	4
all_values[5]	468	1			T19	7		T20	4		T24	4
all_values[6]	468	1			T19	7		T20	4		T24	4
all_values[7]	468	1			T19	7		T20	4		T24	4
all_values[8]	468	1			T19	7		T20	4		T24	4
all_values[9]	468	1			T19	7		T20	4		T24	4
all_values[10]	468	1			T19	7		T20	4		T24	4
all_values[11]	468	1			T19	7		T20	4		T24	4
all_values[12]	468	1			T19	7		T20	4		T24	4
all_values[13]	468	1			T19	7		T20	4		T24	4
all_values[14]	468	1			T19	7		T20	4		T24	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3760

1

T19

73

T20

36

T24

34

auto[1]

3260

1

T19

32

T20

24

T24

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T19

13

T20

19

T24

16

auto[1]

5889

1

T19

92

T20

41

T24

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4152

1

T19

56

T20

40

T24

40

auto[1]

2868

1

T19

49

T20

20

T24

20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	46	1			T20	1		T182	1		T3	1
all_values[0]	auto[0]	auto[0]	auto[1]	113	1			T19	4		T20	1		T61	2
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T20	1		T3	1		T125	1
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T24	2		T27	2		T89	1
all_values[0]	auto[1]	auto[0]	auto[1]	109	1			T19	3		T20	1		T24	1
all_values[0]	auto[1]	auto[1]	auto[1]	99	1			T24	1		T27	2		T89	2
all_values[1]	auto[0]	auto[0]	auto[0]	53	1			T20	1		T24	2		T27	1
all_values[1]	auto[0]	auto[0]	auto[1]	109	1			T19	2		T27	2		T61	1
all_values[1]	auto[0]	auto[1]	auto[0]	38	1			T24	2		T122	2		T124	1
all_values[1]	auto[0]	auto[1]	auto[1]	89	1			T19	1		T20	1		T90	1
all_values[1]	auto[1]	auto[0]	auto[1]	105	1			T19	1		T27	1		T61	2
all_values[1]	auto[1]	auto[1]	auto[1]	74	1			T19	3		T20	2		T181	2
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T19	1		T20	1		T183	1
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T19	1		T20	1		T27	1
all_values[2]	auto[0]	auto[1]	auto[0]	39	1			T20	1		T163	1		T75	2
all_values[2]	auto[0]	auto[1]	auto[1]	97	1			T19	3		T24	2		T89	1
all_values[2]	auto[1]	auto[0]	auto[1]	101	1			T19	1		T20	1		T24	2
all_values[2]	auto[1]	auto[1]	auto[1]	89	1			T19	1		T27	2		T61	1
all_values[3]	auto[0]	auto[0]	auto[0]	46	1			T19	3		T24	2		T182	1
all_values[3]	auto[0]	auto[0]	auto[1]	104	1			T27	2		T61	1		T90	2
all_values[3]	auto[0]	auto[1]	auto[0]	37	1			T19	4		T24	2		T27	1
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T20	2		T61	2		T89	2
all_values[3]	auto[1]	auto[0]	auto[1]	97	1			T20	1		T61	1		T89	2
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T20	1		T27	1		T181	1
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T61	1		T90	1		T123	1
all_values[4]	auto[0]	auto[0]	auto[1]	111	1			T19	2		T20	1		T27	1
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T61	1		T122	1		T125	2
all_values[4]	auto[0]	auto[1]	auto[1]	98	1			T19	1		T20	1		T24	2
all_values[4]	auto[1]	auto[0]	auto[1]	96	1			T19	3		T20	1		T24	1
all_values[4]	auto[1]	auto[1]	auto[1]	91	1			T19	1		T20	1		T24	1
all_values[5]	auto[0]	auto[0]	auto[0]	39	1			T20	1		T89	1		T90	1
all_values[5]	auto[0]	auto[0]	auto[1]	120	1			T19	4		T20	1		T61	1
all_values[5]	auto[0]	auto[1]	auto[0]	27	1			T89	3		T90	1		T163	1
all_values[5]	auto[0]	auto[1]	auto[1]	93	1			T24	2		T27	1		T163	2
all_values[5]	auto[1]	auto[0]	auto[1]	105	1			T19	3		T20	1		T24	2
all_values[5]	auto[1]	auto[1]	auto[1]	84	1			T20	1		T27	1		T61	1
all_values[6]	auto[0]	auto[0]	auto[0]	52	1			T19	1		T20	1		T24	2
all_values[6]	auto[0]	auto[0]	auto[1]	100	1			T19	1		T20	2		T24	1
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T122	1		T124	1		T125	1
all_values[6]	auto[0]	auto[1]	auto[1]	91	1			T19	1		T89	2		T163	1
all_values[6]	auto[1]	auto[0]	auto[1]	113	1			T19	3		T24	1		T61	2
all_values[6]	auto[1]	auto[1]	auto[1]	88	1			T19	1		T20	1		T90	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T19	1		T20	1		T24	1
all_values[7]	auto[0]	auto[0]	auto[1]	92	1			T19	3		T61	1		T89	1
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T27	2		T30	2		T75	1
all_values[7]	auto[0]	auto[1]	auto[1]	112	1			T20	1		T24	2		T61	1
all_values[7]	auto[1]	auto[0]	auto[1]	100	1			T19	3		T20	1		T61	1
all_values[7]	auto[1]	auto[1]	auto[1]	89	1			T20	1		T24	1		T61	1
all_values[8]	auto[0]	auto[0]	auto[0]	29	1			T89	1		T90	1		T75	1
all_values[8]	auto[0]	auto[0]	auto[1]	94	1			T19	3		T20	3		T24	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T122	1		T124	3		T184	1
all_values[8]	auto[0]	auto[1]	auto[1]	122	1			T19	1		T24	1		T27	1
all_values[8]	auto[1]	auto[0]	auto[1]	99	1			T19	2		T20	1		T24	1
all_values[8]	auto[1]	auto[1]	auto[1]	99	1			T19	1		T27	1		T89	1
all_values[9]	auto[0]	auto[0]	auto[0]	50	1			T20	1		T24	1		T27	2
all_values[9]	auto[0]	auto[0]	auto[1]	106	1			T19	3		T24	1		T61	2
all_values[9]	auto[0]	auto[1]	auto[0]	39	1			T27	2		T163	4		T181	1
all_values[9]	auto[0]	auto[1]	auto[1]	93	1			T19	1		T20	2		T89	2
all_values[9]	auto[1]	auto[0]	auto[1]	88	1			T19	2		T24	2		T61	1
all_values[9]	auto[1]	auto[1]	auto[1]	92	1			T19	1		T20	1		T61	1
all_values[10]	auto[0]	auto[0]	auto[0]	60	1			T20	2		T61	3		T89	2
all_values[10]	auto[0]	auto[0]	auto[1]	113	1			T19	1		T27	2		T90	1
all_values[10]	auto[0]	auto[1]	auto[0]	40	1			T20	2		T61	1		T89	2
all_values[10]	auto[0]	auto[1]	auto[1]	83	1			T19	2		T24	2		T27	1
all_values[10]	auto[1]	auto[0]	auto[1]	99	1			T19	2		T24	1		T90	1
all_values[10]	auto[1]	auto[1]	auto[1]	73	1			T19	2		T24	1		T27	1
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T19	1		T20	4		T24	1
all_values[11]	auto[0]	auto[0]	auto[1]	107	1			T19	1		T24	1		T89	2
all_values[11]	auto[0]	auto[1]	auto[0]	42	1			T27	2		T181	1		T123	1
all_values[11]	auto[0]	auto[1]	auto[1]	95	1			T19	1		T24	1		T61	1
all_values[11]	auto[1]	auto[0]	auto[1]	90	1			T19	2		T24	1		T61	1
all_values[11]	auto[1]	auto[1]	auto[1]	86	1			T19	2		T89	1		T163	3
all_values[12]	auto[0]	auto[0]	auto[0]	34	1			T19	1		T20	2		T24	1
all_values[12]	auto[0]	auto[0]	auto[1]	94	1			T19	2		T24	1		T61	1
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T24	1		T27	1		T163	2
all_values[12]	auto[0]	auto[1]	auto[1]	108	1			T20	1		T27	1		T61	2
all_values[12]	auto[1]	auto[0]	auto[1]	118	1			T19	1		T24	1		T61	1
all_values[12]	auto[1]	auto[1]	auto[1]	91	1			T19	3		T20	1		T27	2
all_values[13]	auto[0]	auto[0]	auto[0]	35	1			T24	1		T89	1		T182	1
all_values[13]	auto[0]	auto[0]	auto[1]	98	1			T19	3		T24	1		T27	2
all_values[13]	auto[0]	auto[1]	auto[0]	21	1			T89	1		T124	1		T125	1
all_values[13]	auto[0]	auto[1]	auto[1]	109	1			T20	1		T24	1		T61	1
all_values[13]	auto[1]	auto[0]	auto[1]	99	1			T19	3		T20	1		T27	2
all_values[13]	auto[1]	auto[1]	auto[1]	106	1			T19	1		T20	2		T24	1
all_values[14]	auto[0]	auto[0]	auto[0]	44	1			T19	1		T27	4		T61	2
all_values[14]	auto[0]	auto[0]	auto[1]	107	1			T19	1		T20	3		T24	1
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T61	2		T182	1		T3	1
all_values[14]	auto[0]	auto[1]	auto[1]	97	1			T19	1		T24	1		T89	1
all_values[14]	auto[1]	auto[0]	auto[1]	102	1			T19	4		T20	1		T24	2
all_values[14]	auto[1]	auto[1]	auto[1]	93	1			T90	1		T163	1		T181	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal