Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7447772	1			T21	8		T22	1		T23	5
all_values[1]	7447772	1			T21	8		T22	1		T23	5
all_values[2]	7447772	1			T21	8		T22	1		T23	5
all_values[3]	7447772	1			T21	8		T22	1		T23	5
all_values[4]	7447772	1			T21	8		T22	1		T23	5
all_values[5]	7447772	1			T21	8		T22	1		T23	5
all_values[6]	7447772	1			T21	8		T22	1		T23	5
all_values[7]	7447772	1			T21	8		T22	1		T23	5
all_values[8]	7447772	1			T21	8		T22	1		T23	5
all_values[9]	7447772	1			T21	8		T22	1		T23	5
all_values[10]	7447772	1			T21	8		T22	1		T23	5
all_values[11]	7447772	1			T21	8		T22	1		T23	5
all_values[12]	7447772	1			T21	8		T22	1		T23	5
all_values[13]	7447772	1			T21	8		T22	1		T23	5
all_values[14]	7447772	1			T21	8		T22	1		T23	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106334590

1

T21

78

T22

15

T23

48

auto[1]

5381990

1

T21

42

T23

27

T24

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103627241

1

T21

12

T22

15

T23

23

auto[1]

8089339

1

T21

108

T23

52

T24

52

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6162059	1			T21	1		T22	1		T23	1
all_values[0]	auto[0]	auto[1]	454886	1			T21	6		T23	3		T26	3
all_values[0]	auto[1]	auto[0]	726543	1			T11	20588		T63	1		T12	1
all_values[0]	auto[1]	auto[1]	104284	1			T21	1		T23	1		T26	4
all_values[1]	auto[0]	auto[0]	6463774	1			T21	1		T22	1		T26	2
all_values[1]	auto[0]	auto[1]	387090	1			T21	4		T23	2		T24	4
all_values[1]	auto[1]	auto[0]	536405	1			T11	13458		T12	1		T13	1
all_values[1]	auto[1]	auto[1]	60503	1			T21	3		T23	3		T24	1
all_values[2]	auto[0]	auto[0]	6888600	1			T22	1		T23	1		T27	1
all_values[2]	auto[0]	auto[1]	558927	1			T21	3		T23	1		T24	4
all_values[2]	auto[1]	auto[1]	245	1			T21	5		T23	3		T24	1
all_values[3]	auto[0]	auto[0]	6890946	1			T22	1		T23	2		T24	1
all_values[3]	auto[0]	auto[1]	556588	1			T21	7		T23	1		T24	3
all_values[3]	auto[1]	auto[1]	238	1			T21	1		T23	2		T24	1
all_values[4]	auto[0]	auto[0]	6904343	1			T21	1		T22	1		T26	1
all_values[4]	auto[0]	auto[1]	543114	1			T21	4		T23	3		T24	4
all_values[4]	auto[1]	auto[0]	61	1			T48	61		-	-		-	-
all_values[4]	auto[1]	auto[1]	254	1			T21	3		T23	2		T24	1
all_values[5]	auto[0]	auto[0]	6892486	1			T22	1		T23	1		T24	1
all_values[5]	auto[0]	auto[1]	555032	1			T21	3		T23	2		T24	4
all_values[5]	auto[1]	auto[1]	254	1			T21	5		T23	2		T26	2
all_values[6]	auto[0]	auto[0]	6117992	1			T21	2		T22	1		T23	2
all_values[6]	auto[0]	auto[1]	446877	1			T21	4		T23	1		T24	3
all_values[6]	auto[1]	auto[0]	774968	1			T1	1		T10	1		T11	20323
all_values[6]	auto[1]	auto[1]	107935	1			T21	2		T23	2		T24	2
all_values[7]	auto[0]	auto[0]	6616692	1			T21	3		T22	1		T23	5
all_values[7]	auto[0]	auto[1]	505030	1			T21	2		T24	4		T26	6
all_values[7]	auto[1]	auto[0]	303891	1			T1	1		T10	1		T11	757
all_values[7]	auto[1]	auto[1]	22159	1			T21	3		T26	2		T27	4
all_values[8]	auto[0]	auto[0]	5943295	1			T21	1		T22	1		T27	2
all_values[8]	auto[0]	auto[1]	434986	1			T21	5		T23	1		T24	4
all_values[8]	auto[1]	auto[0]	951521	1			T1	1		T10	1		T11	21612
all_values[8]	auto[1]	auto[1]	117970	1			T21	2		T23	4		T24	1
all_values[9]	auto[0]	auto[0]	6005419	1			T21	1		T22	1		T23	5
all_values[9]	auto[0]	auto[1]	403956	1			T21	4		T24	1		T26	4
all_values[9]	auto[1]	auto[0]	946414	1			T1	1		T10	1		T11	20341
all_values[9]	auto[1]	auto[1]	91983	1			T21	3		T24	2		T26	4
all_values[10]	auto[0]	auto[0]	6735043	1			T21	1		T22	1		T24	5
all_values[10]	auto[0]	auto[1]	558947	1			T21	3		T23	4		T26	4
all_values[10]	auto[1]	auto[0]	153538	1			T15	1788		T16	2354		T17	2934
all_values[10]	auto[1]	auto[1]	244	1			T21	4		T23	1		T26	3
all_values[11]	auto[0]	auto[0]	6438128	1			T22	1		T24	5		T26	1
all_values[11]	auto[0]	auto[1]	527808	1			T21	6		T23	3		T26	4
all_values[11]	auto[1]	auto[0]	481592	1			T15	6895		T16	4518		T17	5334
all_values[11]	auto[1]	auto[1]	244	1			T21	2		T23	2		T26	3
all_values[12]	auto[0]	auto[0]	6916319	1			T22	1		T23	5		T24	1
all_values[12]	auto[0]	auto[1]	531220	1			T21	4		T24	3		T26	3
all_values[12]	auto[1]	auto[1]	233	1			T21	4		T24	1		T26	5
all_values[13]	auto[0]	auto[0]	6888605	1			T21	1		T22	1		T23	1
all_values[13]	auto[0]	auto[1]	558906	1			T21	4		T23	1		T24	4
all_values[13]	auto[1]	auto[0]	12	1			T176	1		T177	1		T178	1
all_values[13]	auto[1]	auto[1]	249	1			T21	3		T23	3		T26	4
all_values[14]	auto[0]	auto[0]	6888595	1			T22	1		T24	1		T26	1
all_values[14]	auto[0]	auto[1]	558927	1			T21	7		T23	3		T24	3
all_values[14]	auto[1]	auto[1]	250	1			T21	1		T23	2		T24	1