Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7447772	1			T21	8		T22	1		T23	5
all_pins[1]	7447772	1			T21	8		T22	1		T23	5
all_pins[2]	7447772	1			T21	8		T22	1		T23	5
all_pins[3]	7447772	1			T21	8		T22	1		T23	5
all_pins[4]	7447772	1			T21	8		T22	1		T23	5
all_pins[5]	7447772	1			T21	8		T22	1		T23	5
all_pins[6]	7447772	1			T21	8		T22	1		T23	5
all_pins[7]	7447772	1			T21	8		T22	1		T23	5
all_pins[8]	7447772	1			T21	8		T22	1		T23	5
all_pins[9]	7447772	1			T21	8		T22	1		T23	5
all_pins[10]	7447772	1			T21	8		T22	1		T23	5
all_pins[11]	7447772	1			T21	8		T22	1		T23	5
all_pins[12]	7447772	1			T21	8		T22	1		T23	5
all_pins[13]	7447772	1			T21	8		T22	1		T23	5
all_pins[14]	7447772	1			T21	8		T22	1		T23	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	106261203	1			T21	100		T22	15		T23	61
values[0x1]	5455377	1			T21	20		T23	14		T24	8
transitions[0x0=>0x1]	3716057	1			T21	17		T23	10		T24	7
transitions[0x1=>0x0]	3716071	1			T21	18		T23	10		T24	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6616760	1			T21	8		T22	1		T23	5
all_pins[0]	values[0x1]	831012	1			T26	3		T27	2		T95	1
all_pins[0]	transitions[0x0=>0x1]	257377	1			T26	2		T27	2		T95	1
all_pins[0]	transitions[0x1=>0x0]	25946	1			T21	2		T23	2		T24	1
all_pins[1]	values[0x0]	6848191	1			T21	6		T22	1		T23	3
all_pins[1]	values[0x1]	599581	1			T21	2		T23	2		T24	1
all_pins[1]	transitions[0x0=>0x1]	599555	1			T21	1		T26	1		T27	2
all_pins[1]	transitions[0x1=>0x0]	106	1			T21	2		T26	1		T27	1
all_pins[2]	values[0x0]	7447640	1			T21	5		T22	1		T23	3
all_pins[2]	values[0x1]	132	1			T21	3		T23	2		T24	1
all_pins[2]	transitions[0x0=>0x1]	99	1			T21	3		T23	2		T24	1
all_pins[2]	transitions[0x1=>0x0]	89	1			T26	2		T27	1		T28	3
all_pins[3]	values[0x0]	7447650	1			T21	8		T22	1		T23	5
all_pins[3]	values[0x1]	122	1			T26	2		T27	2		T28	3
all_pins[3]	transitions[0x0=>0x1]	89	1			T26	2		T27	1		T110	1
all_pins[3]	transitions[0x1=>0x0]	175	1			T21	1		T24	1		T26	1
all_pins[4]	values[0x0]	7447564	1			T21	7		T22	1		T23	5
all_pins[4]	values[0x1]	208	1			T21	1		T24	1		T26	1
all_pins[4]	transitions[0x0=>0x1]	173	1			T21	1		T24	1		T26	1
all_pins[4]	transitions[0x1=>0x0]	94	1			T23	2		T27	1		T95	2
all_pins[5]	values[0x0]	7447643	1			T21	8		T22	1		T23	3
all_pins[5]	values[0x1]	129	1			T23	2		T27	2		T28	1
all_pins[5]	transitions[0x0=>0x1]	81	1			T27	2		T95	2		T140	2
all_pins[5]	transitions[0x1=>0x0]	886423	1			T21	2		T24	1		T26	3
all_pins[6]	values[0x0]	6561301	1			T21	6		T22	1		T23	3
all_pins[6]	values[0x1]	886471	1			T21	2		T23	2		T24	1
all_pins[6]	transitions[0x0=>0x1]	863364	1			T21	2		T23	2		T24	1
all_pins[6]	transitions[0x1=>0x0]	342948	1			T21	2		T26	1		T27	1
all_pins[7]	values[0x0]	7081717	1			T21	6		T22	1		T23	5
all_pins[7]	values[0x1]	366055	1			T21	2		T26	1		T27	1
all_pins[7]	transitions[0x0=>0x1]	298207	1			T21	2		T26	1		T27	1
all_pins[7]	transitions[0x1=>0x0]	1028369	1			T21	1		T23	3		T26	3
all_pins[8]	values[0x0]	6351555	1			T21	7		T22	1		T23	2
all_pins[8]	values[0x1]	1096217	1			T21	1		T23	3		T26	3
all_pins[8]	transitions[0x0=>0x1]	252185	1			T21	1		T23	3		T26	3
all_pins[8]	transitions[0x1=>0x0]	195351	1			T21	2		T24	2		T26	1
all_pins[9]	values[0x0]	6408389	1			T21	6		T22	1		T23	5
all_pins[9]	values[0x1]	1039383	1			T21	2		T24	2		T26	1
all_pins[9]	transitions[0x0=>0x1]	958485	1			T21	2		T24	2		T27	3
all_pins[9]	transitions[0x1=>0x0]	73053	1			T21	2		T26	1		T27	1
all_pins[10]	values[0x0]	7293821	1			T21	6		T22	1		T23	5
all_pins[10]	values[0x1]	153951	1			T21	2		T26	2		T27	1
all_pins[10]	transitions[0x0=>0x1]	4464	1			T21	2		T26	1		T27	1
all_pins[10]	transitions[0x1=>0x0]	332230	1			T21	1		T23	2		T26	1
all_pins[11]	values[0x0]	6966055	1			T21	7		T22	1		T23	3
all_pins[11]	values[0x1]	481717	1			T21	1		T23	2		T26	2
all_pins[11]	transitions[0x0=>0x1]	481687	1			T23	2		T26	1		T27	2
all_pins[11]	transitions[0x1=>0x0]	90	1			T21	2		T24	1		T26	2
all_pins[12]	values[0x0]	7447652	1			T21	5		T22	1		T23	5
all_pins[12]	values[0x1]	120	1			T21	3		T24	1		T26	3
all_pins[12]	transitions[0x0=>0x1]	94	1			T21	3		T24	1		T26	2
all_pins[12]	transitions[0x1=>0x0]	121	1			T26	2		T27	1		T28	4
all_pins[13]	values[0x0]	7447625	1			T21	8		T22	1		T23	5
all_pins[13]	values[0x1]	147	1			T26	3		T27	2		T28	4
all_pins[13]	transitions[0x0=>0x1]	105	1			T26	2		T27	2		T28	4
all_pins[13]	transitions[0x1=>0x0]	90	1			T21	1		T23	1		T24	1
all_pins[14]	values[0x0]	7447640	1			T21	7		T22	1		T23	4
all_pins[14]	values[0x1]	132	1			T21	1		T23	1		T24	1
all_pins[14]	transitions[0x0=>0x1]	92	1			T23	1		T24	1		T26	2
all_pins[14]	transitions[0x1=>0x0]	830986	1			T26	3		T27	2		T95	1