Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 0 21 100.00
Crosses 90 0 90 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 15 0 15 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 90 0 90 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 553 1 T21 7 T23 4 T24 4
all_values[1] 553 1 T21 7 T23 4 T24 4
all_values[2] 553 1 T21 7 T23 4 T24 4
all_values[3] 553 1 T21 7 T23 4 T24 4
all_values[4] 553 1 T21 7 T23 4 T24 4
all_values[5] 553 1 T21 7 T23 4 T24 4
all_values[6] 553 1 T21 7 T23 4 T24 4
all_values[7] 553 1 T21 7 T23 4 T24 4
all_values[8] 553 1 T21 7 T23 4 T24 4
all_values[9] 553 1 T21 7 T23 4 T24 4
all_values[10] 553 1 T21 7 T23 4 T24 4
all_values[11] 553 1 T21 7 T23 4 T24 4
all_values[12] 553 1 T21 7 T23 4 T24 4
all_values[13] 553 1 T21 7 T23 4 T24 4
all_values[14] 553 1 T21 7 T23 4 T24 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4205 1 T21 69 T23 39 T24 36
auto[1] 4090 1 T21 36 T23 21 T24 24



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1124 1 T21 12 T23 20 T24 20
auto[1] 7171 1 T21 93 T23 40 T24 40



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4879 1 T21 58 T23 41 T24 42
auto[1] 3416 1 T21 47 T23 19 T24 18



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 90 0 90 100.00
Automatically Generated Cross Bins 90 0 90 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 42 1 T21 1 T23 1 T24 2
all_values[0] auto[0] auto[0] auto[1] 116 1 T21 3 T23 2 T27 1
all_values[0] auto[0] auto[1] auto[0] 27 1 T24 2 T27 1 T149 2
all_values[0] auto[0] auto[1] auto[1] 138 1 T21 1 T26 3 T27 3
all_values[0] auto[1] auto[0] auto[1] 121 1 T21 2 T23 1 T26 1
all_values[0] auto[1] auto[1] auto[1] 109 1 T26 2 T27 1 T95 1
all_values[1] auto[0] auto[0] auto[0] 48 1 T21 1 T26 2 T95 1
all_values[1] auto[0] auto[0] auto[1] 129 1 T21 1 T23 1 T26 1
all_values[1] auto[0] auto[1] auto[0] 26 1 T144 1 T150 2 T131 3
all_values[1] auto[0] auto[1] auto[1] 143 1 T21 1 T23 1 T24 2
all_values[1] auto[1] auto[0] auto[1] 124 1 T21 1 T23 1 T26 1
all_values[1] auto[1] auto[1] auto[1] 83 1 T21 3 T23 1 T24 2
all_values[2] auto[0] auto[0] auto[0] 39 1 T23 1 T28 2 T79 2
all_values[2] auto[0] auto[0] auto[1] 114 1 T21 1 T24 1 T26 2
all_values[2] auto[0] auto[1] auto[0] 30 1 T27 1 T112 2 T130 1
all_values[2] auto[0] auto[1] auto[1] 138 1 T21 3 T23 1 T24 1
all_values[2] auto[1] auto[0] auto[1] 123 1 T21 1 T24 1 T26 2
all_values[2] auto[1] auto[1] auto[1] 109 1 T21 2 T23 2 T24 1
all_values[3] auto[0] auto[0] auto[0] 40 1 T23 1 T24 1 T95 1
all_values[3] auto[0] auto[0] auto[1] 107 1 T21 2 T23 1 T24 2
all_values[3] auto[0] auto[1] auto[0] 49 1 T23 1 T27 1 T95 1
all_values[3] auto[0] auto[1] auto[1] 138 1 T21 3 T26 3 T27 2
all_values[3] auto[1] auto[0] auto[1] 113 1 T21 2 T23 1 T24 1
all_values[3] auto[1] auto[1] auto[1] 106 1 T26 1 T27 1 T28 3
all_values[4] auto[0] auto[0] auto[0] 37 1 T21 1 T26 1 T110 2
all_values[4] auto[0] auto[0] auto[1] 117 1 T21 3 T23 3 T24 2
all_values[4] auto[0] auto[1] auto[0] 40 1 T112 4 T130 1 T131 2
all_values[4] auto[0] auto[1] auto[1] 127 1 T26 1 T27 1 T28 2
all_values[4] auto[1] auto[0] auto[1] 125 1 T21 3 T23 1 T26 3
all_values[4] auto[1] auto[1] auto[1] 107 1 T24 2 T27 4 T28 3
all_values[5] auto[0] auto[0] auto[0] 43 1 T23 1 T26 1 T79 1
all_values[5] auto[0] auto[0] auto[1] 122 1 T21 4 T24 2 T26 1
all_values[5] auto[0] auto[1] auto[0] 32 1 T24 1 T26 4 T79 1
all_values[5] auto[0] auto[1] auto[1] 129 1 T23 1 T27 3 T28 3
all_values[5] auto[1] auto[0] auto[1] 124 1 T21 3 T23 1 T26 1
all_values[5] auto[1] auto[1] auto[1] 103 1 T23 1 T24 1 T27 1
all_values[6] auto[0] auto[0] auto[0] 25 1 T21 2 T23 1 T27 1
all_values[6] auto[0] auto[0] auto[1] 108 1 T26 2 T28 2 T95 1
all_values[6] auto[0] auto[1] auto[0] 27 1 T23 1 T27 3 T140 1
all_values[6] auto[0] auto[1] auto[1] 143 1 T21 2 T23 1 T24 2
all_values[6] auto[1] auto[0] auto[1] 119 1 T26 1 T27 1 T28 1
all_values[6] auto[1] auto[1] auto[1] 131 1 T21 3 T23 1 T24 2
all_values[7] auto[0] auto[0] auto[0] 55 1 T21 3 T23 2 T24 1
all_values[7] auto[0] auto[0] auto[1] 127 1 T26 5 T27 1 T28 4
all_values[7] auto[0] auto[1] auto[0] 41 1 T23 2 T27 2 T79 1
all_values[7] auto[0] auto[1] auto[1] 115 1 T21 1 T24 2 T26 1
all_values[7] auto[1] auto[0] auto[1] 110 1 T21 1 T24 1 T27 1
all_values[7] auto[1] auto[1] auto[1] 105 1 T21 2 T26 1 T27 2
all_values[8] auto[0] auto[0] auto[0] 45 1 T21 1 T27 2 T139 1
all_values[8] auto[0] auto[0] auto[1] 116 1 T21 2 T24 2 T26 2
all_values[8] auto[0] auto[1] auto[0] 37 1 T149 1 T130 1 T131 1
all_values[8] auto[0] auto[1] auto[1] 123 1 T21 1 T23 2 T26 1
all_values[8] auto[1] auto[0] auto[1] 119 1 T21 1 T23 1 T24 2
all_values[8] auto[1] auto[1] auto[1] 113 1 T21 2 T23 1 T26 4
all_values[9] auto[0] auto[0] auto[0] 50 1 T21 1 T23 3 T24 2
all_values[9] auto[0] auto[0] auto[1] 113 1 T21 2 T26 4 T27 2
all_values[9] auto[0] auto[1] auto[0] 35 1 T23 1 T139 1 T130 1
all_values[9] auto[0] auto[1] auto[1] 135 1 T21 1 T24 1 T27 1
all_values[9] auto[1] auto[0] auto[1] 116 1 T21 2 T26 1 T27 2
all_values[9] auto[1] auto[1] auto[1] 104 1 T21 1 T24 1 T26 2
all_values[10] auto[0] auto[0] auto[0] 28 1 T21 1 T24 2 T26 1
all_values[10] auto[0] auto[0] auto[1] 119 1 T21 1 T23 3 T26 2
all_values[10] auto[0] auto[1] auto[0] 23 1 T24 2 T110 3 T149 1
all_values[10] auto[0] auto[1] auto[1] 139 1 T21 1 T26 1 T27 4
all_values[10] auto[1] auto[0] auto[1] 126 1 T21 2 T23 1 T26 2
all_values[10] auto[1] auto[1] auto[1] 118 1 T21 2 T26 1 T27 1
all_values[11] auto[0] auto[0] auto[0] 50 1 T24 2 T110 1 T112 1
all_values[11] auto[0] auto[0] auto[1] 122 1 T21 3 T23 2 T26 3
all_values[11] auto[0] auto[1] auto[0] 41 1 T24 2 T26 1 T27 1
all_values[11] auto[0] auto[1] auto[1] 128 1 T27 2 T28 2 T79 2
all_values[11] auto[1] auto[0] auto[1] 115 1 T21 2 T23 1 T27 1
all_values[11] auto[1] auto[1] auto[1] 97 1 T21 2 T23 1 T26 3
all_values[12] auto[0] auto[0] auto[0] 44 1 T23 2 T24 1 T95 2
all_values[12] auto[0] auto[0] auto[1] 118 1 T21 1 T24 2 T26 1
all_values[12] auto[0] auto[1] auto[0] 24 1 T23 2 T95 2 T79 2
all_values[12] auto[0] auto[1] auto[1] 134 1 T21 2 T26 1 T27 1
all_values[12] auto[1] auto[0] auto[1] 120 1 T21 2 T24 1 T26 3
all_values[12] auto[1] auto[1] auto[1] 113 1 T21 2 T26 2 T27 2
all_values[13] auto[0] auto[0] auto[0] 43 1 T21 1 T23 1 T24 1
all_values[13] auto[0] auto[0] auto[1] 126 1 T21 3 T23 1 T24 2
all_values[13] auto[0] auto[1] auto[0] 40 1 T79 1 T110 4 T150 1
all_values[13] auto[0] auto[1] auto[1] 122 1 T26 3 T27 1 T28 2
all_values[13] auto[1] auto[0] auto[1] 118 1 T21 3 T23 1 T24 1
all_values[13] auto[1] auto[1] auto[1] 104 1 T23 1 T26 2 T27 2
all_values[14] auto[0] auto[0] auto[0] 42 1 T24 1 T28 1 T110 2
all_values[14] auto[0] auto[0] auto[1] 127 1 T21 3 T23 2 T24 1
all_values[14] auto[0] auto[1] auto[0] 21 1 T26 1 T144 2 T140 1
all_values[14] auto[0] auto[1] auto[1] 122 1 T21 1 T26 1 T27 3
all_values[14] auto[1] auto[0] auto[1] 120 1 T21 3 T23 2 T24 2
all_values[14] auto[1] auto[1] auto[1] 121 1 T26 1 T27 1 T95 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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