Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7755806	1			T22	8		T25	8		T68	1
all_values[1]	7755806	1			T22	8		T25	8		T68	1
all_values[2]	7755806	1			T22	8		T25	8		T68	1
all_values[3]	7755806	1			T22	8		T25	8		T68	1
all_values[4]	7755806	1			T22	8		T25	8		T68	1
all_values[5]	7755806	1			T22	8		T25	8		T68	1
all_values[6]	7755806	1			T22	8		T25	8		T68	1
all_values[7]	7755806	1			T22	8		T25	8		T68	1
all_values[8]	7755806	1			T22	8		T25	8		T68	1
all_values[9]	7755806	1			T22	8		T25	8		T68	1
all_values[10]	7755806	1			T22	8		T25	8		T68	1
all_values[11]	7755806	1			T22	8		T25	8		T68	1
all_values[12]	7755806	1			T22	8		T25	8		T68	1
all_values[13]	7755806	1			T22	8		T25	8		T68	1
all_values[14]	7755806	1			T22	8		T25	8		T68	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110063293

1

T22

69

T25

88

T68

15

auto[1]

6273797

1

T22

51

T25

32

T61

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105083533

1

T22

11

T25

5

T68

15

auto[1]

11253557

1

T22

109

T25

115

T61

112

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6170156	1			T22	1		T68	1		T73	1
all_values[0]	auto[0]	auto[1]	595549	1			T22	2		T25	5		T61	4
all_values[0]	auto[1]	auto[0]	844823	1			T2	9		T3	1		T10	26
all_values[0]	auto[1]	auto[1]	145278	1			T22	5		T25	3		T61	4
all_values[1]	auto[0]	auto[0]	6427567	1			T68	1		T61	2		T73	1
all_values[1]	auto[0]	auto[1]	656609	1			T22	3		T25	8		T61	4
all_values[1]	auto[1]	auto[0]	575426	1			T2	79		T10	71		T32	41
all_values[1]	auto[1]	auto[1]	96204	1			T22	5		T61	2		T90	4
all_values[2]	auto[0]	auto[0]	7003003	1			T22	2		T68	1		T73	1
all_values[2]	auto[0]	auto[1]	752570	1			T22	3		T25	3		T61	5
all_values[2]	auto[1]	auto[1]	233	1			T22	3		T25	5		T61	3
all_values[3]	auto[0]	auto[0]	6998407	1			T68	1		T73	1		T74	1
all_values[3]	auto[0]	auto[1]	757201	1			T22	7		T25	6		T61	3
all_values[3]	auto[1]	auto[1]	198	1			T22	1		T25	2		T61	5
all_values[4]	auto[0]	auto[0]	7031968	1			T25	1		T68	1		T73	1
all_values[4]	auto[0]	auto[1]	723597	1			T22	2		T25	5		T61	4
all_values[4]	auto[1]	auto[0]	26	1			T42	1		T43	25		-	-
all_values[4]	auto[1]	auto[1]	215	1			T22	6		T25	2		T61	4
all_values[5]	auto[0]	auto[0]	6988902	1			T22	3		T25	1		T68	1
all_values[5]	auto[0]	auto[1]	766701	1			T22	4		T25	3		T61	6
all_values[5]	auto[1]	auto[1]	203	1			T22	1		T25	4		T61	2
all_values[6]	auto[0]	auto[0]	6093690	1			T68	1		T61	2		T73	1
all_values[6]	auto[0]	auto[1]	615354	1			T22	6		T25	7		T61	5
all_values[6]	auto[1]	auto[0]	895235	1			T2	41		T9	1		T10	282
all_values[6]	auto[1]	auto[1]	151527	1			T22	2		T25	1		T61	1
all_values[7]	auto[0]	auto[0]	6681680	1			T68	1		T73	1		T74	1
all_values[7]	auto[0]	auto[1]	743273	1			T22	5		T25	7		T61	4
all_values[7]	auto[1]	auto[0]	310610	1			T2	699		T9	1		T10	855
all_values[7]	auto[1]	auto[1]	20243	1			T22	3		T25	1		T61	4
all_values[8]	auto[0]	auto[0]	6018048	1			T22	2		T68	1		T73	1
all_values[8]	auto[0]	auto[1]	513273	1			T22	3		T25	6		T61	5
all_values[8]	auto[1]	auto[0]	1077129	1			T2	363		T3	1		T9	1
all_values[8]	auto[1]	auto[1]	147356	1			T22	3		T25	2		T61	3
all_values[9]	auto[0]	auto[0]	5894517	1			T22	1		T68	1		T61	2
all_values[9]	auto[0]	auto[1]	616708	1			T22	3		T25	8		T61	3
all_values[9]	auto[1]	auto[0]	1094375	1			T1	1337		T2	30		T3	1
all_values[9]	auto[1]	auto[1]	150206	1			T22	4		T61	3		T90	2
all_values[10]	auto[0]	auto[0]	6826156	1			T22	1		T68	1		T73	1
all_values[10]	auto[0]	auto[1]	747088	1			T22	5		T25	5		T61	5
all_values[10]	auto[1]	auto[0]	182363	1			T1	1556		T14	1286		T15	4
all_values[10]	auto[1]	auto[1]	199	1			T22	2		T25	3		T61	3
all_values[11]	auto[0]	auto[0]	6421617	1			T25	3		T68	1		T61	1
all_values[11]	auto[0]	auto[1]	752860	1			T22	4		T25	5		T61	2
all_values[11]	auto[1]	auto[0]	581129	1			T1	40824		T14	5314		T15	8445
all_values[11]	auto[1]	auto[1]	200	1			T22	4		T61	5		T90	1
all_values[12]	auto[0]	auto[0]	6988885	1			T68	1		T61	1		T73	1
all_values[12]	auto[0]	auto[1]	766717	1			T22	4		T25	6		T61	4
all_values[12]	auto[1]	auto[1]	204	1			T22	4		T25	2		T61	3
all_values[13]	auto[0]	auto[0]	6988900	1			T22	1		T68	1		T73	1
all_values[13]	auto[0]	auto[1]	766703	1			T22	3		T25	4		T61	6
all_values[13]	auto[1]	auto[0]	10	1			T38	1		T151	1		T147	1
all_values[13]	auto[1]	auto[1]	193	1			T22	4		T25	4		T61	2
all_values[14]	auto[0]	auto[0]	6988911	1			T68	1		T73	1		T74	1
all_values[14]	auto[0]	auto[1]	766683	1			T22	4		T25	5		T61	6
all_values[14]	auto[1]	auto[1]	212	1			T22	4		T25	3		T61	2