Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 0 60 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 15 0 15 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 60 0 60 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 7755806 1 T22 8 T25 8 T68 1
all_pins[1] 7755806 1 T22 8 T25 8 T68 1
all_pins[2] 7755806 1 T22 8 T25 8 T68 1
all_pins[3] 7755806 1 T22 8 T25 8 T68 1
all_pins[4] 7755806 1 T22 8 T25 8 T68 1
all_pins[5] 7755806 1 T22 8 T25 8 T68 1
all_pins[6] 7755806 1 T22 8 T25 8 T68 1
all_pins[7] 7755806 1 T22 8 T25 8 T68 1
all_pins[8] 7755806 1 T22 8 T25 8 T68 1
all_pins[9] 7755806 1 T22 8 T25 8 T68 1
all_pins[10] 7755806 1 T22 8 T25 8 T68 1
all_pins[11] 7755806 1 T22 8 T25 8 T68 1
all_pins[12] 7755806 1 T22 8 T25 8 T68 1
all_pins[13] 7755806 1 T22 8 T25 8 T68 1
all_pins[14] 7755806 1 T22 8 T25 8 T68 1


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 109993025 1 T22 91 T25 109 T68 15
values[0x1] 6344065 1 T22 29 T25 11 T61 23
transitions[0x0=>0x1] 4310859 1 T22 20 T25 11 T61 18
transitions[0x1=>0x0] 4310865 1 T22 20 T25 11 T61 18


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 0 60 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 6765485 1 T22 3 T25 7 T68 1
all_pins[0] values[0x1] 990321 1 T22 5 T25 1 T61 2
all_pins[0] transitions[0x0=>0x1] 339723 1 T22 3 T25 1 T61 2
all_pins[0] transitions[0x1=>0x0] 23646 1 T22 1 T61 2 T90 4
all_pins[1] values[0x0] 7081562 1 T22 5 T25 8 T68 1
all_pins[1] values[0x1] 674244 1 T22 3 T61 2 T90 4
all_pins[1] transitions[0x0=>0x1] 674212 1 T22 3 T90 4 T91 1
all_pins[1] transitions[0x1=>0x0] 93 1 T22 2 T25 1 T61 1
all_pins[2] values[0x0] 7755681 1 T22 6 T25 7 T68 1
all_pins[2] values[0x1] 125 1 T22 2 T25 1 T61 3
all_pins[2] transitions[0x0=>0x1] 98 1 T22 2 T25 1 T61 2
all_pins[2] transitions[0x1=>0x0] 70 1 T61 1 T89 1 T28 1
all_pins[3] values[0x0] 7755709 1 T22 8 T25 8 T68 1
all_pins[3] values[0x1] 97 1 T61 2 T89 1 T11 1
all_pins[3] transitions[0x0=>0x1] 72 1 T61 1 T89 1 T11 1
all_pins[3] transitions[0x1=>0x0] 117 1 T22 5 T25 1 T61 1
all_pins[4] values[0x0] 7755664 1 T22 3 T25 7 T68 1
all_pins[4] values[0x1] 142 1 T22 5 T25 1 T61 2
all_pins[4] transitions[0x0=>0x1] 114 1 T22 4 T25 1 T61 1
all_pins[4] transitions[0x1=>0x0] 76 1 T25 2 T91 1 T112 3
all_pins[5] values[0x0] 7755702 1 T22 7 T25 6 T68 1
all_pins[5] values[0x1] 104 1 T22 1 T25 2 T61 1
all_pins[5] transitions[0x0=>0x1] 81 1 T22 1 T25 2 T61 1
all_pins[5] transitions[0x1=>0x0] 1050320 1 T25 1 T61 1 T90 1
all_pins[6] values[0x0] 6705463 1 T22 8 T25 7 T68 1
all_pins[6] values[0x1] 1050343 1 T25 1 T61 1 T90 1
all_pins[6] transitions[0x0=>0x1] 1025154 1 T25 1 T61 1 T90 1
all_pins[6] transitions[0x1=>0x0] 344129 1 T22 2 T25 1 T61 2
all_pins[7] values[0x0] 7386488 1 T22 6 T25 7 T68 1
all_pins[7] values[0x1] 369318 1 T22 2 T25 1 T61 2
all_pins[7] transitions[0x0=>0x1] 299398 1 T22 2 T25 1 T61 2
all_pins[7] transitions[0x1=>0x0] 1179628 1 T22 1 T90 1 T89 3
all_pins[8] values[0x0] 6506258 1 T22 7 T25 8 T68 1
all_pins[8] values[0x1] 1249548 1 T22 1 T90 1 T89 3
all_pins[8] transitions[0x0=>0x1] 235869 1 T22 1 T90 1 T89 3
all_pins[8] transitions[0x1=>0x0] 231826 1 T22 2 T61 1 T113 2
all_pins[9] values[0x0] 6510301 1 T22 6 T25 8 T68 1
all_pins[9] values[0x1] 1245505 1 T22 2 T61 1 T113 2
all_pins[9] transitions[0x0=>0x1] 1150346 1 T22 2 T61 1 T113 2
all_pins[9] transitions[0x1=>0x0] 87641 1 T22 1 T25 1 T61 1
all_pins[10] values[0x0] 7573006 1 T22 7 T25 7 T68 1
all_pins[10] values[0x1] 182800 1 T22 1 T25 1 T61 1
all_pins[10] transitions[0x0=>0x1] 4345 1 T25 1 T61 1 T91 1
all_pins[10] transitions[0x1=>0x0] 402768 1 T61 3 T89 1 T1 39279
all_pins[11] values[0x0] 7174583 1 T22 7 T25 8 T68 1
all_pins[11] values[0x1] 581223 1 T22 1 T61 3 T89 2
all_pins[11] transitions[0x0=>0x1] 581207 1 T22 1 T61 3 T89 1
all_pins[11] transitions[0x1=>0x0] 90 1 T22 2 T25 1 T61 1
all_pins[12] values[0x0] 7755700 1 T22 6 T25 7 T68 1
all_pins[12] values[0x1] 106 1 T22 2 T25 1 T61 1
all_pins[12] transitions[0x0=>0x1] 92 1 T22 1 T25 1 T61 1
all_pins[12] transitions[0x1=>0x0] 75 1 T22 1 T25 2 T61 1
all_pins[13] values[0x0] 7755717 1 T22 6 T25 6 T68 1
all_pins[13] values[0x1] 89 1 T22 2 T25 2 T61 1
all_pins[13] transitions[0x0=>0x1] 72 1 T25 2 T61 1 T89 1
all_pins[13] transitions[0x1=>0x0] 83 1 T61 1 T91 2 T11 6
all_pins[14] values[0x0] 7755706 1 T22 6 T25 8 T68 1
all_pins[14] values[0x1] 100 1 T22 2 T61 1 T91 2
all_pins[14] transitions[0x0=>0x1] 76 1 T61 1 T91 1 T11 5
all_pins[14] transitions[0x1=>0x0] 990303 1 T22 3 T25 1 T61 2

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