Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	480	1			T22	7		T25	7		T61	7
all_values[1]	480	1			T22	7		T25	7		T61	7
all_values[2]	480	1			T22	7		T25	7		T61	7
all_values[3]	480	1			T22	7		T25	7		T61	7
all_values[4]	480	1			T22	7		T25	7		T61	7
all_values[5]	480	1			T22	7		T25	7		T61	7
all_values[6]	480	1			T22	7		T25	7		T61	7
all_values[7]	480	1			T22	7		T25	7		T61	7
all_values[8]	480	1			T22	7		T25	7		T61	7
all_values[9]	480	1			T22	7		T25	7		T61	7
all_values[10]	480	1			T22	7		T25	7		T61	7
all_values[11]	480	1			T22	7		T25	7		T61	7
all_values[12]	480	1			T22	7		T25	7		T61	7
all_values[13]	480	1			T22	7		T25	7		T61	7
all_values[14]	480	1			T22	7		T25	7		T61	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3848

1

T22

61

T25

62

T61

52

auto[1]

3352

1

T22

44

T25

43

T61

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

987

1

T22

11

T25

5

T61

8

auto[1]

6213

1

T22

94

T25

100

T61

97

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4220

1

T22

56

T25

60

T61

58

auto[1]

2980

1

T22

49

T25

45

T61

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	49	1			T22	1		T91	1		T112	2
all_values[0]	auto[0]	auto[0]	auto[1]	106	1			T25	1		T61	2		T90	1
all_values[0]	auto[0]	auto[1]	auto[0]	20	1			T90	1		T112	2		T164	1
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T22	4		T25	3		T61	1
all_values[0]	auto[1]	auto[0]	auto[1]	122	1			T25	1		T61	2		T90	2
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T22	2		T25	2		T61	2
all_values[1]	auto[0]	auto[0]	auto[0]	26	1			T61	2		T89	1		T12	2
all_values[1]	auto[0]	auto[0]	auto[1]	123	1			T22	1		T25	2		T61	2
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T11	2		T12	2		T127	3
all_values[1]	auto[0]	auto[1]	auto[1]	105	1			T22	2		T25	3		T61	1
all_values[1]	auto[1]	auto[0]	auto[1]	125	1			T22	3		T91	3		T112	2
all_values[1]	auto[1]	auto[1]	auto[1]	80	1			T22	1		T25	2		T61	2
all_values[2]	auto[0]	auto[0]	auto[0]	41	1			T22	2		T90	1		T112	1
all_values[2]	auto[0]	auto[0]	auto[1]	101	1			T25	1		T61	3		T90	1
all_values[2]	auto[0]	auto[1]	auto[0]	25	1			T89	1		T12	2		T126	1
all_values[2]	auto[0]	auto[1]	auto[1]	111	1			T22	1		T25	3		T61	1
all_values[2]	auto[1]	auto[0]	auto[1]	105	1			T22	2		T25	3		T61	2
all_values[2]	auto[1]	auto[1]	auto[1]	97	1			T22	2		T61	1		T91	2
all_values[3]	auto[0]	auto[0]	auto[0]	48	1			T91	3		T113	3		T12	1
all_values[3]	auto[0]	auto[0]	auto[1]	116	1			T22	4		T25	4		T61	2
all_values[3]	auto[0]	auto[1]	auto[0]	47	1			T90	2		T91	4		T113	1
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T22	1		T112	2		T89	2
all_values[3]	auto[1]	auto[0]	auto[1]	99	1			T22	2		T25	3		T61	3
all_values[3]	auto[1]	auto[1]	auto[1]	85	1			T61	2		T11	2		T28	1
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T25	1		T91	1		T89	2
all_values[4]	auto[0]	auto[0]	auto[1]	108	1			T22	1		T25	1		T61	1
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T113	1		T12	4		T28	2
all_values[4]	auto[0]	auto[1]	auto[1]	98	1			T22	2		T25	2		T90	2
all_values[4]	auto[1]	auto[0]	auto[1]	101	1			T22	2		T25	1		T61	2
all_values[4]	auto[1]	auto[1]	auto[1]	102	1			T22	2		T25	2		T61	4
all_values[5]	auto[0]	auto[0]	auto[0]	43	1			T22	1		T25	1		T89	1
all_values[5]	auto[0]	auto[0]	auto[1]	107	1			T22	1		T25	1		T91	4
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T22	2		T90	4		T28	2
all_values[5]	auto[0]	auto[1]	auto[1]	109	1			T22	1		T25	2		T61	5
all_values[5]	auto[1]	auto[0]	auto[1]	112	1			T22	1		T25	1		T61	1
all_values[5]	auto[1]	auto[1]	auto[1]	88	1			T22	1		T25	2		T61	1
all_values[6]	auto[0]	auto[0]	auto[0]	38	1			T61	1		T90	1		T112	1
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T22	2		T90	1		T91	1
all_values[6]	auto[0]	auto[1]	auto[0]	42	1			T61	1		T112	3		T165	3
all_values[6]	auto[0]	auto[1]	auto[1]	113	1			T22	1		T25	2		T61	3
all_values[6]	auto[1]	auto[0]	auto[1]	107	1			T22	3		T25	2		T90	1
all_values[6]	auto[1]	auto[1]	auto[1]	93	1			T22	1		T25	3		T61	2
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T90	1		T89	1		T126	1
all_values[7]	auto[0]	auto[0]	auto[1]	120	1			T22	2		T25	2		T90	1
all_values[7]	auto[0]	auto[1]	auto[0]	29	1			T113	2		T11	4		T166	2
all_values[7]	auto[0]	auto[1]	auto[1]	101	1			T22	1		T25	3		T61	3
all_values[7]	auto[1]	auto[0]	auto[1]	99	1			T22	2		T25	1		T61	3
all_values[7]	auto[1]	auto[1]	auto[1]	90	1			T22	2		T25	1		T61	1
all_values[8]	auto[0]	auto[0]	auto[0]	38	1			T22	2		T91	1		T89	2
all_values[8]	auto[0]	auto[0]	auto[1]	101	1			T22	2		T25	1		T61	2
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T90	1		T28	5		T167	5
all_values[8]	auto[0]	auto[1]	auto[1]	115	1			T22	1		T25	1		T61	1
all_values[8]	auto[1]	auto[0]	auto[1]	102	1			T22	1		T25	5		T61	3
all_values[8]	auto[1]	auto[1]	auto[1]	96	1			T22	1		T61	1		T90	1
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T22	1		T61	2		T89	1
all_values[9]	auto[0]	auto[0]	auto[1]	105	1			T22	1		T25	2		T61	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T89	1		T11	1		T126	1
all_values[9]	auto[0]	auto[1]	auto[1]	105	1			T22	1		T25	2		T61	1
all_values[9]	auto[1]	auto[0]	auto[1]	122	1			T22	2		T25	1		T61	1
all_values[9]	auto[1]	auto[1]	auto[1]	93	1			T22	2		T25	2		T61	2
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T22	1		T90	3		T89	2
all_values[10]	auto[0]	auto[0]	auto[1]	119	1			T22	2		T25	3		T61	2
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T90	1		T91	1		T28	2
all_values[10]	auto[0]	auto[1]	auto[1]	106	1			T22	2		T25	1		T61	2
all_values[10]	auto[1]	auto[0]	auto[1]	113	1			T22	1		T25	1		T61	2
all_values[10]	auto[1]	auto[1]	auto[1]	86	1			T22	1		T25	2		T61	1
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T25	1		T61	1		T90	1
all_values[11]	auto[0]	auto[0]	auto[1]	119	1			T22	4		T25	2		T61	1
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T25	2		T113	2		T11	1
all_values[11]	auto[0]	auto[1]	auto[1]	103	1			T61	3		T91	1		T112	1
all_values[11]	auto[1]	auto[0]	auto[1]	110	1			T22	2		T25	2		T90	1
all_values[11]	auto[1]	auto[1]	auto[1]	82	1			T22	1		T61	2		T91	2
all_values[12]	auto[0]	auto[0]	auto[0]	34	1			T61	1		T11	1		T126	2
all_values[12]	auto[0]	auto[0]	auto[1]	104	1			T22	1		T25	5		T89	2
all_values[12]	auto[0]	auto[1]	auto[0]	14	1			T91	1		T11	1		T166	1
all_values[12]	auto[0]	auto[1]	auto[1]	124	1			T22	2		T61	3		T90	2
all_values[12]	auto[1]	auto[0]	auto[1]	110	1			T22	3		T25	1		T61	2
all_values[12]	auto[1]	auto[1]	auto[1]	94	1			T22	1		T25	1		T61	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T22	1		T91	1		T113	2
all_values[13]	auto[0]	auto[0]	auto[1]	106	1			T22	2		T25	3		T61	2
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T91	6		T113	2		T11	1
all_values[13]	auto[0]	auto[1]	auto[1]	120	1			T25	1		T61	3		T90	2
all_values[13]	auto[1]	auto[0]	auto[1]	110	1			T22	2		T25	2		T61	2
all_values[13]	auto[1]	auto[1]	auto[1]	76	1			T22	2		T25	1		T89	1
all_values[14]	auto[0]	auto[0]	auto[0]	35	1			T112	3		T89	3		T28	1
all_values[14]	auto[0]	auto[0]	auto[1]	107	1			T22	2		T25	4		T61	2
all_values[14]	auto[0]	auto[1]	auto[0]	31	1			T90	1		T112	1		T12	1
all_values[14]	auto[0]	auto[1]	auto[1]	115	1			T22	1		T61	3		T91	2
all_values[14]	auto[1]	auto[0]	auto[1]	107	1			T22	1		T25	3		T61	2
all_values[14]	auto[1]	auto[1]	auto[1]	85	1			T22	3		T91	3		T113	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal