Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20872	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31109

1

T1

11

T2

1148

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26690	1			T1	11		T2	959		T3	11
values[0x0]	12421	1			T1	5		T2	470		T3	5
values[0x1]	12870	1			T1	6		T2	488		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36897

1

T1

13

T2

1266

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	168	1			T2	10		T5	4		T8	3
valid_sources[0x01]	196	1			T2	6		T4	8		T8	2
valid_sources[0x02]	206	1			T2	6		T5	1		T6	4
valid_sources[0x03]	147	1			T2	6		T4	4		T8	1
valid_sources[0x04]	432	1			T2	6		T5	2		T8	2
valid_sources[0x05]	213	1			T2	2		T5	4		T8	1
valid_sources[0x06]	257	1			T2	1		T6	2		T25	2
valid_sources[0x07]	189	1			T2	9		T5	1		T6	1
valid_sources[0x08]	235	1			T2	5		T5	3		T8	1
valid_sources[0x09]	169	1			T1	1		T4	1		T5	2
valid_sources[0x0a]	177	1			T5	3		T6	4		T14	1
valid_sources[0x0b]	164	1			T2	11		T4	4		T5	4
valid_sources[0x0c]	155	1			T2	7		T5	3		T25	3
valid_sources[0x0d]	162	1			T2	3		T5	2		T6	2
valid_sources[0x0e]	190	1			T2	2		T4	5		T5	4
valid_sources[0x0f]	157	1			T2	5		T4	4		T8	3
valid_sources[0x10]	140	1			T2	12		T8	4		T25	1
valid_sources[0x11]	207	1			T2	4		T4	3		T5	2
valid_sources[0x12]	262	1			T1	2		T2	6		T4	5
valid_sources[0x13]	141	1			T2	3		T4	1		T6	2
valid_sources[0x14]	174	1			T2	5		T5	2		T8	1
valid_sources[0x15]	307	1			T2	17		T4	3		T5	2
valid_sources[0x16]	189	1			T2	11		T4	2		T8	1
valid_sources[0x17]	174	1			T1	1		T2	7		T5	2
valid_sources[0x18]	296	1			T2	23		T5	1		T13	19
valid_sources[0x19]	242	1			T2	20		T6	6		T9	30
valid_sources[0x1a]	202	1			T1	2		T2	5		T5	2
valid_sources[0x1b]	109	1			T2	2		T5	1		T8	1
valid_sources[0x1c]	145	1			T2	16		T5	3		T25	1
valid_sources[0x1d]	167	1			T2	11		T4	7		T8	1
valid_sources[0x1e]	184	1			T2	4		T8	3		T25	2
valid_sources[0x1f]	145	1			T2	4		T4	9		T5	2
valid_sources[0x20]	267	1			T2	10		T11	3		T5	3
valid_sources[0x21]	245	1			T2	6		T4	4		T8	3
valid_sources[0x22]	200	1			T2	16		T4	7		T5	4
valid_sources[0x23]	160	1			T2	2		T5	3		T8	2
valid_sources[0x24]	153	1			T2	7		T4	3		T5	1
valid_sources[0x25]	226	1			T2	12		T10	1		T25	1
valid_sources[0x26]	180	1			T1	1		T2	4		T4	3
valid_sources[0x27]	236	1			T2	21		T4	2		T5	1
valid_sources[0x28]	350	1			T2	3		T4	1		T6	6
valid_sources[0x29]	207	1			T1	1		T2	5		T4	11
valid_sources[0x2a]	260	1			T2	6		T4	1		T5	4
valid_sources[0x2b]	184	1			T2	10		T5	2		T9	10
valid_sources[0x2c]	182	1			T2	14		T25	1		T14	1
valid_sources[0x2d]	279	1			T2	3		T4	3		T5	1
valid_sources[0x2e]	206	1			T2	12		T4	3		T5	2
valid_sources[0x2f]	316	1			T2	15		T5	2		T25	2
valid_sources[0x30]	262	1			T2	14		T4	4		T8	1
valid_sources[0x31]	205	1			T2	2		T4	6		T5	2
valid_sources[0x32]	124	1			T2	6		T5	3		T8	2
valid_sources[0x33]	198	1			T2	9		T4	3		T5	1
valid_sources[0x34]	179	1			T2	10		T5	1		T8	2
valid_sources[0x35]	159	1			T2	9		T4	2		T5	2
valid_sources[0x36]	233	1			T2	14		T6	5		T25	1
valid_sources[0x37]	182	1			T2	6		T4	6		T8	3
valid_sources[0x38]	149	1			T2	6		T4	9		T5	3
valid_sources[0x39]	170	1			T2	4		T5	1		T8	1
valid_sources[0x3a]	487	1			T2	11		T4	1		T5	3
valid_sources[0x3b]	147	1			T2	4		T4	5		T21	1
valid_sources[0x3c]	304	1			T2	8		T4	8		T5	2
valid_sources[0x3d]	249	1			T2	6		T8	1		T13	5
valid_sources[0x3e]	184	1			T2	11		T4	3		T25	1
valid_sources[0x3f]	345	1			T2	14		T5	5		T8	3
valid_sources[0x40]	145	1			T2	3		T11	2		T5	4
valid_sources[0x41]	169	1			T2	10		T5	1		T8	1
valid_sources[0x42]	159	1			T2	8		T5	1		T8	2
valid_sources[0x43]	147	1			T2	5		T5	1		T8	1
valid_sources[0x44]	219	1			T2	7		T5	2		T21	1
valid_sources[0x45]	146	1			T2	5		T4	4		T5	2
valid_sources[0x46]	135	1			T2	8		T4	2		T5	2
valid_sources[0x47]	196	1			T2	18		T4	2		T6	4
valid_sources[0x48]	205	1			T2	16		T4	1		T6	7
valid_sources[0x49]	180	1			T2	4		T4	5		T5	4
valid_sources[0x4a]	135	1			T2	10		T5	1		T8	2
valid_sources[0x4b]	180	1			T1	1		T2	7		T5	3
valid_sources[0x4c]	125	1			T2	2		T5	1		T14	2
valid_sources[0x4d]	188	1			T2	5		T5	3		T10	2
valid_sources[0x4e]	205	1			T2	14		T4	1		T5	1
valid_sources[0x4f]	160	1			T2	6		T4	1		T5	3
valid_sources[0x50]	366	1			T2	1		T5	1		T8	1
valid_sources[0x51]	178	1			T2	7		T4	3		T5	1
valid_sources[0x52]	289	1			T2	9		T4	10		T5	4
valid_sources[0x53]	169	1			T2	15		T4	2		T5	2
valid_sources[0x54]	172	1			T2	16		T4	1		T5	2
valid_sources[0x55]	237	1			T2	8		T5	2		T8	3
valid_sources[0x56]	166	1			T1	1		T2	15		T4	1
valid_sources[0x57]	312	1			T2	5		T5	1		T21	1
valid_sources[0x58]	131	1			T2	8		T8	2		T10	1
valid_sources[0x59]	203	1			T2	6		T5	5		T6	1
valid_sources[0x5a]	193	1			T2	10		T4	3		T5	2
valid_sources[0x5b]	354	1			T1	1		T2	6		T4	2
valid_sources[0x5c]	245	1			T2	2		T4	2		T5	4
valid_sources[0x5d]	156	1			T2	8		T4	2		T5	2
valid_sources[0x5e]	290	1			T2	8		T4	2		T5	2
valid_sources[0x5f]	172	1			T2	21		T4	2		T5	2
valid_sources[0x60]	251	1			T2	5		T4	5		T5	3
valid_sources[0x61]	176	1			T2	6		T7	27		T5	1
valid_sources[0x62]	123	1			T2	5		T8	2		T21	1
valid_sources[0x63]	291	1			T2	6		T4	2		T5	2
valid_sources[0x64]	131	1			T2	4		T5	1		T8	2
valid_sources[0x65]	191	1			T2	6		T8	1		T6	6
valid_sources[0x66]	146	1			T2	7		T4	6		T8	1
valid_sources[0x67]	165	1			T2	7		T4	4		T5	1
valid_sources[0x68]	191	1			T2	8		T5	1		T8	1
valid_sources[0x69]	392	1			T1	1		T2	10		T5	3
valid_sources[0x6a]	130	1			T2	4		T5	1		T8	2
valid_sources[0x6b]	208	1			T2	3		T4	9		T5	1
valid_sources[0x6c]	159	1			T2	10		T5	2		T6	1
valid_sources[0x6d]	226	1			T2	8		T5	2		T8	2
valid_sources[0x6e]	125	1			T2	5		T4	3		T5	4
valid_sources[0x6f]	192	1			T2	5		T5	2		T8	1
valid_sources[0x70]	251	1			T2	5		T4	4		T5	2
valid_sources[0x71]	196	1			T2	3		T4	5		T6	3
valid_sources[0x72]	159	1			T2	2		T8	1		T25	1
valid_sources[0x73]	156	1			T2	11		T8	1		T25	1
valid_sources[0x74]	194	1			T2	6		T4	2		T5	4
valid_sources[0x75]	146	1			T2	4		T4	3		T5	2
valid_sources[0x76]	157	1			T2	5		T5	1		T6	5
valid_sources[0x77]	143	1			T2	6		T4	6		T6	1
valid_sources[0x78]	141	1			T2	12		T8	2		T21	3
valid_sources[0x79]	140	1			T2	3		T4	2		T5	2
valid_sources[0x7a]	216	1			T2	8		T4	4		T5	2
valid_sources[0x7b]	202	1			T2	6		T4	1		T5	5
valid_sources[0x7c]	122	1			T1	1		T2	5		T4	3
valid_sources[0x7d]	269	1			T2	4		T4	4		T25	3
valid_sources[0x7e]	152	1			T2	8		T3	22		T4	1
valid_sources[0x7f]	286	1			T2	2		T21	2		T25	2
valid_sources[0x80]	158	1			T2	9		T4	5		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11382

1

T1

6

T2

485

T3

4

values[0x0]

all_enables

biggest_size

10146

1

T1

2

T2

343

T3

1

values[0x1]

all_enables

biggest_size

9581

1

T1

3

T2

320

T7

7