Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	351	1			T13	1		T7	8		T8	5
all_pins[1]	351	1			T13	1		T7	8		T8	5
all_pins[2]	351	1			T13	1		T7	8		T8	5
all_pins[3]	351	1			T13	1		T7	8		T8	5
all_pins[4]	351	1			T13	1		T7	8		T8	5
all_pins[5]	351	1			T13	1		T7	8		T8	5
all_pins[6]	351	1			T13	1		T7	8		T8	5
all_pins[7]	351	1			T13	1		T7	8		T8	5
all_pins[8]	351	1			T13	1		T7	8		T8	5
all_pins[9]	351	1			T13	1		T7	8		T8	5
all_pins[10]	351	1			T13	1		T7	8		T8	5
all_pins[11]	351	1			T13	1		T7	8		T8	5
all_pins[12]	351	1			T13	1		T7	8		T8	5
all_pins[13]	351	1			T13	1		T7	8		T8	5
all_pins[14]	351	1			T13	1		T7	8		T8	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4208	1			T13	15		T7	103		T8	67
values[0x1]	1057	1			T7	17		T8	8		T11	11
transitions[0x0=>0x1]	739	1			T7	13		T8	6		T11	9
transitions[0x1=>0x0]	750	1			T7	13		T8	6		T11	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280	1			T13	1		T7	7		T8	5
all_pins[0]	values[0x1]	71	1			T7	1		T11	3		T9	5
all_pins[0]	transitions[0x0=>0x1]	51	1			T7	1		T11	3		T9	4
all_pins[0]	transitions[0x1=>0x0]	48	1			T9	1		T10	1		T75	3
all_pins[1]	values[0x0]	283	1			T13	1		T7	8		T8	5
all_pins[1]	values[0x1]	68	1			T9	2		T10	1		T76	2
all_pins[1]	transitions[0x0=>0x1]	46	1			T10	1		T76	2		T75	1
all_pins[1]	transitions[0x1=>0x0]	53	1			T8	2		T10	2		T68	1
all_pins[2]	values[0x0]	276	1			T13	1		T7	8		T8	3
all_pins[2]	values[0x1]	75	1			T8	2		T9	2		T10	2
all_pins[2]	transitions[0x0=>0x1]	53	1			T9	2		T10	2		T75	2
all_pins[2]	transitions[0x1=>0x0]	53	1			T11	1		T10	4		T76	2
all_pins[3]	values[0x0]	276	1			T13	1		T7	8		T8	3
all_pins[3]	values[0x1]	75	1			T8	2		T11	1		T10	4
all_pins[3]	transitions[0x0=>0x1]	54	1			T8	2		T11	1		T10	3
all_pins[3]	transitions[0x1=>0x0]	36	1			T7	2		T9	2		T10	1
all_pins[4]	values[0x0]	294	1			T13	1		T7	6		T8	5
all_pins[4]	values[0x1]	57	1			T7	2		T9	2		T10	2
all_pins[4]	transitions[0x0=>0x1]	47	1			T7	1		T9	2		T10	1
all_pins[4]	transitions[0x1=>0x0]	49	1			T68	4		T77	1		T78	2
all_pins[5]	values[0x0]	292	1			T13	1		T7	7		T8	5
all_pins[5]	values[0x1]	59	1			T7	1		T10	1		T68	4
all_pins[5]	transitions[0x0=>0x1]	46	1			T7	1		T10	1		T68	3
all_pins[5]	transitions[0x1=>0x0]	62	1			T7	2		T9	3		T10	1
all_pins[6]	values[0x0]	276	1			T13	1		T7	6		T8	5
all_pins[6]	values[0x1]	75	1			T7	2		T9	3		T10	1
all_pins[6]	transitions[0x0=>0x1]	44	1			T7	2		T9	3		T68	1
all_pins[6]	transitions[0x1=>0x0]	46	1			T7	1		T11	1		T10	1
all_pins[7]	values[0x0]	274	1			T13	1		T7	7		T8	5
all_pins[7]	values[0x1]	77	1			T7	1		T11	1		T10	2
all_pins[7]	transitions[0x0=>0x1]	48	1			T7	1		T11	1		T10	1
all_pins[7]	transitions[0x1=>0x0]	45	1			T7	1		T9	4		T77	2
all_pins[8]	values[0x0]	277	1			T13	1		T7	7		T8	5
all_pins[8]	values[0x1]	74	1			T7	1		T9	4		T10	1
all_pins[8]	transitions[0x0=>0x1]	48	1			T7	1		T9	4		T10	1
all_pins[8]	transitions[0x1=>0x0]	59	1			T7	1		T8	1		T10	1
all_pins[9]	values[0x0]	266	1			T13	1		T7	7		T8	4
all_pins[9]	values[0x1]	85	1			T7	1		T8	1		T10	1
all_pins[9]	transitions[0x0=>0x1]	60	1			T8	1		T76	2		T68	2
all_pins[9]	transitions[0x1=>0x0]	38	1			T7	1		T8	1		T9	2
all_pins[10]	values[0x0]	288	1			T13	1		T7	6		T8	4
all_pins[10]	values[0x1]	63	1			T7	2		T8	1		T9	2
all_pins[10]	transitions[0x0=>0x1]	54	1			T7	2		T8	1		T9	1
all_pins[10]	transitions[0x1=>0x0]	49	1			T7	1		T11	3		T9	3
all_pins[11]	values[0x0]	293	1			T13	1		T7	7		T8	5
all_pins[11]	values[0x1]	58	1			T7	1		T11	3		T9	4
all_pins[11]	transitions[0x0=>0x1]	42	1			T11	1		T9	3		T10	2
all_pins[11]	transitions[0x1=>0x0]	42	1			T7	1		T8	1		T76	1
all_pins[12]	values[0x0]	293	1			T13	1		T7	6		T8	4
all_pins[12]	values[0x1]	58	1			T7	2		T8	1		T11	2
all_pins[12]	transitions[0x0=>0x1]	42	1			T7	1		T8	1		T11	2
all_pins[12]	transitions[0x1=>0x0]	68	1			T11	1		T9	1		T10	2
all_pins[13]	values[0x0]	267	1			T13	1		T7	7		T8	5
all_pins[13]	values[0x1]	84	1			T7	1		T11	1		T9	1
all_pins[13]	transitions[0x0=>0x1]	60	1			T7	1		T11	1		T9	1
all_pins[13]	transitions[0x1=>0x0]	54	1			T7	2		T8	1		T9	2
all_pins[14]	values[0x0]	273	1			T13	1		T7	6		T8	4
all_pins[14]	values[0x1]	78	1			T7	2		T8	1		T9	2
all_pins[14]	transitions[0x0=>0x1]	44	1			T7	2		T8	1		T10	2
all_pins[14]	transitions[0x1=>0x0]	48	1			T7	1		T11	3		T9	3