Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
59.07	52.44	59.16	94.90	0.00	53.13	100.00	53.89

Total tests in report: 164

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.75	51.75	49.66	49.66	51.27	51.27	95.65	95.65	0.00	0.00	50.38	50.38	96.46	96.46	18.80	18.80	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.381428166
57.68	5.93	51.76	2.10	57.22	5.95	99.49	3.84	0.00	0.00	53.02	2.63	96.78	0.32	45.48	26.68	/workspace/coverage/cover_reg_top/37.i2c_intr_test.3916155800
58.36	0.68	51.76	0.00	58.62	1.40	100.00	0.51	0.00	0.00	53.13	0.11	97.11	0.32	47.90	2.42	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.3596576539
58.76	0.41	51.76	0.00	58.62	0.00	100.00	0.00	0.00	0.00	53.13	0.00	97.11	0.00	50.74	2.84	/workspace/coverage/cover_reg_top/12.i2c_intr_test.2998834858
59.13	0.37	51.76	0.00	58.62	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.68	2.57	50.74	0.00	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.139529842
59.30	0.17	51.76	0.00	58.62	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.00	51.89	1.16	/workspace/coverage/cover_reg_top/30.i2c_intr_test.3761754914
59.44	0.15	52.44	0.68	58.76	0.13	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.00	52.10	0.21	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.487395349
59.53	0.09	52.44	0.00	58.76	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.00	52.73	0.63	/workspace/coverage/cover_reg_top/8.i2c_intr_test.2192334875
59.59	0.06	52.44	0.00	58.76	0.00	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.00	53.15	0.42	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2233057119
59.64	0.05	52.44	0.00	58.89	0.13	100.00	0.00	0.00	0.00	53.13	0.00	99.68	0.00	53.36	0.21	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3522734369
59.69	0.05	52.44	0.00	58.89	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.32	53.36	0.00	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1493723987
59.72	0.03	52.44	0.00	58.89	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.57	0.21	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3058751823
59.75	0.03	52.44	0.00	58.89	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.78	0.21	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1509649655
59.77	0.02	52.44	0.00	59.02	0.13	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.78	0.00	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.349196432
59.78	0.02	52.44	0.00	59.02	0.00	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.89	0.11	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1173429695
59.79	0.01	52.44	0.00	59.09	0.07	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.89	0.00	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.1221340385
59.80	0.01	52.44	0.00	59.16	0.07	100.00	0.00	0.00	0.00	53.13	0.00	100.00	0.00	53.89	0.00	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.527670600

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3775006795
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.149911798
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2545101213
/workspace/coverage/cover_reg_top/0.i2c_intr_test.706015733
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.658468542
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2545591068
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3680714291
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.4284475941
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3273067469
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3689613353
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.317395392
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4042587227
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.112944649
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3827655482
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1105152639
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.697891437
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3161603277
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3685872573
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3718521259
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1987822308
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1211811939
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1621034246
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.760145667
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3512680674
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3110140113
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.285710069
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4086727644
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.90789388
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2807527286
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4284285060
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.575228850
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2668578277
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.2159811611
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3338121862
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2459817929
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2552185236
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2940714567
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2569724755
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2340780266
/workspace/coverage/cover_reg_top/15.i2c_intr_test.3498317362
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3566617397
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.2737404918
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3310115674
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3363577209
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2992505593
/workspace/coverage/cover_reg_top/16.i2c_intr_test.1845665159
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3729009752
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1475644431
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2614587580
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.4057672726
/workspace/coverage/cover_reg_top/17.i2c_intr_test.2846186851
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1205896668
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3690762741
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1537079472
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3709701326
/workspace/coverage/cover_reg_top/18.i2c_intr_test.3566264322
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2723690076
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.759028256
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2092903012
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.630840885
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3405708655
/workspace/coverage/cover_reg_top/19.i2c_intr_test.185143674
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.337364164
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1399501091
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2323917546
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1395448693
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1055144788
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3640265291
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1188452638
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3012966344
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3829074163
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1768685062
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2521772564
/workspace/coverage/cover_reg_top/20.i2c_intr_test.1474796938
/workspace/coverage/cover_reg_top/21.i2c_intr_test.3802023340
/workspace/coverage/cover_reg_top/22.i2c_intr_test.457146282
/workspace/coverage/cover_reg_top/23.i2c_intr_test.148985722
/workspace/coverage/cover_reg_top/24.i2c_intr_test.372946968
/workspace/coverage/cover_reg_top/25.i2c_intr_test.856238711
/workspace/coverage/cover_reg_top/26.i2c_intr_test.270822568
/workspace/coverage/cover_reg_top/27.i2c_intr_test.3888602464
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3108776880
/workspace/coverage/cover_reg_top/29.i2c_intr_test.1806352212
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.422140677
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1284110995
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2540471803
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2793052206
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.4165434502
/workspace/coverage/cover_reg_top/3.i2c_intr_test.3382105144
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3912993341
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2456425392
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1752922983
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1726714826
/workspace/coverage/cover_reg_top/32.i2c_intr_test.2588988851
/workspace/coverage/cover_reg_top/33.i2c_intr_test.483889335
/workspace/coverage/cover_reg_top/34.i2c_intr_test.2282351312
/workspace/coverage/cover_reg_top/35.i2c_intr_test.3141439078
/workspace/coverage/cover_reg_top/36.i2c_intr_test.4022670392
/workspace/coverage/cover_reg_top/38.i2c_intr_test.467208963
/workspace/coverage/cover_reg_top/39.i2c_intr_test.191938143
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2536134660
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.878044353
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4046532479
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3041599321
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.533340717
/workspace/coverage/cover_reg_top/4.i2c_intr_test.2077735621
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2776241441
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2663588004
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3737721075
/workspace/coverage/cover_reg_top/40.i2c_intr_test.2487332857
/workspace/coverage/cover_reg_top/41.i2c_intr_test.2766306589
/workspace/coverage/cover_reg_top/42.i2c_intr_test.2237064294
/workspace/coverage/cover_reg_top/43.i2c_intr_test.3841947258
/workspace/coverage/cover_reg_top/44.i2c_intr_test.2882977395
/workspace/coverage/cover_reg_top/45.i2c_intr_test.3914965248
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3187111201
/workspace/coverage/cover_reg_top/47.i2c_intr_test.2712960374
/workspace/coverage/cover_reg_top/48.i2c_intr_test.3898036392
/workspace/coverage/cover_reg_top/49.i2c_intr_test.1588037170
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3731431666
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.1749116411
/workspace/coverage/cover_reg_top/5.i2c_intr_test.826121563
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4201370158
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3376767433
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4234053052
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.924883497
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2436336727
/workspace/coverage/cover_reg_top/6.i2c_intr_test.1396243086
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3599084672
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2842410501
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4234328225
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1712544967
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2428240833
/workspace/coverage/cover_reg_top/7.i2c_intr_test.1650520989
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1538475606
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.2378058508
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1859886768
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.778213003
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.674179309
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1542396111
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.3454840941
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.33801980
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.3374826305
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2161443741
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4185273004
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3819161478
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2035174069

Total test records in report: 164

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.487395349	Jan 14 01:13:55 PM PST 24	Jan 14 01:13:57 PM PST 24	24682246 ps
T2	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.139529842	Jan 14 01:13:42 PM PST 24	Jan 14 01:13:43 PM PST 24	71524663 ps
T3	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3737721075	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:30 PM PST 24	492813490 ps
T4	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.381428166	Jan 14 01:13:36 PM PST 24	Jan 14 01:13:39 PM PST 24	228038831 ps
T5	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3640265291	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:33 PM PST 24	56330924 ps
T13	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.3596576539	Jan 14 01:13:42 PM PST 24	Jan 14 01:13:44 PM PST 24	67655618 ps
T14	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.778213003	Jan 14 01:13:38 PM PST 24	Jan 14 01:13:39 PM PST 24	68280356 ps
T6	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3599084672	Jan 14 01:13:28 PM PST 24	Jan 14 01:13:30 PM PST 24	21831137 ps
T7	/workspace/coverage/cover_reg_top/37.i2c_intr_test.3916155800	Jan 14 01:14:01 PM PST 24	Jan 14 01:14:02 PM PST 24	26585900 ps
T8	/workspace/coverage/cover_reg_top/27.i2c_intr_test.3888602464	Jan 14 01:14:03 PM PST 24	Jan 14 01:14:05 PM PST 24	22030285 ps
T15	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2456425392	Jan 14 01:13:30 PM PST 24	Jan 14 01:13:34 PM PST 24	49471795 ps
T16	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.285710069	Jan 14 01:13:45 PM PST 24	Jan 14 01:13:48 PM PST 24	84400708 ps
T17	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2614587580	Jan 14 01:13:48 PM PST 24	Jan 14 01:13:49 PM PST 24	27349488 ps
T22	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2323917546	Jan 14 01:13:29 PM PST 24	Jan 14 01:13:31 PM PST 24	73359117 ps
T18	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2552185236	Jan 14 01:14:00 PM PST 24	Jan 14 01:14:04 PM PST 24	1576832898 ps
T11	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1396243086	Jan 14 01:13:29 PM PST 24	Jan 14 01:13:31 PM PST 24	38065732 ps
T19	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.759028256	Jan 14 01:13:46 PM PST 24	Jan 14 01:13:48 PM PST 24	140843938 ps
T23	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.527670600	Jan 14 01:13:44 PM PST 24	Jan 14 01:13:46 PM PST 24	263613385 ps
T20	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3690762741	Jan 14 01:13:51 PM PST 24	Jan 14 01:13:53 PM PST 24	50997304 ps
T12	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2459817929	Jan 14 01:14:03 PM PST 24	Jan 14 01:14:06 PM PST 24	25009925 ps
T89	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3731431666	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:33 PM PST 24	18209762 ps
T9	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3338121862	Jan 14 01:13:57 PM PST 24	Jan 14 01:13:59 PM PST 24	38829660 ps
T10	/workspace/coverage/cover_reg_top/40.i2c_intr_test.2487332857	Jan 14 01:14:00 PM PST 24	Jan 14 01:14:02 PM PST 24	18402385 ps
T90	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1537079472	Jan 14 01:13:49 PM PST 24	Jan 14 01:13:50 PM PST 24	77599528 ps
T51	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.658468542	Jan 14 01:13:17 PM PST 24	Jan 14 01:13:20 PM PST 24	52349692 ps
T66	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2793052206	Jan 14 01:13:28 PM PST 24	Jan 14 01:13:30 PM PST 24	30925461 ps
T52	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1538475606	Jan 14 01:13:30 PM PST 24	Jan 14 01:13:32 PM PST 24	79071549 ps
T21	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2842410501	Jan 14 01:13:29 PM PST 24	Jan 14 01:13:32 PM PST 24	480165793 ps
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T56	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3273067469	Jan 14 01:13:26 PM PST 24	Jan 14 01:13:28 PM PST 24	20623949 ps
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T24	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1284110995	Jan 14 01:13:29 PM PST 24	Jan 14 01:13:35 PM PST 24	587026901 ps
T25	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4046532479	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:33 PM PST 24	22597049 ps
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T75	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1173429695	Jan 14 01:13:23 PM PST 24	Jan 14 01:13:25 PM PST 24	23572638 ps
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T67	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3363577209	Jan 14 01:13:48 PM PST 24	Jan 14 01:13:49 PM PST 24	81327276 ps
T77	/workspace/coverage/cover_reg_top/25.i2c_intr_test.856238711	Jan 14 01:13:59 PM PST 24	Jan 14 01:14:01 PM PST 24	36132094 ps
T55	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1205896668	Jan 14 01:13:57 PM PST 24	Jan 14 01:13:59 PM PST 24	80254829 ps
T26	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.1749116411	Jan 14 01:13:32 PM PST 24	Jan 14 01:13:34 PM PST 24	54934108 ps
T27	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2536134660	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:29 PM PST 24	127721976 ps
T28	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1542396111	Jan 14 01:13:32 PM PST 24	Jan 14 01:13:34 PM PST 24	84708192 ps
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T65	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2668578277	Jan 14 01:13:41 PM PST 24	Jan 14 01:13:43 PM PST 24	525076167 ps
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T29	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3680714291	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:30 PM PST 24	391753288 ps
T93	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.33801980	Jan 14 01:13:44 PM PST 24	Jan 14 01:13:45 PM PST 24	21519018 ps
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T31	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.878044353	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:32 PM PST 24	355139419 ps
T32	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3827655482	Jan 14 01:13:38 PM PST 24	Jan 14 01:13:40 PM PST 24	72703222 ps
T42	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2569724755	Jan 14 01:13:44 PM PST 24	Jan 14 01:13:45 PM PST 24	114454665 ps
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T45	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3689613353	Jan 14 01:13:21 PM PST 24	Jan 14 01:13:22 PM PST 24	18425598 ps
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T47	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3718521259	Jan 14 01:13:43 PM PST 24	Jan 14 01:13:44 PM PST 24	115479575 ps
T48	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3566617397	Jan 14 01:13:47 PM PST 24	Jan 14 01:13:49 PM PST 24	161214314 ps
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T69	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1621034246	Jan 14 01:13:52 PM PST 24	Jan 14 01:13:53 PM PST 24	67399599 ps
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T74	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2035174069	Jan 14 01:13:39 PM PST 24	Jan 14 01:13:41 PM PST 24	186840349 ps
T34	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.317395392	Jan 14 01:13:21 PM PST 24	Jan 14 01:13:23 PM PST 24	18482623 ps
T49	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4284285060	Jan 14 01:13:50 PM PST 24	Jan 14 01:13:51 PM PST 24	53462561 ps
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T35	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.149911798	Jan 14 01:13:22 PM PST 24	Jan 14 01:13:27 PM PST 24	178381700 ps
T84	/workspace/coverage/cover_reg_top/8.i2c_intr_test.2192334875	Jan 14 01:13:36 PM PST 24	Jan 14 01:13:38 PM PST 24	17105393 ps
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T80	/workspace/coverage/cover_reg_top/30.i2c_intr_test.3761754914	Jan 14 01:14:01 PM PST 24	Jan 14 01:14:03 PM PST 24	15242689 ps
T36	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1395448693	Jan 14 01:13:26 PM PST 24	Jan 14 01:13:30 PM PST 24	54178670 ps
T96	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4201370158	Jan 14 01:13:29 PM PST 24	Jan 14 01:13:31 PM PST 24	60961849 ps
T87	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3108776880	Jan 14 01:13:58 PM PST 24	Jan 14 01:13:59 PM PST 24	91476479 ps
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T97	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1987822308	Jan 14 01:13:42 PM PST 24	Jan 14 01:13:43 PM PST 24	61216620 ps
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T99	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3110140113	Jan 14 01:13:48 PM PST 24	Jan 14 01:13:49 PM PST 24	23283355 ps
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T102	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2233057119	Jan 14 01:13:20 PM PST 24	Jan 14 01:13:22 PM PST 24	78658322 ps
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T104	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.112944649	Jan 14 01:13:42 PM PST 24	Jan 14 01:13:43 PM PST 24	103215731 ps
T105	/workspace/coverage/cover_reg_top/7.i2c_intr_test.1650520989	Jan 14 01:13:29 PM PST 24	Jan 14 01:13:31 PM PST 24	17953211 ps
T106	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.4284475941	Jan 14 01:13:22 PM PST 24	Jan 14 01:13:25 PM PST 24	643652435 ps
T37	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.422140677	Jan 14 01:13:26 PM PST 24	Jan 14 01:13:28 PM PST 24	30441159 ps
T60	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.349196432	Jan 14 01:13:36 PM PST 24	Jan 14 01:13:38 PM PST 24	135921293 ps
T107	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3912993341	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:30 PM PST 24	55007985 ps
T50	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1493723987	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:29 PM PST 24	48349987 ps
T85	/workspace/coverage/cover_reg_top/23.i2c_intr_test.148985722	Jan 14 01:13:58 PM PST 24	Jan 14 01:13:59 PM PST 24	28430566 ps
T81	/workspace/coverage/cover_reg_top/29.i2c_intr_test.1806352212	Jan 14 01:14:00 PM PST 24	Jan 14 01:14:01 PM PST 24	18157866 ps
T39	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.4057672726	Jan 14 01:13:44 PM PST 24	Jan 14 01:13:46 PM PST 24	27131294 ps
T40	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3775006795	Jan 14 01:13:25 PM PST 24	Jan 14 01:13:28 PM PST 24	59927656 ps
T70	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1509649655	Jan 14 01:13:52 PM PST 24	Jan 14 01:13:53 PM PST 24	287109786 ps
T108	/workspace/coverage/cover_reg_top/4.i2c_intr_test.2077735621	Jan 14 01:13:30 PM PST 24	Jan 14 01:13:32 PM PST 24	16468706 ps
T109	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2436336727	Jan 14 01:13:30 PM PST 24	Jan 14 01:13:32 PM PST 24	137942516 ps
T110	/workspace/coverage/cover_reg_top/47.i2c_intr_test.2712960374	Jan 14 01:13:56 PM PST 24	Jan 14 01:13:57 PM PST 24	18366517 ps
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T112	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4086727644	Jan 14 01:13:55 PM PST 24	Jan 14 01:13:57 PM PST 24	413658200 ps
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T116	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2723690076	Jan 14 01:13:57 PM PST 24	Jan 14 01:13:58 PM PST 24	34106291 ps
T117	/workspace/coverage/cover_reg_top/41.i2c_intr_test.2766306589	Jan 14 01:13:49 PM PST 24	Jan 14 01:13:50 PM PST 24	17074485 ps
T118	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.575228850	Jan 14 01:13:51 PM PST 24	Jan 14 01:13:54 PM PST 24	43375367 ps
T71	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.533340717	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:33 PM PST 24	32766857 ps
T88	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.630840885	Jan 14 01:13:59 PM PST 24	Jan 14 01:14:00 PM PST 24	29492114 ps
T58	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2521772564	Jan 14 01:13:25 PM PST 24	Jan 14 01:13:28 PM PST 24	426435638 ps
T119	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.697891437	Jan 14 01:13:42 PM PST 24	Jan 14 01:13:43 PM PST 24	33180761 ps
T120	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2776241441	Jan 14 01:13:33 PM PST 24	Jan 14 01:13:35 PM PST 24	21938647 ps
T121	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1188452638	Jan 14 01:13:28 PM PST 24	Jan 14 01:13:30 PM PST 24	53194748 ps
T41	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1055144788	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:29 PM PST 24	151926742 ps
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T125	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.924883497	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:33 PM PST 24	33987673 ps
T126	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2428240833	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:33 PM PST 24	42526001 ps
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T127	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2545101213	Jan 14 01:13:25 PM PST 24	Jan 14 01:13:28 PM PST 24	22636079 ps
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T130	/workspace/coverage/cover_reg_top/33.i2c_intr_test.483889335	Jan 14 01:13:47 PM PST 24	Jan 14 01:13:48 PM PST 24	38215644 ps
T63	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3685872573	Jan 14 01:13:35 PM PST 24	Jan 14 01:13:37 PM PST 24	116140261 ps
T131	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3041599321	Jan 14 01:13:27 PM PST 24	Jan 14 01:13:30 PM PST 24	93682056 ps
T38	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2340780266	Jan 14 01:13:50 PM PST 24	Jan 14 01:13:51 PM PST 24	37512280 ps
T132	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3405708655	Jan 14 01:13:57 PM PST 24	Jan 14 01:13:58 PM PST 24	22285852 ps
T133	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3729009752	Jan 14 01:13:51 PM PST 24	Jan 14 01:13:52 PM PST 24	39672647 ps
T134	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1768685062	Jan 14 01:13:23 PM PST 24	Jan 14 01:13:25 PM PST 24	30473532 ps
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T151	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3512680674	Jan 14 01:13:51 PM PST 24	Jan 14 01:13:52 PM PST 24	58256276 ps
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T153	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3829074163	Jan 14 01:13:30 PM PST 24	Jan 14 01:13:32 PM PST 24	88772530 ps
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T155	/workspace/coverage/cover_reg_top/5.i2c_intr_test.826121563	Jan 14 01:13:30 PM PST 24	Jan 14 01:13:32 PM PST 24	36158833 ps
T156	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2846186851	Jan 14 01:13:45 PM PST 24	Jan 14 01:13:47 PM PST 24	25815373 ps
T157	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1712544967	Jan 14 01:13:31 PM PST 24	Jan 14 01:13:34 PM PST 24	51953234 ps
T158	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2092903012	Jan 14 01:13:44 PM PST 24	Jan 14 01:13:46 PM PST 24	143729764 ps
T159	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.674179309	Jan 14 01:13:33 PM PST 24	Jan 14 01:13:34 PM PST 24	18517010 ps
T160	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3802023340	Jan 14 01:13:51 PM PST 24	Jan 14 01:13:52 PM PST 24	72446097 ps
T161	/workspace/coverage/cover_reg_top/45.i2c_intr_test.3914965248	Jan 14 01:13:52 PM PST 24	Jan 14 01:13:53 PM PST 24	23968854 ps
T162	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4185273004	Jan 14 01:13:37 PM PST 24	Jan 14 01:13:39 PM PST 24	40497879 ps
T163	/workspace/coverage/cover_reg_top/39.i2c_intr_test.191938143	Jan 14 01:14:02 PM PST 24	Jan 14 01:14:05 PM PST 24	75010722 ps
T164	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1726714826	Jan 14 01:14:03 PM PST 24	Jan 14 01:14:05 PM PST 24	45682886 ps

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.381428166
Short name	T4
Test name
Test status
Simulation time	228038831 ps
CPU time	1.99 seconds
Started	Jan 14 01:13:36 PM PST 24
Finished	Jan 14 01:13:39 PM PST 24
Peak memory	202804 kb
Host	smart-eab2906d-b49b-4c14-a5f4-a5ac87f03b4d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381428166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.381428166
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.3916155800
Short name	T7
Test name
Test status
Simulation time	26585900 ps
CPU time	0.7 seconds
Started	Jan 14 01:14:01 PM PST 24
Finished	Jan 14 01:14:02 PM PST 24
Peak memory	202728 kb
Host	smart-3d66414d-ecdd-4ddc-882b-ec5e9e0f8ccf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916155800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3916155800
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.3596576539
Short name	T13
Test name
Test status
Simulation time	67655618 ps
CPU time	1.5 seconds
Started	Jan 14 01:13:42 PM PST 24
Finished	Jan 14 01:13:44 PM PST 24
Peak memory	202912 kb
Host	smart-6e02e81a-0d91-470a-b311-c45e293238d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596576539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3596576539
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.2998834858
Short name	T78
Test name
Test status
Simulation time	18082196 ps
CPU time	0.67 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:01 PM PST 24
Peak memory	202420 kb
Host	smart-ffa618c4-492b-4f74-895c-31b3da01e106
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998834858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2998834858
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.139529842
Short name	T2
Test name
Test status
Simulation time	71524663 ps
CPU time	0.71 seconds
Started	Jan 14 01:13:42 PM PST 24
Finished	Jan 14 01:13:43 PM PST 24
Peak memory	202644 kb
Host	smart-87bfa4f9-6592-4677-b036-5e837df78fcd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139529842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.139529842
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.3761754914
Short name	T80
Test name
Test status
Simulation time	15242689 ps
CPU time	0.69 seconds
Started	Jan 14 01:14:01 PM PST 24
Finished	Jan 14 01:14:03 PM PST 24
Peak memory	202672 kb
Host	smart-886199cd-3e77-4f63-ab8c-1da17e02b5b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761754914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3761754914
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.487395349
Short name	T1
Test name
Test status
Simulation time	24682246 ps
CPU time	1.08 seconds
Started	Jan 14 01:13:55 PM PST 24
Finished	Jan 14 01:13:57 PM PST 24
Peak memory	203012 kb
Host	smart-9e53702e-510c-4f20-b9a2-05b5fda4bf88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487395349 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.487395349
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.2192334875
Short name	T84
Test name
Test status
Simulation time	17105393 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:36 PM PST 24
Finished	Jan 14 01:13:38 PM PST 24
Peak memory	202664 kb
Host	smart-a8b6c76d-087c-4ab9-a916-480a038a88d5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192334875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2192334875
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2233057119
Short name	T102
Test name
Test status
Simulation time	78658322 ps
CPU time	0.94 seconds
Started	Jan 14 01:13:20 PM PST 24
Finished	Jan 14 01:13:22 PM PST 24
Peak memory	202984 kb
Host	smart-5c4a4381-311f-4d38-9d49-528469b90e21
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233057119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.2233057119
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3522734369
Short name	T149
Test name
Test status
Simulation time	312777344 ps
CPU time	1.79 seconds
Started	Jan 14 01:13:23 PM PST 24
Finished	Jan 14 01:13:26 PM PST 24
Peak memory	203008 kb
Host	smart-375a6e30-aed2-4edd-bc77-a603f77a699d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522734369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3522734369
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1493723987
Short name	T50
Test name
Test status
Simulation time	48349987 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:29 PM PST 24
Peak memory	202664 kb
Host	smart-db1d3358-dd51-43ef-82a5-9c11907c8af5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493723987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1493723987
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3058751823
Short name	T72
Test name
Test status
Simulation time	32441826 ps
CPU time	0.74 seconds
Started	Jan 14 01:13:19 PM PST 24
Finished	Jan 14 01:13:21 PM PST 24
Peak memory	202816 kb
Host	smart-ab423b51-788e-4988-a837-169c98f0c5fc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058751823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3058751823
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1509649655
Short name	T70
Test name
Test status
Simulation time	287109786 ps
CPU time	0.93 seconds
Started	Jan 14 01:13:52 PM PST 24
Finished	Jan 14 01:13:53 PM PST 24
Peak memory	202872 kb
Host	smart-ecfc4d12-c534-498d-b51e-03fdfff672b6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509649655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.1509649655
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.349196432
Short name	T60
Test name
Test status
Simulation time	135921293 ps
CPU time	1.77 seconds
Started	Jan 14 01:13:36 PM PST 24
Finished	Jan 14 01:13:38 PM PST 24
Peak memory	202972 kb
Host	smart-c7f29652-7bdc-4482-8273-4823acea768b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349196432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.349196432
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1173429695
Short name	T75
Test name
Test status
Simulation time	23572638 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:23 PM PST 24
Finished	Jan 14 01:13:25 PM PST 24
Peak memory	202644 kb
Host	smart-166ea7b6-7d5c-470d-879b-1ba92c1782cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173429695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1173429695
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.1221340385
Short name	T91
Test name
Test status
Simulation time	111366716 ps
CPU time	1.61 seconds
Started	Jan 14 01:13:26 PM PST 24
Finished	Jan 14 01:13:29 PM PST 24
Peak memory	202916 kb
Host	smart-b08d7314-e12c-45eb-837a-65951136aa59
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221340385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1221340385
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.527670600
Short name	T23
Test name
Test status
Simulation time	263613385 ps
CPU time	1.36 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:46 PM PST 24
Peak memory	202880 kb
Host	smart-8a707292-fbd2-4fc9-b337-0765044202a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527670600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.527670600
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3775006795
Short name	T40
Test name
Test status
Simulation time	59927656 ps
CPU time	1.35 seconds
Started	Jan 14 01:13:25 PM PST 24
Finished	Jan 14 01:13:28 PM PST 24
Peak memory	202888 kb
Host	smart-b8f85750-3e3c-48ec-807a-9574f6125d54
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775006795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3775006795
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.149911798
Short name	T35
Test name
Test status
Simulation time	178381700 ps
CPU time	3.42 seconds
Started	Jan 14 01:13:22 PM PST 24
Finished	Jan 14 01:13:27 PM PST 24
Peak memory	202876 kb
Host	smart-eeaf444c-0cc4-4839-92fd-1c6dd0b8f650
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149911798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.149911798
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2545101213
Short name	T127
Test name
Test status
Simulation time	22636079 ps
CPU time	1.06 seconds
Started	Jan 14 01:13:25 PM PST 24
Finished	Jan 14 01:13:28 PM PST 24
Peak memory	203008 kb
Host	smart-8467cd60-77fb-4823-b959-28b6521387a0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545101213 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2545101213
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.706015733
Short name	T124
Test name
Test status
Simulation time	46493131 ps
CPU time	0.64 seconds
Started	Jan 14 01:13:21 PM PST 24
Finished	Jan 14 01:13:23 PM PST 24
Peak memory	202680 kb
Host	smart-5c7db0ce-c953-451b-9a3d-cd4834323e57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706015733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.706015733
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.658468542
Short name	T51
Test name
Test status
Simulation time	52349692 ps
CPU time	0.93 seconds
Started	Jan 14 01:13:17 PM PST 24
Finished	Jan 14 01:13:20 PM PST 24
Peak memory	202824 kb
Host	smart-492dd945-0a2e-4d7c-a82d-0a184ea572b8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658468542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out standing.658468542
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2545591068
Short name	T113
Test name
Test status
Simulation time	124138634 ps
CPU time	1.95 seconds
Started	Jan 14 01:13:23 PM PST 24
Finished	Jan 14 01:13:26 PM PST 24
Peak memory	203068 kb
Host	smart-66f48080-6e8d-4fe4-a606-be66f569af37
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545591068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2545591068
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3680714291
Short name	T29
Test name
Test status
Simulation time	391753288 ps
CPU time	1.31 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202872 kb
Host	smart-03f125ba-1a9e-4400-8ef2-6d7a619a6495
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680714291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3680714291
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.4284475941
Short name	T106
Test name
Test status
Simulation time	643652435 ps
CPU time	2.28 seconds
Started	Jan 14 01:13:22 PM PST 24
Finished	Jan 14 01:13:25 PM PST 24
Peak memory	202936 kb
Host	smart-e6c1ed9c-9796-40da-bdc6-2e8b78e165de
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284475941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.4284475941
Directory	/workspace/1.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3273067469
Short name	T56
Test name
Test status
Simulation time	20623949 ps
CPU time	0.69 seconds
Started	Jan 14 01:13:26 PM PST 24
Finished	Jan 14 01:13:28 PM PST 24
Peak memory	201924 kb
Host	smart-352b3eee-15aa-496c-9e69-8e6e93cb56da
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273067469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3273067469
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3689613353
Short name	T45
Test name
Test status
Simulation time	18425598 ps
CPU time	0.77 seconds
Started	Jan 14 01:13:21 PM PST 24
Finished	Jan 14 01:13:22 PM PST 24
Peak memory	202784 kb
Host	smart-de8b500c-dc09-430d-b56f-79cfe8e1f92b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689613353 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3689613353
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.317395392
Short name	T34
Test name
Test status
Simulation time	18482623 ps
CPU time	0.74 seconds
Started	Jan 14 01:13:21 PM PST 24
Finished	Jan 14 01:13:23 PM PST 24
Peak memory	202728 kb
Host	smart-4fa34328-61c5-41ab-91c1-e38b5181870d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317395392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.317395392
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4042587227
Short name	T57
Test name
Test status
Simulation time	231509743 ps
CPU time	1.92 seconds
Started	Jan 14 01:13:22 PM PST 24
Finished	Jan 14 01:13:25 PM PST 24
Peak memory	202960 kb
Host	smart-c72862f5-97d2-442b-8934-96f5f3bdd451
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042587227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.4042587227
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.112944649
Short name	T104
Test name
Test status
Simulation time	103215731 ps
CPU time	0.82 seconds
Started	Jan 14 01:13:42 PM PST 24
Finished	Jan 14 01:13:43 PM PST 24
Peak memory	202780 kb
Host	smart-beab28bc-ef6f-4e4b-b6e3-d90ddc2109a5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112944649 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.112944649
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3827655482
Short name	T32
Test name
Test status
Simulation time	72703222 ps
CPU time	0.72 seconds
Started	Jan 14 01:13:38 PM PST 24
Finished	Jan 14 01:13:40 PM PST 24
Peak memory	202768 kb
Host	smart-e4c56cf1-5e84-4eb0-9dfd-594104189bc9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827655482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3827655482
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1105152639
Short name	T83
Test name
Test status
Simulation time	19797411 ps
CPU time	0.62 seconds
Started	Jan 14 01:13:33 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	200844 kb
Host	smart-0de4a8c5-7575-4a5f-a004-95636cedbc65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105152639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1105152639
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.697891437
Short name	T119
Test name
Test status
Simulation time	33180761 ps
CPU time	0.81 seconds
Started	Jan 14 01:13:42 PM PST 24
Finished	Jan 14 01:13:43 PM PST 24
Peak memory	202696 kb
Host	smart-9f471a09-a387-4dae-bcbf-7a10aa21e4c3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697891437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou tstanding.697891437
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3161603277
Short name	T94
Test name
Test status
Simulation time	140756494 ps
CPU time	2.13 seconds
Started	Jan 14 01:13:38 PM PST 24
Finished	Jan 14 01:13:40 PM PST 24
Peak memory	202996 kb
Host	smart-23e16ff0-a2ad-4a22-b926-12a17b6b31bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161603277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3161603277
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3685872573
Short name	T63
Test name
Test status
Simulation time	116140261 ps
CPU time	1.28 seconds
Started	Jan 14 01:13:35 PM PST 24
Finished	Jan 14 01:13:37 PM PST 24
Peak memory	203016 kb
Host	smart-7bae2d22-7192-42f4-ae50-24d95cdc21e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685872573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3685872573
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3718521259
Short name	T47
Test name
Test status
Simulation time	115479575 ps
CPU time	0.76 seconds
Started	Jan 14 01:13:43 PM PST 24
Finished	Jan 14 01:13:44 PM PST 24
Peak memory	202836 kb
Host	smart-e091b724-a4da-4877-b204-84254fed5976
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718521259 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3718521259
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1987822308
Short name	T97
Test name
Test status
Simulation time	61216620 ps
CPU time	0.69 seconds
Started	Jan 14 01:13:42 PM PST 24
Finished	Jan 14 01:13:43 PM PST 24
Peak memory	202680 kb
Host	smart-1c0a00ff-122a-4237-a0c9-67aa5fa137ac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987822308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1987822308
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1211811939
Short name	T98
Test name
Test status
Simulation time	136573637 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:45 PM PST 24
Peak memory	202624 kb
Host	smart-f83b2554-c3ee-4cc9-98a1-9c5f60314e5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211811939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1211811939
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1621034246
Short name	T69
Test name
Test status
Simulation time	67399599 ps
CPU time	1.06 seconds
Started	Jan 14 01:13:52 PM PST 24
Finished	Jan 14 01:13:53 PM PST 24
Peak memory	202860 kb
Host	smart-26033475-161c-4283-87e3-edad739384e4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621034246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.1621034246
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.760145667
Short name	T152
Test name
Test status
Simulation time	85345199 ps
CPU time	2.21 seconds
Started	Jan 14 01:13:40 PM PST 24
Finished	Jan 14 01:13:43 PM PST 24
Peak memory	203016 kb
Host	smart-f0e6c218-7756-4fda-8a6d-1fd3e3687117
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760145667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.760145667
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3512680674
Short name	T151
Test name
Test status
Simulation time	58256276 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:51 PM PST 24
Finished	Jan 14 01:13:52 PM PST 24
Peak memory	202796 kb
Host	smart-19203631-d831-42f7-94c7-2e85b1706c2c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512680674 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3512680674
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3110140113
Short name	T99
Test name
Test status
Simulation time	23283355 ps
CPU time	0.82 seconds
Started	Jan 14 01:13:48 PM PST 24
Finished	Jan 14 01:13:49 PM PST 24
Peak memory	202712 kb
Host	smart-b5795086-c528-4782-8c26-cf0773d671dc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110140113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.3110140113
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.285710069
Short name	T16
Test name
Test status
Simulation time	84400708 ps
CPU time	1.92 seconds
Started	Jan 14 01:13:45 PM PST 24
Finished	Jan 14 01:13:48 PM PST 24
Peak memory	201536 kb
Host	smart-f8772fc2-cc4c-4661-b611-71e5534bf093
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285710069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.285710069
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4086727644
Short name	T112
Test name
Test status
Simulation time	413658200 ps
CPU time	1.32 seconds
Started	Jan 14 01:13:55 PM PST 24
Finished	Jan 14 01:13:57 PM PST 24
Peak memory	203028 kb
Host	smart-4abf6cf5-b42d-4dc9-a5b8-bc976929901c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086727644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4086727644
Directory	/workspace/12.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.90789388
Short name	T44
Test name
Test status
Simulation time	21125920 ps
CPU time	0.74 seconds
Started	Jan 14 01:13:50 PM PST 24
Finished	Jan 14 01:13:51 PM PST 24
Peak memory	202852 kb
Host	smart-e3fa7a2d-0ff1-4fb7-91ed-3ef4db4f4cac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90789388 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.90789388
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.2807527286
Short name	T79
Test name
Test status
Simulation time	22077668 ps
CPU time	0.76 seconds
Started	Jan 14 01:13:54 PM PST 24
Finished	Jan 14 01:13:56 PM PST 24
Peak memory	202624 kb
Host	smart-5fdbe17e-f47d-41aa-847a-9a435dc9aef4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807527286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2807527286
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4284285060
Short name	T49
Test name
Test status
Simulation time	53462561 ps
CPU time	0.78 seconds
Started	Jan 14 01:13:50 PM PST 24
Finished	Jan 14 01:13:51 PM PST 24
Peak memory	202784 kb
Host	smart-adf21267-f4b4-4fd9-a989-5a307a49e9fe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284285060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.4284285060
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.575228850
Short name	T118
Test name
Test status
Simulation time	43375367 ps
CPU time	2.09 seconds
Started	Jan 14 01:13:51 PM PST 24
Finished	Jan 14 01:13:54 PM PST 24
Peak memory	202840 kb
Host	smart-9451fa4d-3fbc-4319-aba2-7d79049d1bc9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575228850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.575228850
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2668578277
Short name	T65
Test name
Test status
Simulation time	525076167 ps
CPU time	1.74 seconds
Started	Jan 14 01:13:41 PM PST 24
Finished	Jan 14 01:13:43 PM PST 24
Peak memory	202976 kb
Host	smart-88c0aea6-bc5d-40d5-8db4-19441628066a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668578277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2668578277
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.2159811611
Short name	T30
Test name
Test status
Simulation time	94895657 ps
CPU time	0.65 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:06 PM PST 24
Peak memory	201832 kb
Host	smart-b15f4164-acc7-403b-9013-db348cbd4b13
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159811611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2159811611
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3338121862
Short name	T9
Test name
Test status
Simulation time	38829660 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:57 PM PST 24
Finished	Jan 14 01:13:59 PM PST 24
Peak memory	202720 kb
Host	smart-dcf360b3-ea1f-43a7-880a-fd08665eda7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338121862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3338121862
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2459817929
Short name	T12
Test name
Test status
Simulation time	25009925 ps
CPU time	0.96 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:06 PM PST 24
Peak memory	202908 kb
Host	smart-02d60b44-3d8a-4001-8ad6-49c567e39ad0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459817929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.2459817929
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2552185236
Short name	T18
Test name
Test status
Simulation time	1576832898 ps
CPU time	2.7 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:04 PM PST 24
Peak memory	202868 kb
Host	smart-e12c9405-480a-46dc-a068-951bdb9ba838
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552185236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2552185236
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2940714567
Short name	T150
Test name
Test status
Simulation time	72733704 ps
CPU time	1.14 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:06 PM PST 24
Peak memory	202936 kb
Host	smart-c5fa21ff-1c96-48e6-b7e3-1f5f087b40b7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940714567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2940714567
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2569724755
Short name	T42
Test name
Test status
Simulation time	114454665 ps
CPU time	0.97 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:45 PM PST 24
Peak memory	202704 kb
Host	smart-5660ec8f-2f5f-4611-9e7b-e2ed737974e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569724755 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2569724755
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2340780266
Short name	T38
Test name
Test status
Simulation time	37512280 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:50 PM PST 24
Finished	Jan 14 01:13:51 PM PST 24
Peak memory	202220 kb
Host	smart-4bc41a54-2aa8-4184-a213-baebe9604dae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340780266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2340780266
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.3498317362
Short name	T111
Test name
Test status
Simulation time	15102517 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:57 PM PST 24
Finished	Jan 14 01:13:58 PM PST 24
Peak memory	202720 kb
Host	smart-e522c6cb-6c82-4e3d-a142-7119bcd34b5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498317362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3498317362
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3566617397
Short name	T48
Test name
Test status
Simulation time	161214314 ps
CPU time	0.94 seconds
Started	Jan 14 01:13:47 PM PST 24
Finished	Jan 14 01:13:49 PM PST 24
Peak memory	202784 kb
Host	smart-79239770-c242-436b-922c-b7b471ec5b52
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566617397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.3566617397
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.2737404918
Short name	T143
Test name
Test status
Simulation time	196064404 ps
CPU time	1.46 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:02 PM PST 24
Peak memory	202596 kb
Host	smart-c90d59a4-86fc-4be7-befb-236623619775
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737404918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2737404918
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3310115674
Short name	T137
Test name
Test status
Simulation time	197099620 ps
CPU time	1.15 seconds
Started	Jan 14 01:13:49 PM PST 24
Finished	Jan 14 01:13:51 PM PST 24
Peak memory	202952 kb
Host	smart-a1299ae9-facd-4793-822d-dca03a77c475
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310115674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3310115674
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3363577209
Short name	T67
Test name
Test status
Simulation time	81327276 ps
CPU time	0.83 seconds
Started	Jan 14 01:13:48 PM PST 24
Finished	Jan 14 01:13:49 PM PST 24
Peak memory	202784 kb
Host	smart-f3617a52-1095-46bb-910a-1e81a7511758
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363577209 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3363577209
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2992505593
Short name	T53
Test name
Test status
Simulation time	25097197 ps
CPU time	0.75 seconds
Started	Jan 14 01:13:46 PM PST 24
Finished	Jan 14 01:13:47 PM PST 24
Peak memory	202680 kb
Host	smart-b8632249-868a-4360-a231-ed5c8b4c1880
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992505593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2992505593
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.1845665159
Short name	T154
Test name
Test status
Simulation time	77687068 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:46 PM PST 24
Peak memory	202656 kb
Host	smart-6b0ed659-0931-4cdb-b381-d921c7e9844c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845665159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1845665159
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3729009752
Short name	T133
Test name
Test status
Simulation time	39672647 ps
CPU time	0.99 seconds
Started	Jan 14 01:13:51 PM PST 24
Finished	Jan 14 01:13:52 PM PST 24
Peak memory	202984 kb
Host	smart-a8e39309-d0d9-4e34-a8d2-0e78f0c909d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729009752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.3729009752
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1475644431
Short name	T146
Test name
Test status
Simulation time	65656766 ps
CPU time	1.26 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:47 PM PST 24
Peak memory	202876 kb
Host	smart-196ee2b1-a3bf-4e09-9d57-ab8f2d4f7db5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475644431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1475644431
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2614587580
Short name	T17
Test name
Test status
Simulation time	27349488 ps
CPU time	1.17 seconds
Started	Jan 14 01:13:48 PM PST 24
Finished	Jan 14 01:13:49 PM PST 24
Peak memory	202932 kb
Host	smart-133ff354-3546-442a-9e3d-e2f717730059
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614587580 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2614587580
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.4057672726
Short name	T39
Test name
Test status
Simulation time	27131294 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:46 PM PST 24
Peak memory	202680 kb
Host	smart-d21e4cb0-d591-4f28-b31e-8270f5f757dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057672726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4057672726
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.2846186851
Short name	T156
Test name
Test status
Simulation time	25815373 ps
CPU time	0.63 seconds
Started	Jan 14 01:13:45 PM PST 24
Finished	Jan 14 01:13:47 PM PST 24
Peak memory	201344 kb
Host	smart-f5c3d879-8acd-4cd0-8544-3e9fb332cdf0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846186851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2846186851
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1205896668
Short name	T55
Test name
Test status
Simulation time	80254829 ps
CPU time	0.78 seconds
Started	Jan 14 01:13:57 PM PST 24
Finished	Jan 14 01:13:59 PM PST 24
Peak memory	202752 kb
Host	smart-4c40f151-deaa-4e43-bc12-f5a4e9be148d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205896668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.1205896668
Directory	/workspace/17.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3690762741
Short name	T20
Test name
Test status
Simulation time	50997304 ps
CPU time	1.39 seconds
Started	Jan 14 01:13:51 PM PST 24
Finished	Jan 14 01:13:53 PM PST 24
Peak memory	202904 kb
Host	smart-09d28469-d19b-4ee4-b72b-12c4290d2e42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690762741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3690762741
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1537079472
Short name	T90
Test name
Test status
Simulation time	77599528 ps
CPU time	0.83 seconds
Started	Jan 14 01:13:49 PM PST 24
Finished	Jan 14 01:13:50 PM PST 24
Peak memory	202804 kb
Host	smart-7b52fb91-e1fd-4983-bde6-dd208343333c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537079472 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1537079472
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3709701326
Short name	T54
Test name
Test status
Simulation time	35851511 ps
CPU time	0.74 seconds
Started	Jan 14 01:13:46 PM PST 24
Finished	Jan 14 01:13:47 PM PST 24
Peak memory	202648 kb
Host	smart-3e8857d0-ef76-4c5a-b622-9fcdbcceb71b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709701326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3709701326
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.3566264322
Short name	T141
Test name
Test status
Simulation time	83045813 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:49 PM PST 24
Finished	Jan 14 01:13:50 PM PST 24
Peak memory	202724 kb
Host	smart-a31d1d14-1acd-428f-a9cd-46e9380f06a8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566264322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3566264322
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2723690076
Short name	T116
Test name
Test status
Simulation time	34106291 ps
CPU time	0.81 seconds
Started	Jan 14 01:13:57 PM PST 24
Finished	Jan 14 01:13:58 PM PST 24
Peak memory	202728 kb
Host	smart-eaddcbce-e5b9-432f-be6f-9170a23c4ae6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723690076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.2723690076
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.759028256
Short name	T19
Test name
Test status
Simulation time	140843938 ps
CPU time	1.7 seconds
Started	Jan 14 01:13:46 PM PST 24
Finished	Jan 14 01:13:48 PM PST 24
Peak memory	202840 kb
Host	smart-b613271f-293e-428d-a6d0-3a8681872c58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759028256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.759028256
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2092903012
Short name	T158
Test name
Test status
Simulation time	143729764 ps
CPU time	1.77 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:46 PM PST 24
Peak memory	202852 kb
Host	smart-f936c004-83b7-4a83-9b24-199cf7a4ec8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092903012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2092903012
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.630840885
Short name	T88
Test name
Test status
Simulation time	29492114 ps
CPU time	0.72 seconds
Started	Jan 14 01:13:59 PM PST 24
Finished	Jan 14 01:14:00 PM PST 24
Peak memory	202828 kb
Host	smart-a7a7bf68-c8c4-4448-b721-e15ee5e9fa03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630840885 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.630840885
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3405708655
Short name	T132
Test name
Test status
Simulation time	22285852 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:57 PM PST 24
Finished	Jan 14 01:13:58 PM PST 24
Peak memory	202688 kb
Host	smart-33b1b9c1-8e2d-42cb-bf0c-ce2ed3014711
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405708655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3405708655
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.185143674
Short name	T82
Test name
Test status
Simulation time	14466663 ps
CPU time	0.62 seconds
Started	Jan 14 01:14:02 PM PST 24
Finished	Jan 14 01:14:04 PM PST 24
Peak memory	202680 kb
Host	smart-f67962d1-4794-4e59-bbeb-30564faf9cdb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185143674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.185143674
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.337364164
Short name	T95
Test name
Test status
Simulation time	239713107 ps
CPU time	1.44 seconds
Started	Jan 14 01:13:48 PM PST 24
Finished	Jan 14 01:13:51 PM PST 24
Peak memory	203028 kb
Host	smart-14c7ad3d-a338-4ec3-9d36-bf66a4b29909
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337364164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.337364164
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1399501091
Short name	T135
Test name
Test status
Simulation time	111383943 ps
CPU time	1.88 seconds
Started	Jan 14 01:13:59 PM PST 24
Finished	Jan 14 01:14:02 PM PST 24
Peak memory	202964 kb
Host	smart-d2ceda85-26d6-4eff-8d5c-138b9ca4b919
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399501091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1399501091
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2323917546
Short name	T22
Test name
Test status
Simulation time	73359117 ps
CPU time	0.95 seconds
Started	Jan 14 01:13:29 PM PST 24
Finished	Jan 14 01:13:31 PM PST 24
Peak memory	202684 kb
Host	smart-693ccf0c-21cd-4e17-89b7-ede99a74dede
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323917546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2323917546
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1395448693
Short name	T36
Test name
Test status
Simulation time	54178670 ps
CPU time	2.14 seconds
Started	Jan 14 01:13:26 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202932 kb
Host	smart-bf909a86-6538-44fc-95ce-40fa36fabac4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395448693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1395448693
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1055144788
Short name	T41
Test name
Test status
Simulation time	151926742 ps
CPU time	0.63 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:29 PM PST 24
Peak memory	201568 kb
Host	smart-70e4d150-f9a6-40d1-83fd-63912aaa086d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055144788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1055144788
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3640265291
Short name	T5
Test name
Test status
Simulation time	56330924 ps
CPU time	0.87 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202844 kb
Host	smart-7b2d72b4-0905-486f-888e-c36e0fb8aa40
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640265291 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3640265291
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1188452638
Short name	T121
Test name
Test status
Simulation time	53194748 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:28 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202708 kb
Host	smart-0ef1d0cf-c430-40a9-9962-5f436f3928db
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188452638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1188452638
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.3012966344
Short name	T123
Test name
Test status
Simulation time	20031832 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:21 PM PST 24
Finished	Jan 14 01:13:23 PM PST 24
Peak memory	202568 kb
Host	smart-777667e1-7b35-4de8-a47a-7b5d0e3859e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012966344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3012966344
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3829074163
Short name	T153
Test name
Test status
Simulation time	88772530 ps
CPU time	0.84 seconds
Started	Jan 14 01:13:30 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	202744 kb
Host	smart-35962eaa-9f58-4ec9-9793-8e01b3000e51
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829074163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.3829074163
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1768685062
Short name	T134
Test name
Test status
Simulation time	30473532 ps
CPU time	1.3 seconds
Started	Jan 14 01:13:23 PM PST 24
Finished	Jan 14 01:13:25 PM PST 24
Peak memory	202868 kb
Host	smart-c7729450-9df4-4806-8efc-5f41c2445d2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768685062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1768685062
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2521772564
Short name	T58
Test name
Test status
Simulation time	426435638 ps
CPU time	1.37 seconds
Started	Jan 14 01:13:25 PM PST 24
Finished	Jan 14 01:13:28 PM PST 24
Peak memory	202960 kb
Host	smart-cab82ff5-4f6b-4b28-b9e1-317832108140
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521772564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2521772564
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.1474796938
Short name	T122
Test name
Test status
Simulation time	61423399 ps
CPU time	0.68 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:02 PM PST 24
Peak memory	202536 kb
Host	smart-c3cc9d7c-6e7b-428d-b6eb-8e9e0a9835b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474796938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1474796938
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3802023340
Short name	T160
Test name
Test status
Simulation time	72446097 ps
CPU time	0.69 seconds
Started	Jan 14 01:13:51 PM PST 24
Finished	Jan 14 01:13:52 PM PST 24
Peak memory	202772 kb
Host	smart-9012a18d-37db-42b9-9457-03e671fe920f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802023340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3802023340
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.457146282
Short name	T103
Test name
Test status
Simulation time	31075423 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:48 PM PST 24
Finished	Jan 14 01:13:49 PM PST 24
Peak memory	202752 kb
Host	smart-b17e549a-c52a-49e1-8db9-0804634715c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457146282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.457146282
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.148985722
Short name	T85
Test name
Test status
Simulation time	28430566 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:58 PM PST 24
Finished	Jan 14 01:13:59 PM PST 24
Peak memory	202624 kb
Host	smart-6a333282-0246-4fe9-b3ab-4fc101992617
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148985722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.148985722
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.372946968
Short name	T145
Test name
Test status
Simulation time	40878290 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:57 PM PST 24
Finished	Jan 14 01:13:59 PM PST 24
Peak memory	202636 kb
Host	smart-fa0f71eb-0eff-411b-b60b-5bf32800d98e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372946968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.372946968
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.856238711
Short name	T77
Test name
Test status
Simulation time	36132094 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:59 PM PST 24
Finished	Jan 14 01:14:01 PM PST 24
Peak memory	202564 kb
Host	smart-b1a0a8a8-7ab9-44b7-bf41-dbe56408aa37
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856238711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.856238711
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.270822568
Short name	T139
Test name
Test status
Simulation time	20387442 ps
CPU time	0.74 seconds
Started	Jan 14 01:14:01 PM PST 24
Finished	Jan 14 01:14:03 PM PST 24
Peak memory	202692 kb
Host	smart-732c2e45-b80c-41ad-8e8a-38d3ac8f5696
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270822568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.270822568
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.3888602464
Short name	T8
Test name
Test status
Simulation time	22030285 ps
CPU time	0.63 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:05 PM PST 24
Peak memory	202692 kb
Host	smart-6501b685-1d2e-429b-b89a-6fd9637c3e55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888602464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3888602464
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.3108776880
Short name	T87
Test name
Test status
Simulation time	91476479 ps
CPU time	0.62 seconds
Started	Jan 14 01:13:58 PM PST 24
Finished	Jan 14 01:13:59 PM PST 24
Peak memory	202628 kb
Host	smart-0bacd255-e909-4d51-8305-20c27b28b434
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108776880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3108776880
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.1806352212
Short name	T81
Test name
Test status
Simulation time	18157866 ps
CPU time	0.66 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:01 PM PST 24
Peak memory	202568 kb
Host	smart-7ba5c1ab-6cff-42dd-b0e2-05d3c1a63acf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806352212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1806352212
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.422140677
Short name	T37
Test name
Test status
Simulation time	30441159 ps
CPU time	1.27 seconds
Started	Jan 14 01:13:26 PM PST 24
Finished	Jan 14 01:13:28 PM PST 24
Peak memory	202940 kb
Host	smart-0c62e64c-e703-44b7-852c-6f330eabc022
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422140677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.422140677
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1284110995
Short name	T24
Test name
Test status
Simulation time	587026901 ps
CPU time	4.29 seconds
Started	Jan 14 01:13:29 PM PST 24
Finished	Jan 14 01:13:35 PM PST 24
Peak memory	202880 kb
Host	smart-90812a23-a65d-4978-9697-480ee38e840e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284110995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1284110995
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2540471803
Short name	T73
Test name
Test status
Simulation time	57216754 ps
CPU time	0.74 seconds
Started	Jan 14 01:13:28 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202472 kb
Host	smart-75ad6032-3c94-40f4-9589-b98d5931511f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540471803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2540471803
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2793052206
Short name	T66
Test name
Test status
Simulation time	30925461 ps
CPU time	0.79 seconds
Started	Jan 14 01:13:28 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202888 kb
Host	smart-2154404f-6b1a-47f9-b83b-2b813365dfda
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793052206 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2793052206
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.4165434502
Short name	T144
Test name
Test status
Simulation time	27558371 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:25 PM PST 24
Finished	Jan 14 01:13:27 PM PST 24
Peak memory	202712 kb
Host	smart-24f1c99c-7c14-484e-8705-66633299fe05
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165434502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.4165434502
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.3382105144
Short name	T101
Test name
Test status
Simulation time	50118702 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:26 PM PST 24
Finished	Jan 14 01:13:28 PM PST 24
Peak memory	202668 kb
Host	smart-8eabd646-814f-4307-abea-cdaee204ccca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382105144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3382105144
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3912993341
Short name	T107
Test name
Test status
Simulation time	55007985 ps
CPU time	1.05 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202856 kb
Host	smart-2803111f-0c89-4307-8331-f1e42bcaa0b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912993341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.3912993341
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2456425392
Short name	T15
Test name
Test status
Simulation time	49471795 ps
CPU time	2.43 seconds
Started	Jan 14 01:13:30 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	203000 kb
Host	smart-d989f864-0e10-4b5b-b22b-f238b49ee0ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456425392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2456425392
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1752922983
Short name	T61
Test name
Test status
Simulation time	80554429 ps
CPU time	1.75 seconds
Started	Jan 14 01:13:26 PM PST 24
Finished	Jan 14 01:13:29 PM PST 24
Peak memory	202908 kb
Host	smart-58ff81e8-4ef1-404f-babd-349fe2e353a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752922983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1752922983
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1726714826
Short name	T164
Test name
Test status
Simulation time	45682886 ps
CPU time	0.67 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:05 PM PST 24
Peak memory	202732 kb
Host	smart-f33bf0db-2075-4a1b-95d2-e776d77f926e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726714826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1726714826
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.2588988851
Short name	T142
Test name
Test status
Simulation time	21883552 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:56 PM PST 24
Finished	Jan 14 01:13:57 PM PST 24
Peak memory	202628 kb
Host	smart-ec1bc4a9-4b95-4169-8ff8-46cb0e1ac4b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588988851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2588988851
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.483889335
Short name	T130
Test name
Test status
Simulation time	38215644 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:47 PM PST 24
Finished	Jan 14 01:13:48 PM PST 24
Peak memory	202620 kb
Host	smart-5db4740c-d3bb-4d17-8755-39bf6cd47ed6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483889335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.483889335
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.2282351312
Short name	T138
Test name
Test status
Simulation time	16774901 ps
CPU time	0.67 seconds
Started	Jan 14 01:14:02 PM PST 24
Finished	Jan 14 01:14:04 PM PST 24
Peak memory	202692 kb
Host	smart-b2781eb6-1e6b-40d5-919f-ce8d1cd7b5c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282351312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2282351312
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.3141439078
Short name	T76
Test name
Test status
Simulation time	34958817 ps
CPU time	0.63 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:06 PM PST 24
Peak memory	202680 kb
Host	smart-bfb8ed7c-29f7-4f52-9958-0cb2d64e939e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141439078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3141439078
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.4022670392
Short name	T128
Test name
Test status
Simulation time	21722138 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:49 PM PST 24
Finished	Jan 14 01:13:50 PM PST 24
Peak memory	202652 kb
Host	smart-202ae7fa-4e22-4d97-84ca-a7741970de89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022670392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.4022670392
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.467208963
Short name	T43
Test name
Test status
Simulation time	18033368 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:55 PM PST 24
Finished	Jan 14 01:13:56 PM PST 24
Peak memory	202736 kb
Host	smart-9690267c-916e-4f02-af72-8c40b7d96f2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467208963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.467208963
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.191938143
Short name	T163
Test name
Test status
Simulation time	75010722 ps
CPU time	0.68 seconds
Started	Jan 14 01:14:02 PM PST 24
Finished	Jan 14 01:14:05 PM PST 24
Peak memory	202688 kb
Host	smart-e4617cd2-bb44-42a6-86e9-ca65ea8ae7e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191938143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.191938143
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2536134660
Short name	T27
Test name
Test status
Simulation time	127721976 ps
CPU time	0.97 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:29 PM PST 24
Peak memory	202680 kb
Host	smart-99128287-12a3-48c0-960f-d3b7d5a4a01d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536134660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2536134660
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.878044353
Short name	T31
Test name
Test status
Simulation time	355139419 ps
CPU time	3.56 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	203000 kb
Host	smart-edaa2324-37b5-401c-b8f4-ad712c539e2b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878044353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.878044353
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4046532479
Short name	T25
Test name
Test status
Simulation time	22597049 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202816 kb
Host	smart-acd82bed-8ae1-4728-a177-1c76d67ebe68
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046532479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.4046532479
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3041599321
Short name	T131
Test name
Test status
Simulation time	93682056 ps
CPU time	1.45 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	203036 kb
Host	smart-813e4225-5b9f-4fac-9adb-ea89e01d1db1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041599321 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3041599321
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.533340717
Short name	T71
Test name
Test status
Simulation time	32766857 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202728 kb
Host	smart-01757445-aeeb-4b21-b60c-9780787b7832
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533340717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.533340717
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.2077735621
Short name	T108
Test name
Test status
Simulation time	16468706 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:30 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	202644 kb
Host	smart-e980453c-a02c-4f8e-bb20-e604341b9300
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077735621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2077735621
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2776241441
Short name	T120
Test name
Test status
Simulation time	21938647 ps
CPU time	0.78 seconds
Started	Jan 14 01:13:33 PM PST 24
Finished	Jan 14 01:13:35 PM PST 24
Peak memory	202772 kb
Host	smart-0352ac7c-1d21-468a-8e71-8cb09457f0a0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776241441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.2776241441
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2663588004
Short name	T46
Test name
Test status
Simulation time	42440833 ps
CPU time	1.5 seconds
Started	Jan 14 01:13:28 PM PST 24
Finished	Jan 14 01:13:31 PM PST 24
Peak memory	202652 kb
Host	smart-bbac3c89-8182-4059-8749-08caa7df68f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663588004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2663588004
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3737721075
Short name	T3
Test name
Test status
Simulation time	492813490 ps
CPU time	1.2 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202960 kb
Host	smart-4858c707-6a5a-476d-a6db-339e8a8324cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737721075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3737721075
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.2487332857
Short name	T10
Test name
Test status
Simulation time	18402385 ps
CPU time	0.71 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:02 PM PST 24
Peak memory	202544 kb
Host	smart-a75c2aff-c768-4166-971e-ffd64b6c3231
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487332857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2487332857
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.2766306589
Short name	T117
Test name
Test status
Simulation time	17074485 ps
CPU time	0.63 seconds
Started	Jan 14 01:13:49 PM PST 24
Finished	Jan 14 01:13:50 PM PST 24
Peak memory	202676 kb
Host	smart-c0279ca8-06e1-4501-8952-2980edb4460e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766306589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2766306589
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.2237064294
Short name	T68
Test name
Test status
Simulation time	21481884 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:56 PM PST 24
Finished	Jan 14 01:13:57 PM PST 24
Peak memory	202624 kb
Host	smart-697503d5-9941-4d0d-9f62-db17821512f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237064294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2237064294
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3841947258
Short name	T147
Test name
Test status
Simulation time	32359654 ps
CPU time	0.61 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:05 PM PST 24
Peak memory	202672 kb
Host	smart-a3d3aea7-5c98-481a-8b3c-b065bf91a208
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841947258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3841947258
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.2882977395
Short name	T86
Test name
Test status
Simulation time	47858317 ps
CPU time	0.66 seconds
Started	Jan 14 01:14:03 PM PST 24
Finished	Jan 14 01:14:06 PM PST 24
Peak memory	202680 kb
Host	smart-f19b423c-3478-40d5-b128-d8372d5d50ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882977395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2882977395
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.3914965248
Short name	T161
Test name
Test status
Simulation time	23968854 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:52 PM PST 24
Finished	Jan 14 01:13:53 PM PST 24
Peak memory	202592 kb
Host	smart-272ea0b2-e60c-4bae-9f6e-5130aca43056
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914965248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3914965248
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.3187111201
Short name	T140
Test name
Test status
Simulation time	45626900 ps
CPU time	0.66 seconds
Started	Jan 14 01:14:00 PM PST 24
Finished	Jan 14 01:14:01 PM PST 24
Peak memory	202684 kb
Host	smart-53527e23-79be-457e-8951-052bfc7aa404
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187111201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3187111201
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.2712960374
Short name	T110
Test name
Test status
Simulation time	18366517 ps
CPU time	0.71 seconds
Started	Jan 14 01:13:56 PM PST 24
Finished	Jan 14 01:13:57 PM PST 24
Peak memory	202644 kb
Host	smart-23ad1cc3-97d5-4343-991a-83d62e4792c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712960374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2712960374
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.3898036392
Short name	T115
Test name
Test status
Simulation time	17256754 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:53 PM PST 24
Finished	Jan 14 01:13:54 PM PST 24
Peak memory	202648 kb
Host	smart-e2519b40-cb09-4987-a169-6581dc104e49
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898036392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3898036392
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.1588037170
Short name	T114
Test name
Test status
Simulation time	28307312 ps
CPU time	0.7 seconds
Started	Jan 14 01:13:48 PM PST 24
Finished	Jan 14 01:13:49 PM PST 24
Peak memory	202676 kb
Host	smart-cc4f9d57-f081-4f99-9190-280374f604e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588037170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1588037170
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3731431666
Short name	T89
Test name
Test status
Simulation time	18209762 ps
CPU time	0.81 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202848 kb
Host	smart-ed3eb066-4dd4-4da7-9512-6ba23d7ce64d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731431666 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3731431666
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.1749116411
Short name	T26
Test name
Test status
Simulation time	54934108 ps
CPU time	0.66 seconds
Started	Jan 14 01:13:32 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	202052 kb
Host	smart-276a9a75-126d-4822-a3a4-7fe0de584211
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749116411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1749116411
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.826121563
Short name	T155
Test name
Test status
Simulation time	36158833 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:30 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	202680 kb
Host	smart-6b8cdf76-57a1-4e94-9c2c-ec62068efc48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826121563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.826121563
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4201370158
Short name	T96
Test name
Test status
Simulation time	60961849 ps
CPU time	0.78 seconds
Started	Jan 14 01:13:29 PM PST 24
Finished	Jan 14 01:13:31 PM PST 24
Peak memory	202648 kb
Host	smart-8ef3c11d-8522-4828-9880-d9b38495f9f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201370158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.4201370158
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3376767433
Short name	T148
Test name
Test status
Simulation time	74358930 ps
CPU time	1.93 seconds
Started	Jan 14 01:13:27 PM PST 24
Finished	Jan 14 01:13:31 PM PST 24
Peak memory	202880 kb
Host	smart-de862ba8-0571-4abb-8ca1-424f04e6b1a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376767433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3376767433
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4234053052
Short name	T62
Test name
Test status
Simulation time	83822744 ps
CPU time	1.81 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	202968 kb
Host	smart-eb96e5fa-dd2e-4fd8-875f-51ec2f567e43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234053052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4234053052
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.924883497
Short name	T125
Test name
Test status
Simulation time	33987673 ps
CPU time	1.04 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202816 kb
Host	smart-00fb5bf3-e5ce-45ed-b27f-f06c206e2b8d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924883497 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.924883497
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2436336727
Short name	T109
Test name
Test status
Simulation time	137942516 ps
CPU time	0.69 seconds
Started	Jan 14 01:13:30 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	202660 kb
Host	smart-0d1c2fb7-42db-47d8-b2b8-6f31fb993f6d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436336727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2436336727
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1396243086
Short name	T11
Test name
Test status
Simulation time	38065732 ps
CPU time	0.64 seconds
Started	Jan 14 01:13:29 PM PST 24
Finished	Jan 14 01:13:31 PM PST 24
Peak memory	202644 kb
Host	smart-422da641-7804-47ce-8d9e-cc2e1a210406
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396243086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1396243086
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3599084672
Short name	T6
Test name
Test status
Simulation time	21831137 ps
CPU time	0.81 seconds
Started	Jan 14 01:13:28 PM PST 24
Finished	Jan 14 01:13:30 PM PST 24
Peak memory	202720 kb
Host	smart-be4541b3-ba3f-489e-b380-0f94f31150b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599084672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.3599084672
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2842410501
Short name	T21
Test name
Test status
Simulation time	480165793 ps
CPU time	1.91 seconds
Started	Jan 14 01:13:29 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	202844 kb
Host	smart-0fadf907-da5a-4c38-ad87-4d56e49b905f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842410501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2842410501
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4234328225
Short name	T64
Test name
Test status
Simulation time	106978311 ps
CPU time	1.21 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202896 kb
Host	smart-1a2b792d-4ed0-42f6-936c-0bb8661f03b1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234328225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4234328225
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1712544967
Short name	T157
Test name
Test status
Simulation time	51953234 ps
CPU time	0.96 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	202736 kb
Host	smart-4535fe5c-da1b-414f-8b26-6f6e81fcb81d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712544967 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1712544967
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.2428240833
Short name	T126
Test name
Test status
Simulation time	42526001 ps
CPU time	0.65 seconds
Started	Jan 14 01:13:31 PM PST 24
Finished	Jan 14 01:13:33 PM PST 24
Peak memory	202716 kb
Host	smart-8dade296-1ca8-4739-be15-8b723b6f04d9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428240833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2428240833
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.1650520989
Short name	T105
Test name
Test status
Simulation time	17953211 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:29 PM PST 24
Finished	Jan 14 01:13:31 PM PST 24
Peak memory	202768 kb
Host	smart-b14cd955-4ee8-460e-9968-42766f2ee52e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650520989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1650520989
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1538475606
Short name	T52
Test name
Test status
Simulation time	79071549 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:30 PM PST 24
Finished	Jan 14 01:13:32 PM PST 24
Peak memory	202616 kb
Host	smart-6e46630e-f8a1-4da6-8b56-01d8aaa87d17
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538475606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.1538475606
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.2378058508
Short name	T100
Test name
Test status
Simulation time	56708372 ps
CPU time	1.52 seconds
Started	Jan 14 01:13:33 PM PST 24
Finished	Jan 14 01:13:35 PM PST 24
Peak memory	203016 kb
Host	smart-5ac7449b-b76d-4890-8d86-0f53ba6e2bba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378058508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2378058508
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1859886768
Short name	T59
Test name
Test status
Simulation time	124267224 ps
CPU time	1.93 seconds
Started	Jan 14 01:13:33 PM PST 24
Finished	Jan 14 01:13:36 PM PST 24
Peak memory	202988 kb
Host	smart-69eb9e62-786d-484a-a400-4a324d4cfa86
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859886768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1859886768
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.778213003
Short name	T14
Test name
Test status
Simulation time	68280356 ps
CPU time	0.89 seconds
Started	Jan 14 01:13:38 PM PST 24
Finished	Jan 14 01:13:39 PM PST 24
Peak memory	202852 kb
Host	smart-51fd1a12-f406-4143-9706-1554d936a07b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778213003 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.778213003
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.674179309
Short name	T159
Test name
Test status
Simulation time	18517010 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:33 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	202132 kb
Host	smart-a7ef3038-2a74-4303-85ff-615b21543f1b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674179309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.674179309
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1542396111
Short name	T28
Test name
Test status
Simulation time	84708192 ps
CPU time	0.76 seconds
Started	Jan 14 01:13:32 PM PST 24
Finished	Jan 14 01:13:34 PM PST 24
Peak memory	202640 kb
Host	smart-85341ba7-f624-4ff0-a5e9-ece82ae13e44
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542396111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.1542396111
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.3454840941
Short name	T129
Test name
Test status
Simulation time	220403774 ps
CPU time	2.6 seconds
Started	Jan 14 01:13:38 PM PST 24
Finished	Jan 14 01:13:42 PM PST 24
Peak memory	202964 kb
Host	smart-9c60ea8e-4b8b-451f-9c56-243b03b08796
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454840941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3454840941
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.33801980
Short name	T93
Test name
Test status
Simulation time	21519018 ps
CPU time	0.73 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:45 PM PST 24
Peak memory	202848 kb
Host	smart-7cd8b314-528d-4177-a541-4c881b592fb6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801980 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.33801980
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.3374826305
Short name	T33
Test name
Test status
Simulation time	162702364 ps
CPU time	0.68 seconds
Started	Jan 14 01:13:44 PM PST 24
Finished	Jan 14 01:13:45 PM PST 24
Peak memory	202680 kb
Host	smart-6e5387fa-723b-4c8d-b610-9587c434f1bc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374826305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3374826305
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2161443741
Short name	T136
Test name
Test status
Simulation time	18851249 ps
CPU time	0.67 seconds
Started	Jan 14 01:13:34 PM PST 24
Finished	Jan 14 01:13:35 PM PST 24
Peak memory	202664 kb
Host	smart-073933cd-c587-4408-bcb4-0aea54c38d89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161443741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2161443741
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4185273004
Short name	T162
Test name
Test status
Simulation time	40497879 ps
CPU time	0.95 seconds
Started	Jan 14 01:13:37 PM PST 24
Finished	Jan 14 01:13:39 PM PST 24
Peak memory	202752 kb
Host	smart-eed43598-2cbe-4b55-a42c-beb1cac89928
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185273004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.4185273004
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3819161478
Short name	T92
Test name
Test status
Simulation time	128952023 ps
CPU time	1.53 seconds
Started	Jan 14 01:13:36 PM PST 24
Finished	Jan 14 01:13:38 PM PST 24
Peak memory	202964 kb
Host	smart-3f7eb11a-59d2-4b02-8afe-99ad3a45e8d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819161478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3819161478
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2035174069
Short name	T74
Test name
Test status
Simulation time	186840349 ps
CPU time	1.86 seconds
Started	Jan 14 01:13:39 PM PST 24
Finished	Jan 14 01:13:41 PM PST 24
Peak memory	202848 kb
Host	smart-5a5470a0-ba57-41e2-9907-de23bc21da5c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035174069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2035174069
Directory	/workspace/9.i2c_tl_intg_err/latest