Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

244675

1

T1

832

T2

1088

T3

202

ack

20136

1

T1

26

T2

34

T3

16

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	965	1			T1	2		T2	3		T10	3
high	54129	1			T1	176		T2	234		T3	61
med	98808	1			T1	344		T2	433		T3	73
sml	109925	1			T1	332		T2	448		T3	83
all_zero	984	1			T1	4		T2	4		T3	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132207

1

T1

429

T2

545

T3

108

auto[1]

132604

1

T1

429

T2

577

T3

110

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181220

1

T1

599

T2

721

T3

153

auto[1]

83591

1

T1

259

T2

401

T3

65

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253356

1

T1

846

T2

1106

T3

218

auto[1]

11455

1

T1

12

T2

16

T10

5

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249948

1

T1

833

T2

1089

T3

202

auto[1]

14863

1

T1

25

T2

33

T3

16

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

251853

1

T1

834

T2

1090

T3

202

auto[1]

12958

1

T1

24

T2

32

T3

16

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132207

1

T1

429

T2

545

T3

108

auto[1]

132604

1

T1

429

T2

577

T3

110

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181220

1

T1

599

T2

721

T3

153

auto[1]

83591

1

T1

259

T2

401

T3

65

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253356

1

T1

846

T2

1106

T3

218

auto[1]

11455

1

T1

12

T2

16

T10

5

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249948

1

T1

833

T2

1089

T3

202

auto[1]

14863

1

T1

25

T2

33

T3

16

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

251853

1

T1

834

T2

1090

T3

202

auto[1]

12958

1

T1

24

T2

32

T3

16

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T187

1

T188

1

T189

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T190

1

T191

1

T108

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T192

1

T193

1

T189

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

642

1

T1

1

T2

2

T10

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

339

1

T1

1

T2

2

T37

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

315

1

T74

1

T76

1

T194

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1226

1

T1

3

T2

3

T10

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

608

1

T2

4

T37

4

T75

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

577

1

T2

2

T10

1

T37

7

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1180

1

T1

3

T2

2

T10

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

571

1

T1

2

T2

2

T37

6

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

635

1

T1

3

T2

2

T37

4

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

27

1

T12

1

T144

1

T195

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

9

1

T196

1

T192

1

T197

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T193

1

T198

1

T199

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	77432	1			T1	276		T2	311		T3	63
write_address_byte	14863	1			T1	25		T2	33		T3	16
read_with_ack	3954	1			T10	2		T37	42		T14	9
read_with_nack	7501	1			T1	12		T2	16		T10	3
stop_byte	12958	1			T1	24		T2	32		T3	16
write_address_byte_nak	9728	1			T1	22		T2	30		T10	9
data_byte_nack	244675	1			T1	832		T2	1088		T3	202
stop_byte_nack	9363	1			T1	21		T2	29		T3	16
nakok_byte_nack	122572	1			T1	415		T2	564		T3	105
nakok_addr_byte_nack	4827	1			T1	14		T2	14		T10	5