Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51903272	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17422779

1

T18

121

T19

100

T20

356

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	61134566	1			T18	81		T19	72		T20	641
values[0x0]	4093745	1			T18	47		T19	41		T20	27
values[0x1]	4097740	1			T18	43		T19	48		T20	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38148980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31177071

1

T18

135

T19

117

T20

420

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	262976	1			T18	2		T20	3		T78	6
valid_sources[0x01]	212251	1			T20	2		T23	4		T77	2
valid_sources[0x02]	240770	1			T20	6		T23	3		T25	1
valid_sources[0x03]	1108709	1			T20	1		T21	1		T23	1
valid_sources[0x04]	263552	1			T19	9		T20	3		T23	1
valid_sources[0x05]	261452	1			T18	1		T20	3		T25	1
valid_sources[0x06]	232649	1			T20	5		T23	6		T77	1
valid_sources[0x07]	223675	1			T19	4		T20	3		T25	2
valid_sources[0x08]	223189	1			T20	5		T77	1		T78	3
valid_sources[0x09]	231139	1			T20	1		T23	3		T25	2
valid_sources[0x0a]	224883	1			T23	5		T77	1		T78	3
valid_sources[0x0b]	202585	1			T20	1		T23	2		T77	1
valid_sources[0x0c]	253747	1			T20	7		T25	2		T77	3
valid_sources[0x0d]	320226	1			T20	3		T25	1		T77	3
valid_sources[0x0e]	226469	1			T20	2		T78	3		T82	2
valid_sources[0x0f]	270354	1			T20	2		T23	17		T25	3
valid_sources[0x10]	232447	1			T20	3		T23	2		T25	3
valid_sources[0x11]	221865	1			T20	6		T21	1		T23	4
valid_sources[0x12]	241380	1			T19	5		T20	4		T77	1
valid_sources[0x13]	284463	1			T20	5		T23	8		T78	7
valid_sources[0x14]	229176	1			T20	1		T23	3		T78	5
valid_sources[0x15]	309625	1			T19	3		T20	1		T23	2
valid_sources[0x16]	219374	1			T20	4		T21	1		T78	3
valid_sources[0x17]	231016	1			T18	2		T20	5		T23	2
valid_sources[0x18]	221707	1			T18	1		T20	5		T23	3
valid_sources[0x19]	235859	1			T18	1		T20	1		T23	4
valid_sources[0x1a]	233423	1			T18	1		T20	2		T23	5
valid_sources[0x1b]	253261	1			T19	5		T20	2		T23	6
valid_sources[0x1c]	232376	1			T20	2		T23	2		T25	5
valid_sources[0x1d]	218205	1			T20	2		T77	2		T78	2
valid_sources[0x1e]	216419	1			T18	2		T20	2		T23	3
valid_sources[0x1f]	220426	1			T18	2		T20	4		T23	5
valid_sources[0x20]	223880	1			T18	1		T23	1		T77	2
valid_sources[0x21]	240128	1			T18	1		T20	1		T23	1
valid_sources[0x22]	216871	1			T20	3		T22	3		T23	7
valid_sources[0x23]	225727	1			T20	5		T25	4		T77	2
valid_sources[0x24]	212283	1			T21	2		T23	9		T82	1
valid_sources[0x25]	212938	1			T19	3		T20	6		T78	4
valid_sources[0x26]	226865	1			T18	3		T20	2		T25	1
valid_sources[0x27]	223096	1			T18	5		T20	3		T23	9
valid_sources[0x28]	257124	1			T20	7		T23	3		T25	2
valid_sources[0x29]	229342	1			T18	3		T20	2		T25	2
valid_sources[0x2a]	216807	1			T18	1		T20	2		T23	8
valid_sources[0x2b]	235052	1			T23	3		T24	38		T77	1
valid_sources[0x2c]	242241	1			T20	3		T23	9		T25	3
valid_sources[0x2d]	239594	1			T20	3		T23	5		T25	1
valid_sources[0x2e]	241302	1			T18	1		T20	2		T23	1
valid_sources[0x2f]	227204	1			T20	3		T21	2		T78	7
valid_sources[0x30]	228633	1			T18	1		T20	1		T23	1
valid_sources[0x31]	227005	1			T20	1		T23	4		T77	1
valid_sources[0x32]	266221	1			T18	1		T20	8		T22	5
valid_sources[0x33]	242920	1			T18	1		T20	1		T21	1
valid_sources[0x34]	1190523	1			T20	10		T23	7		T77	1
valid_sources[0x35]	345030	1			T20	1		T23	7		T77	1
valid_sources[0x36]	216458	1			T18	1		T19	4		T20	4
valid_sources[0x37]	227289	1			T18	1		T20	2		T23	3
valid_sources[0x38]	233047	1			T20	3		T23	3		T25	5
valid_sources[0x39]	217215	1			T20	2		T21	1		T23	7
valid_sources[0x3a]	219767	1			T20	3		T23	1		T25	1
valid_sources[0x3b]	216325	1			T20	3		T21	1		T23	2
valid_sources[0x3c]	225039	1			T20	6		T23	3		T77	2
valid_sources[0x3d]	225099	1			T19	2		T20	3		T23	5
valid_sources[0x3e]	238809	1			T18	6		T20	7		T77	3
valid_sources[0x3f]	645841	1			T20	1		T21	1		T77	2
valid_sources[0x40]	214108	1			T18	1		T20	3		T23	6
valid_sources[0x41]	257374	1			T20	3		T23	22		T78	8
valid_sources[0x42]	231370	1			T23	4		T78	4		T82	6
valid_sources[0x43]	270730	1			T18	1		T20	1		T23	10
valid_sources[0x44]	229415	1			T20	5		T23	3		T78	2
valid_sources[0x45]	225195	1			T20	5		T23	2		T77	4
valid_sources[0x46]	241786	1			T18	1		T20	3		T77	1
valid_sources[0x47]	221863	1			T19	2		T20	1		T23	1
valid_sources[0x48]	234253	1			T20	3		T23	4		T26	1
valid_sources[0x49]	233588	1			T18	3		T20	2		T23	4
valid_sources[0x4a]	217176	1			T20	2		T23	3		T25	3
valid_sources[0x4b]	269867	1			T18	1		T20	3		T25	3
valid_sources[0x4c]	235114	1			T19	2		T20	4		T23	2
valid_sources[0x4d]	221086	1			T20	2		T78	3		T82	6
valid_sources[0x4e]	409494	1			T19	3		T20	1		T23	2
valid_sources[0x4f]	251070	1			T20	1		T23	5		T77	3
valid_sources[0x50]	207259	1			T20	2		T23	2		T77	1
valid_sources[0x51]	274039	1			T20	3		T25	1		T78	3
valid_sources[0x52]	321736	1			T18	2		T20	6		T23	2
valid_sources[0x53]	239981	1			T20	5		T23	2		T77	1
valid_sources[0x54]	265814	1			T20	3		T77	1		T78	3
valid_sources[0x55]	286754	1			T18	1		T20	1		T23	2
valid_sources[0x56]	216422	1			T19	7		T20	2		T23	1
valid_sources[0x57]	218314	1			T18	1		T23	2		T25	1
valid_sources[0x58]	263627	1			T19	1		T23	1		T78	5
valid_sources[0x59]	218750	1			T21	1		T23	5		T25	1
valid_sources[0x5a]	224331	1			T20	3		T23	2		T78	6
valid_sources[0x5b]	226516	1			T20	5		T77	2		T82	1
valid_sources[0x5c]	230708	1			T20	10		T23	3		T77	1
valid_sources[0x5d]	230004	1			T18	2		T20	3		T23	2
valid_sources[0x5e]	217380	1			T18	3		T20	4		T23	1
valid_sources[0x5f]	232890	1			T19	3		T20	2		T23	4
valid_sources[0x60]	248759	1			T20	3		T23	2		T25	5
valid_sources[0x61]	236056	1			T19	1		T20	8		T21	1
valid_sources[0x62]	211954	1			T20	3		T23	1		T77	2
valid_sources[0x63]	357608	1			T18	7		T20	2		T23	5
valid_sources[0x64]	234478	1			T19	2		T20	1		T23	1
valid_sources[0x65]	245567	1			T18	2		T20	1		T78	4
valid_sources[0x66]	218954	1			T18	3		T19	3		T20	2
valid_sources[0x67]	271378	1			T20	1		T23	1		T25	1
valid_sources[0x68]	211596	1			T18	1		T20	1		T23	3
valid_sources[0x69]	225314	1			T18	4		T20	7		T22	4
valid_sources[0x6a]	536285	1			T20	2		T23	3		T77	1
valid_sources[0x6b]	225134	1			T20	1		T23	5		T25	7
valid_sources[0x6c]	239444	1			T19	6		T20	3		T21	2
valid_sources[0x6d]	230423	1			T18	2		T20	2		T77	2
valid_sources[0x6e]	265854	1			T18	1		T20	3		T25	1
valid_sources[0x6f]	372334	1			T19	1		T20	4		T23	8
valid_sources[0x70]	214625	1			T20	4		T23	4		T77	1
valid_sources[0x71]	448325	1			T20	1		T25	1		T78	5
valid_sources[0x72]	284074	1			T18	1		T20	4		T23	1
valid_sources[0x73]	242068	1			T20	2		T25	1		T77	5
valid_sources[0x74]	234232	1			T20	4		T23	1		T25	1
valid_sources[0x75]	223337	1			T20	3		T23	3		T78	10
valid_sources[0x76]	245934	1			T20	2		T23	1		T25	2
valid_sources[0x77]	222087	1			T20	1		T77	2		T78	4
valid_sources[0x78]	231338	1			T20	1		T23	5		T24	37
valid_sources[0x79]	221316	1			T20	2		T23	5		T78	4
valid_sources[0x7a]	216900	1			T19	4		T20	1		T23	3
valid_sources[0x7b]	239224	1			T19	12		T20	3		T23	1
valid_sources[0x7c]	228379	1			T18	4		T20	4		T23	1
valid_sources[0x7d]	425656	1			T22	1		T77	2		T78	6
valid_sources[0x7e]	213983	1			T20	3		T23	1		T25	1
valid_sources[0x7f]	236614	1			T20	1		T23	7		T25	1
valid_sources[0x80]	214457	1			T19	1		T20	6		T78	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14299625

1

T18

44

T19

31

T20

326

values[0x0]

all_enables

biggest_size

2011935

1

T18

42

T19

36

T20

21

values[0x1]

all_enables

biggest_size

1111219

1

T18

35

T19

33

T20

9