Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

227099

1

T3

896

T9

462

T10

732

ack

18980

1

T3

28

T9

78

T10

22

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	894	1			T3	4		T9	2		T10	2
high	50161	1			T3	194		T9	88		T10	152
med	91769	1			T3	359		T9	185		T10	289
sml	102345	1			T3	365		T9	265		T10	309
all_zero	910	1			T3	2		T10	2		T37	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122957

1

T3

459

T9

255

T10

375

auto[1]

123122

1

T3

465

T9

285

T10

379

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168262

1

T3

635

T9

359

T10

501

auto[1]

77817

1

T3

289

T9

181

T10

253

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235052

1

T3

911

T9

449

T10

746

auto[1]

11027

1

T3

13

T9

91

T10

8

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232103

1

T3

897

T9

471

T10

737

auto[1]

13976

1

T3

27

T9

69

T10

17

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233866

1

T3

898

T9

486

T10

738

auto[1]

12213

1

T3

26

T9

54

T10

16

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122957

1

T3

459

T9

255

T10

375

auto[1]

123122

1

T3

465

T9

285

T10

379

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168262

1

T3

635

T9

359

T10

501

auto[1]

77817

1

T3

289

T9

181

T10

253

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235052

1

T3

911

T9

449

T10

746

auto[1]

11027

1

T3

13

T9

91

T10

8

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232103

1

T3

897

T9

471

T10

737

auto[1]

13976

1

T3

27

T9

69

T10

17

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233866

1

T3

898

T9

486

T10

738

auto[1]

12213

1

T3

26

T9

54

T10

16

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T175

1

T176

1

T177

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T111

1

T178

1

T179

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T180

1

T181

1

T182

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

606

1

T9

7

T10

4

T37

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

318

1

T3

1

T9

1

T10

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

286

1

T3

1

T10

1

T37

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1139

1

T3

2

T9

4

T10

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

594

1

T3

2

T9

3

T10

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

593

1

T9

2

T10

1

T37

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1129

1

T3

3

T9

7

T10

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

603

1

T3

1

T9

2

T10

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

584

1

T3

2

T9

6

T10

3

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T12

1

T183

1

T184

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

15

1

T185

1

T139

1

T186

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

11

1

T184

1

T187

1

T188

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	71603	1			T3	302		T9	120		T10	236
write_address_byte	13976	1			T3	27		T9	69		T10	17
read_with_ack	3866	1			T9	52		T37	59		T13	6
read_with_nack	7161	1			T3	13		T9	39		T10	8
stop_byte	12213	1			T3	26		T9	54		T10	16
write_address_byte_nak	9151	1			T3	24		T9	55		T10	16
data_byte_nack	227099	1			T3	896		T9	462		T10	732
stop_byte_nack	8846	1			T3	23		T9	41		T10	16
nakok_byte_nack	113675	1			T3	454		T9	248		T10	367
nakok_addr_byte_nack	4529	1			T3	12		T9	33		T10	10