Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51526705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18017073

1

T19

33

T20

48

T21

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	61159919	1			T19	59		T20	55		T21	11
values[0x0]	4190253	1			T19	19		T20	11		T21	3
values[0x1]	4193606	1			T19	18		T20	23		T21	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37937634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31606144

1

T19

56

T20

55

T21

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257355	1			T28	5		T119	14		T79	5
valid_sources[0x01]	262319	1			T28	1		T119	8		T123	2
valid_sources[0x02]	675425	1			T28	4		T119	14		T75	2
valid_sources[0x03]	252444	1			T28	2		T119	8		T79	5
valid_sources[0x04]	244503	1			T22	1		T28	2		T119	14
valid_sources[0x05]	239236	1			T28	2		T119	5		T122	8
valid_sources[0x06]	275822	1			T22	1		T28	1		T119	11
valid_sources[0x07]	261502	1			T19	1		T21	1		T22	1
valid_sources[0x08]	251047	1			T75	7		T123	2		T79	11
valid_sources[0x09]	230167	1			T21	1		T27	128		T28	1
valid_sources[0x0a]	276705	1			T22	1		T28	4		T119	19
valid_sources[0x0b]	257980	1			T22	1		T28	5		T119	11
valid_sources[0x0c]	273613	1			T21	1		T27	128		T28	2
valid_sources[0x0d]	228074	1			T28	4		T119	10		T79	1
valid_sources[0x0e]	243842	1			T19	1		T22	1		T28	3
valid_sources[0x0f]	242963	1			T28	3		T119	17		T66	2
valid_sources[0x10]	237113	1			T28	4		T119	10		T75	6
valid_sources[0x11]	271289	1			T22	1		T27	128		T28	2
valid_sources[0x12]	252484	1			T24	3		T28	2		T119	2
valid_sources[0x13]	288378	1			T19	1		T28	3		T119	6
valid_sources[0x14]	233038	1			T21	1		T28	3		T119	11
valid_sources[0x15]	251720	1			T28	4		T119	3		T79	4
valid_sources[0x16]	293856	1			T19	2		T22	1		T28	2
valid_sources[0x17]	260737	1			T28	4		T119	10		T66	1
valid_sources[0x18]	260327	1			T22	4		T119	6		T66	1
valid_sources[0x19]	255707	1			T19	4		T22	1		T27	128
valid_sources[0x1a]	255047	1			T19	1		T22	1		T28	3
valid_sources[0x1b]	236166	1			T119	3		T123	1		T79	5
valid_sources[0x1c]	247115	1			T28	6		T119	10		T75	1
valid_sources[0x1d]	243507	1			T28	2		T119	8		T79	3
valid_sources[0x1e]	245021	1			T28	3		T119	15		T66	1
valid_sources[0x1f]	272562	1			T23	1		T28	3		T119	1
valid_sources[0x20]	224904	1			T22	1		T28	2		T119	3
valid_sources[0x21]	244467	1			T119	20		T79	1		T1	103
valid_sources[0x22]	234161	1			T28	3		T119	2		T122	6
valid_sources[0x23]	509570	1			T21	1		T28	6		T119	7
valid_sources[0x24]	230001	1			T28	3		T119	7		T75	10
valid_sources[0x25]	257256	1			T21	1		T28	1		T75	11
valid_sources[0x26]	261416	1			T19	1		T22	1		T28	5
valid_sources[0x27]	231986	1			T28	3		T119	4		T123	2
valid_sources[0x28]	242730	1			T28	1		T119	5		T79	4
valid_sources[0x29]	549862	1			T27	128		T28	1		T119	5
valid_sources[0x2a]	266484	1			T19	2		T28	4		T122	1
valid_sources[0x2b]	263061	1			T28	1		T75	5		T79	8
valid_sources[0x2c]	246869	1			T22	1		T27	128		T28	4
valid_sources[0x2d]	235532	1			T19	2		T28	2		T119	3
valid_sources[0x2e]	256600	1			T19	1		T22	2		T28	1
valid_sources[0x2f]	294150	1			T28	2		T119	2		T75	1
valid_sources[0x30]	260149	1			T28	2		T119	7		T123	1
valid_sources[0x31]	252055	1			T22	1		T27	124		T119	8
valid_sources[0x32]	262543	1			T28	2		T119	6		T123	1
valid_sources[0x33]	240210	1			T27	128		T28	6		T119	1
valid_sources[0x34]	253857	1			T28	2		T119	9		T75	2
valid_sources[0x35]	251084	1			T28	3		T119	17		T67	2
valid_sources[0x36]	414006	1			T23	6		T28	3		T119	18
valid_sources[0x37]	245623	1			T28	2		T119	7		T122	14
valid_sources[0x38]	263106	1			T27	128		T28	3		T119	1
valid_sources[0x39]	250407	1			T28	3		T119	12		T79	4
valid_sources[0x3a]	248804	1			T28	9		T119	4		T75	8
valid_sources[0x3b]	244038	1			T21	1		T28	1		T119	18
valid_sources[0x3c]	248504	1			T21	1		T27	128		T119	1
valid_sources[0x3d]	257506	1			T24	2		T28	1		T119	6
valid_sources[0x3e]	246294	1			T28	5		T119	20		T66	2
valid_sources[0x3f]	233206	1			T21	1		T28	7		T119	12
valid_sources[0x40]	240526	1			T119	11		T75	22		T122	6
valid_sources[0x41]	262322	1			T20	4		T26	10		T27	256
valid_sources[0x42]	312999	1			T28	3		T119	10		T75	7
valid_sources[0x43]	255947	1			T22	1		T28	1		T119	8
valid_sources[0x44]	346440	1			T24	1		T28	1		T119	4
valid_sources[0x45]	248815	1			T28	3		T119	11		T79	4
valid_sources[0x46]	232800	1			T19	2		T28	4		T119	9
valid_sources[0x47]	255155	1			T27	128		T28	4		T119	1
valid_sources[0x48]	234534	1			T19	2		T24	4		T28	3
valid_sources[0x49]	240155	1			T28	5		T119	9		T79	8
valid_sources[0x4a]	244327	1			T119	3		T123	1		T79	5
valid_sources[0x4b]	267828	1			T19	2		T28	6		T119	19
valid_sources[0x4c]	242102	1			T28	4		T119	4		T75	13
valid_sources[0x4d]	237014	1			T79	2		T81	1		T1	107
valid_sources[0x4e]	243509	1			T19	1		T21	1		T28	5
valid_sources[0x4f]	237066	1			T21	1		T119	2		T79	6
valid_sources[0x50]	244919	1			T28	3		T119	3		T75	1
valid_sources[0x51]	335492	1			T22	1		T28	3		T119	6
valid_sources[0x52]	346509	1			T19	3		T28	4		T119	7
valid_sources[0x53]	240758	1			T28	2		T119	6		T123	2
valid_sources[0x54]	252910	1			T119	4		T122	3		T76	24
valid_sources[0x55]	245034	1			T27	128		T28	2		T119	10
valid_sources[0x56]	247720	1			T28	4		T119	1		T122	22
valid_sources[0x57]	265443	1			T26	10		T28	4		T119	1
valid_sources[0x58]	494643	1			T23	3		T28	2		T119	9
valid_sources[0x59]	247794	1			T21	1		T22	1		T27	127
valid_sources[0x5a]	283677	1			T28	1		T119	5		T66	1
valid_sources[0x5b]	250986	1			T28	2		T119	5		T75	8
valid_sources[0x5c]	258952	1			T21	1		T28	5		T119	17
valid_sources[0x5d]	275265	1			T21	1		T28	1		T119	23
valid_sources[0x5e]	261397	1			T19	1		T20	10		T28	4
valid_sources[0x5f]	250481	1			T28	4		T119	1		T79	5
valid_sources[0x60]	253757	1			T20	5		T28	3		T119	6
valid_sources[0x61]	237829	1			T19	1		T28	3		T119	19
valid_sources[0x62]	261536	1			T28	1		T119	5		T122	1
valid_sources[0x63]	234044	1			T28	6		T119	10		T66	3
valid_sources[0x64]	294613	1			T19	1		T27	128		T28	5
valid_sources[0x65]	250910	1			T28	2		T119	1		T75	10
valid_sources[0x66]	235848	1			T28	1		T119	8		T122	8
valid_sources[0x67]	233017	1			T119	7		T79	3		T78	21
valid_sources[0x68]	232200	1			T19	1		T22	1		T28	2
valid_sources[0x69]	232643	1			T28	8		T119	3		T79	6
valid_sources[0x6a]	233388	1			T28	1		T119	6		T123	1
valid_sources[0x6b]	273348	1			T28	4		T119	13		T79	3
valid_sources[0x6c]	225474	1			T19	6		T28	1		T119	11
valid_sources[0x6d]	245661	1			T21	1		T28	4		T119	4
valid_sources[0x6e]	245127	1			T28	4		T119	4		T122	6
valid_sources[0x6f]	234020	1			T27	128		T28	1		T119	1
valid_sources[0x70]	231420	1			T22	2		T28	5		T119	3
valid_sources[0x71]	486264	1			T22	1		T28	7		T119	6
valid_sources[0x72]	519473	1			T28	2		T119	6		T79	6
valid_sources[0x73]	261485	1			T20	2		T24	3		T28	5
valid_sources[0x74]	227855	1			T28	1		T119	8		T66	1
valid_sources[0x75]	265225	1			T22	1		T28	3		T119	5
valid_sources[0x76]	249829	1			T19	1		T28	2		T119	12
valid_sources[0x77]	248928	1			T28	4		T119	2		T75	16
valid_sources[0x78]	235680	1			T22	1		T28	2		T119	5
valid_sources[0x79]	233824	1			T22	1		T28	2		T119	3
valid_sources[0x7a]	248058	1			T28	2		T119	19		T122	2
valid_sources[0x7b]	261438	1			T22	2		T28	4		T119	13
valid_sources[0x7c]	233289	1			T28	1		T119	8		T79	4
valid_sources[0x7d]	247493	1			T28	2		T119	12		T79	2
valid_sources[0x7e]	239647	1			T28	2		T119	4		T79	10
valid_sources[0x7f]	240377	1			T119	10		T66	1		T123	1
valid_sources[0x80]	237870	1			T20	32		T28	3		T119	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14834616

1

T19

10

T20

24

T21

7

values[0x0]

all_enables

biggest_size

2050966

1

T19

11

T20

10

T21

1

values[0x1]

all_enables

biggest_size

1131491

1

T19

12

T20

14

T21

2