Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	556717872	54942	0	0
ctrl_rd_A	556717872	1768	0	0
fifo_ctrl_rd_A	556717872	3743	0	0
host_timeout_ctrl_rd_A	556717872	1396	0	0
intr_enable_rd_A	556717872	3361	0	0
ovrd_rd_A	556717872	2353	0	0
target_id_rd_A	556717872	1844	0	0
timeout_ctrl_rd_A	556717872	1528	0	0
timing0_rd_A	556717872	1757	0	0
timing1_rd_A	556717872	1560	0	0
timing2_rd_A	556717872	1840	0	0
timing3_rd_A	556717872	1606	0	0
timing4_rd_A	556717872	1581	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	54942	0	0
T20	1930	2	0	0
T21	1002	0	0	0
T22	2274	0	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	0	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T31	0	24865	0	0
T75	0	2	0	0
T76	0	3	0	0
T77	0	22	0	0
T78	0	30	0	0
T79	0	5	0	0
T81	0	457	0	0
T85	0	9246	0	0
T119	15085	0	0	0
T141	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1768	0	0
T19	1834	6	0	0
T20	1930	11	0	0
T21	1002	0	0	0
T22	2274	3	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	3	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	8	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	12	0	0
T116	0	10	0	0
T117	0	54	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	3743	0	0
T19	1834	16	0	0
T20	1930	14	0	0
T21	1002	0	0	0
T22	2274	9	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	10	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	10	0	0
T78	0	9	0	0
T80	0	1	0	0
T81	0	22	0	0
T116	0	6	0	0
T117	0	34	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1396	0	0
T19	1834	3	0	0
T20	1930	10	0	0
T21	1002	0	0	0
T22	2274	4	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	12	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	16	0	0
T78	0	3	0	0
T81	0	4	0	0
T86	0	352	0	0
T116	0	2	0	0
T117	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	3361	0	0
T19	1834	54	0	0
T20	1930	8	0	0
T21	1002	0	0	0
T22	2274	10	0	0
T23	1320	8	0	0
T24	587	0	0	0
T25	1324	17	0	0
T26	1564	11	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	29	0	0
T78	0	8	0	0
T80	0	8	0	0
T142	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	2353	0	0
T19	1834	18	0	0
T20	1930	9	0	0
T21	1002	0	0	0
T22	2274	9	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	6	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	12	0	0
T78	0	10	0	0
T81	0	11	0	0
T116	0	15	0	0
T117	0	42	0	0
T143	0	27	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1844	0	0
T19	1834	15	0	0
T20	1930	17	0	0
T21	1002	0	0	0
T22	2274	7	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	2	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	4	0	0
T78	0	1	0	0
T80	0	16	0	0
T81	0	2	0	0
T116	0	22	0	0
T117	0	31	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1528	0	0
T19	1834	11	0	0
T20	1930	16	0	0
T21	1002	0	0	0
T22	2274	9	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	2	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T78	0	17	0	0
T81	0	14	0	0
T86	0	412	0	0
T112	0	23	0	0
T116	0	6	0	0
T117	0	40	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1757	0	0
T19	1834	11	0	0
T20	1930	19	0	0
T21	1002	0	0	0
T22	2274	7	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	10	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	9	0	0
T78	0	13	0	0
T80	0	13	0	0
T81	0	25	0	0
T116	0	9	0	0
T117	0	49	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1560	0	0
T19	1834	7	0	0
T20	1930	27	0	0
T21	1002	0	0	0
T22	2274	12	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	6	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	9	0	0
T78	0	7	0	0
T80	0	13	0	0
T86	0	437	0	0
T116	0	7	0	0
T117	0	28	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1840	0	0
T19	1834	15	0	0
T20	1930	16	0	0
T21	1002	0	0	0
T22	2274	8	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	7	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	5	0	0
T78	0	13	0	0
T80	0	3	0	0
T81	0	13	0	0
T116	0	10	0	0
T117	0	42	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1606	0	0
T19	1834	17	0	0
T20	1930	11	0	0
T21	1002	0	0	0
T22	2274	9	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	15	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	6	0	0
T78	0	14	0	0
T81	0	33	0	0
T86	0	351	0	0
T116	0	7	0	0
T117	0	88	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556717872	1581	0	0
T19	1834	13	0	0
T20	1930	0	0	0
T21	1002	0	0	0
T22	2274	20	0	0
T23	1320	0	0	0
T24	587	0	0	0
T25	1324	0	0	0
T26	1564	7	0	0
T27	9048	0	0	0
T28	5425	0	0	0
T77	0	16	0	0
T78	0	4	0	0
T80	0	1	0	0
T81	0	13	0	0
T86	0	457	0	0
T117	0	63	0	0
T126	0	6	0	0