Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29344

1

T1

281

T2

15

T3

364

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25330	1			T1	163		T2	35		T3	620
values[0x0]	11532	1			T1	100		T2	11		T3	199
values[0x1]	12256	1			T1	117		T2	10		T3	188

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35143

1

T1

317

T2

25

T3

586

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	213	1			T6	1		T13	8		T16	3
valid_sources[0x01]	165	1			T1	12		T5	1		T4	3
valid_sources[0x02]	215	1			T5	2		T6	3		T28	5
valid_sources[0x03]	363	1			T5	1		T6	7		T28	10
valid_sources[0x04]	171	1			T1	21		T4	1		T6	2
valid_sources[0x05]	171	1			T1	1		T2	2		T6	3
valid_sources[0x06]	193	1			T3	50		T5	1		T4	2
valid_sources[0x07]	191	1			T1	7		T5	1		T4	1
valid_sources[0x08]	267	1			T5	1		T4	1		T6	2
valid_sources[0x09]	408	1			T3	23		T4	1		T6	9
valid_sources[0x0a]	151	1			T1	5		T6	3		T25	1
valid_sources[0x0b]	303	1			T1	1		T3	4		T4	1
valid_sources[0x0c]	206	1			T3	1		T5	2		T4	1
valid_sources[0x0d]	253	1			T3	5		T4	1		T6	11
valid_sources[0x0e]	128	1			T4	1		T6	2		T26	4
valid_sources[0x0f]	172	1			T6	2		T15	6		T27	6
valid_sources[0x10]	140	1			T5	1		T4	1		T6	6
valid_sources[0x11]	148	1			T6	5		T26	7		T28	3
valid_sources[0x12]	161	1			T6	4		T8	1		T26	1
valid_sources[0x13]	119	1			T4	1		T6	7		T15	1
valid_sources[0x14]	121	1			T1	4		T6	5		T9	1
valid_sources[0x15]	238	1			T3	2		T6	2		T13	2
valid_sources[0x16]	327	1			T1	1		T4	1		T6	3
valid_sources[0x17]	152	1			T6	7		T16	2		T25	1
valid_sources[0x18]	146	1			T3	3		T5	3		T4	1
valid_sources[0x19]	216	1			T4	2		T6	3		T22	4
valid_sources[0x1a]	185	1			T2	1		T6	5		T28	8
valid_sources[0x1b]	205	1			T4	1		T6	4		T22	8
valid_sources[0x1c]	186	1			T1	3		T3	13		T5	1
valid_sources[0x1d]	229	1			T3	21		T4	1		T6	3
valid_sources[0x1e]	119	1			T5	1		T6	1		T28	10
valid_sources[0x1f]	400	1			T1	6		T6	4		T15	11
valid_sources[0x20]	202	1			T5	1		T4	1		T28	4
valid_sources[0x21]	157	1			T1	10		T4	1		T26	6
valid_sources[0x22]	189	1			T4	2		T6	9		T28	15
valid_sources[0x23]	199	1			T2	1		T3	12		T6	1
valid_sources[0x24]	194	1			T1	2		T4	2		T6	8
valid_sources[0x25]	295	1			T2	1		T3	1		T5	1
valid_sources[0x26]	245	1			T5	1		T4	1		T6	7
valid_sources[0x27]	166	1			T1	4		T6	3		T16	4
valid_sources[0x28]	122	1			T3	1		T4	2		T6	7
valid_sources[0x29]	313	1			T1	1		T4	2		T6	6
valid_sources[0x2a]	162	1			T1	5		T4	2		T6	5
valid_sources[0x2b]	181	1			T4	2		T6	9		T15	6
valid_sources[0x2c]	293	1			T4	1		T6	3		T13	8
valid_sources[0x2d]	137	1			T1	1		T3	5		T6	3
valid_sources[0x2e]	193	1			T1	42		T5	2		T4	1
valid_sources[0x2f]	187	1			T4	2		T6	6		T28	9
valid_sources[0x30]	128	1			T1	8		T6	3		T28	5
valid_sources[0x31]	154	1			T1	2		T6	2		T16	2
valid_sources[0x32]	226	1			T2	1		T4	1		T6	1
valid_sources[0x33]	311	1			T3	4		T4	2		T6	7
valid_sources[0x34]	170	1			T4	1		T6	7		T28	11
valid_sources[0x35]	162	1			T2	1		T4	1		T16	4
valid_sources[0x36]	195	1			T2	3		T3	15		T4	1
valid_sources[0x37]	178	1			T3	5		T6	8		T9	1
valid_sources[0x38]	180	1			T5	2		T6	1		T16	2
valid_sources[0x39]	142	1			T5	2		T6	1		T22	8
valid_sources[0x3a]	273	1			T2	3		T4	1		T6	2
valid_sources[0x3b]	188	1			T4	1		T6	4		T9	1
valid_sources[0x3c]	129	1			T3	15		T5	3		T4	2
valid_sources[0x3d]	243	1			T6	5		T28	8		T17	5
valid_sources[0x3e]	165	1			T2	1		T5	3		T6	7
valid_sources[0x3f]	153	1			T1	1		T4	1		T6	3
valid_sources[0x40]	174	1			T1	5		T4	2		T6	1
valid_sources[0x41]	174	1			T6	6		T13	6		T27	11
valid_sources[0x42]	116	1			T3	3		T4	1		T6	3
valid_sources[0x43]	123	1			T2	1		T5	1		T6	2
valid_sources[0x44]	242	1			T5	1		T4	3		T6	2
valid_sources[0x45]	256	1			T4	2		T6	5		T8	4
valid_sources[0x46]	176	1			T5	1		T6	5		T28	12
valid_sources[0x47]	237	1			T5	2		T4	1		T6	7
valid_sources[0x48]	389	1			T6	3		T16	3		T28	16
valid_sources[0x49]	166	1			T2	1		T3	7		T5	3
valid_sources[0x4a]	183	1			T3	24		T6	1		T22	5
valid_sources[0x4b]	188	1			T6	5		T9	2		T16	4
valid_sources[0x4c]	227	1			T4	1		T6	4		T16	3
valid_sources[0x4d]	143	1			T3	1		T6	6		T13	2
valid_sources[0x4e]	171	1			T6	5		T28	5		T29	5
valid_sources[0x4f]	218	1			T6	4		T22	6		T16	3
valid_sources[0x50]	121	1			T5	1		T6	3		T28	1
valid_sources[0x51]	155	1			T1	1		T2	2		T4	2
valid_sources[0x52]	318	1			T3	23		T6	3		T22	8
valid_sources[0x53]	181	1			T6	5		T22	16		T28	7
valid_sources[0x54]	317	1			T5	1		T4	2		T6	3
valid_sources[0x55]	163	1			T5	1		T4	2		T6	1
valid_sources[0x56]	113	1			T2	1		T5	1		T6	6
valid_sources[0x57]	320	1			T4	3		T6	2		T26	4
valid_sources[0x58]	157	1			T4	2		T6	4		T28	9
valid_sources[0x59]	114	1			T4	3		T6	2		T16	2
valid_sources[0x5a]	202	1			T4	3		T6	6		T14	6
valid_sources[0x5b]	151	1			T2	2		T4	2		T6	5
valid_sources[0x5c]	149	1			T5	1		T4	3		T6	4
valid_sources[0x5d]	144	1			T5	2		T4	2		T6	3
valid_sources[0x5e]	238	1			T2	1		T6	1		T26	4
valid_sources[0x5f]	271	1			T3	2		T4	3		T16	2
valid_sources[0x60]	164	1			T5	1		T6	3		T28	12
valid_sources[0x61]	166	1			T1	20		T4	1		T6	4
valid_sources[0x62]	219	1			T1	5		T3	4		T6	5
valid_sources[0x63]	195	1			T6	4		T28	18		T29	4
valid_sources[0x64]	197	1			T1	3		T5	1		T4	2
valid_sources[0x65]	198	1			T1	1		T5	1		T6	3
valid_sources[0x66]	196	1			T3	1		T5	1		T6	1
valid_sources[0x67]	180	1			T4	3		T25	2		T27	2
valid_sources[0x68]	125	1			T5	2		T6	1		T28	6
valid_sources[0x69]	216	1			T2	1		T6	9		T13	12
valid_sources[0x6a]	266	1			T3	75		T5	2		T6	1
valid_sources[0x6b]	252	1			T5	2		T6	7		T27	1
valid_sources[0x6c]	159	1			T6	6		T22	11		T26	2
valid_sources[0x6d]	246	1			T4	1		T6	4		T22	23
valid_sources[0x6e]	157	1			T4	2		T6	7		T15	1
valid_sources[0x6f]	210	1			T1	10		T2	2		T5	1
valid_sources[0x70]	190	1			T5	1		T4	1		T6	6
valid_sources[0x71]	322	1			T5	1		T4	3		T6	10
valid_sources[0x72]	185	1			T4	1		T6	3		T28	3
valid_sources[0x73]	150	1			T3	6		T6	7		T16	4
valid_sources[0x74]	186	1			T3	12		T6	2		T9	1
valid_sources[0x75]	253	1			T1	8		T6	8		T8	1
valid_sources[0x76]	156	1			T1	3		T5	3		T4	1
valid_sources[0x77]	241	1			T2	1		T6	3		T15	9
valid_sources[0x78]	168	1			T3	20		T4	1		T6	5
valid_sources[0x79]	158	1			T2	1		T4	1		T6	2
valid_sources[0x7a]	278	1			T3	9		T5	1		T4	1
valid_sources[0x7b]	199	1			T2	1		T6	6		T15	10
valid_sources[0x7c]	149	1			T6	6		T28	6		T17	7
valid_sources[0x7d]	140	1			T3	2		T6	6		T13	2
valid_sources[0x7e]	157	1			T8	1		T13	3		T15	3
valid_sources[0x7f]	191	1			T1	11		T6	3		T15	9
valid_sources[0x80]	300	1			T4	1		T6	2		T15	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10719

1

T1

90

T2

3

T3

95

values[0x0]

all_enables

biggest_size

9527

1

T1

91

T2

8

T3

147

values[0x1]

all_enables

biggest_size

9098

1

T1

100

T2

4

T3

122