Line Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Line Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 10 | 0 | 0.00 |
| ALWAYS | 60 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 66 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 68 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 73 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 60 |
0 |
2 |
| 61 |
0 |
2 |
|
|
|
==> MISSING_ELSE |
| 66 |
0 |
1 |
| 68 |
0 |
1 |
| 73 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Cond Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 68
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Branch Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
0 |
0.00 |
| IF |
60 |
3 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_ni))
-2-: 61 if (reg2hw_intr_test_qe_i)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_overflow
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_overflow
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_overflow
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_nak
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_nak
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_nak
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 10 | 0 | 0.00 |
| ALWAYS | 60 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 66 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 68 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 73 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 60 |
0 |
2 |
| 61 |
0 |
2 |
|
|
|
==> MISSING_ELSE |
| 66 |
0 |
1 |
| 68 |
0 |
1 |
| 73 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 68
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
0 |
0.00 |
| IF |
60 |
3 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_ni))
-2-: 61 if (reg2hw_intr_test_qe_i)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_overflow
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_overflow
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_overflow
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 10 | 0 | 0.00 |
| ALWAYS | 60 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 66 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 68 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 73 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 60 |
0 |
2 |
| 61 |
0 |
2 |
|
|
|
==> MISSING_ELSE |
| 66 |
0 |
1 |
| 68 |
0 |
1 |
| 73 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 68
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
0 |
0.00 |
| IF |
60 |
3 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_ni))
-2-: 61 if (reg2hw_intr_test_qe_i)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 0 | 0.00 |
| CONT_ASSIGN | 47 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 49 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 52 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 54 | 1 | 0 | 0.00 |
| ALWAYS | 80 | 3 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
0 |
1 |
| 49 |
0 |
1 |
| 52 |
0 |
1 |
| 54 |
0 |
1 |
| 80 |
0 |
1 |
| 81 |
0 |
1 |
| 83 |
0 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
| Total | Covered | Percent |
|---|
| Conditions | 12 | 0 | 0.00 |
| Logical | 12 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
0 |
0.00 |
| IF |
80 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|