Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.33	0.00	0.00	100.00				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	605703	11883	0	0
ctrl_rd_A	605703	2090	0	0
fifo_ctrl_rd_A	605703	2796	0	0
host_timeout_ctrl_rd_A	605703	1695	0	0
intr_enable_rd_A	605703	4623	0	0
ovrd_rd_A	605703	2127	0	0
target_id_rd_A	605703	2158	0	0
timeout_ctrl_rd_A	605703	1819	0	0
timing0_rd_A	605703	1957	0	0
timing1_rd_A	605703	1941	0	0
timing2_rd_A	605703	1921	0	0
timing3_rd_A	605703	1858	0	0
timing4_rd_A	605703	1861	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	11883	0	0
T1	2644	192	0	0
T2	1728	0	0	0
T3	11925	9	0	0
T4	2288	23	0	0
T5	2024	0	0	0
T6	7482	8	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T13	2273	23	0	0
T14	860	0	0	0
T15	0	498	0	0
T16	0	120	0	0
T17	0	69	0	0
T18	0	4	0	0
T59	0	14	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	2090	0	0
T3	11925	191	0	0
T4	2288	15	0	0
T5	2024	10	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	11	0	0
T14	860	0	0	0
T15	0	5	0	0
T16	0	15	0	0
T22	3485	73	0	0
T25	0	13	0	0
T26	0	10	0	0
T28	0	205	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	2796	0	0
T3	11925	240	0	0
T4	2288	12	0	0
T5	2024	5	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	32	0	0
T14	860	0	0	0
T15	0	14	0	0
T16	0	25	0	0
T22	3485	77	0	0
T25	0	37	0	0
T26	0	2	0	0
T28	0	245	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1695	0	0
T3	11925	71	0	0
T4	2288	8	0	0
T5	2024	6	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	16	0	0
T14	860	0	0	0
T15	0	7	0	0
T20	0	47	0	0
T22	3485	81	0	0
T25	0	13	0	0
T26	0	6	0	0
T28	0	245	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	4623	0	0
T3	11925	541	0	0
T4	2288	79	0	0
T5	2024	26	0	0
T6	7482	0	0	0
T7	1905	2	0	0
T8	1830	0	0	0
T9	1330	14	0	0
T13	2273	15	0	0
T14	860	0	0	0
T15	0	6	0	0
T22	3485	79	0	0
T25	0	58	0	0
T26	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	2127	0	0
T3	11925	145	0	0
T4	2288	36	0	0
T5	2024	4	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	22	0	0
T14	860	0	0	0
T15	0	5	0	0
T16	0	22	0	0
T22	3485	62	0	0
T25	0	12	0	0
T26	0	1	0	0
T28	0	199	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	2158	0	0
T3	11925	192	0	0
T4	2288	22	0	0
T5	2024	5	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	13	0	0
T14	860	0	0	0
T16	0	6	0	0
T20	0	44	0	0
T22	3485	98	0	0
T25	0	10	0	0
T26	0	22	0	0
T28	0	231	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1819	0	0
T3	11925	97	0	0
T4	2288	10	0	0
T5	2024	0	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	21	0	0
T14	860	0	0	0
T15	0	26	0	0
T16	0	4	0	0
T20	0	20	0	0
T22	3485	72	0	0
T25	0	10	0	0
T26	0	28	0	0
T28	0	236	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1957	0	0
T3	11925	109	0	0
T4	2288	18	0	0
T5	2024	7	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	15	0	0
T14	860	0	0	0
T15	0	10	0	0
T16	0	5	0	0
T22	3485	94	0	0
T25	0	16	0	0
T26	0	14	0	0
T28	0	218	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1941	0	0
T3	11925	118	0	0
T4	2288	15	0	0
T5	2024	0	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	16	0	0
T14	860	0	0	0
T15	0	2	0	0
T16	0	19	0	0
T20	0	17	0	0
T22	3485	82	0	0
T25	0	12	0	0
T26	0	28	0	0
T28	0	213	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1921	0	0
T3	11925	143	0	0
T4	2288	12	0	0
T5	2024	0	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	11	0	0
T14	860	0	0	0
T15	0	22	0	0
T16	0	8	0	0
T20	0	49	0	0
T22	3485	84	0	0
T25	0	13	0	0
T26	0	21	0	0
T28	0	226	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1858	0	0
T3	11925	118	0	0
T4	2288	26	0	0
T5	2024	4	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	16	0	0
T14	860	0	0	0
T15	0	6	0	0
T16	0	3	0	0
T22	3485	88	0	0
T25	0	10	0	0
T26	0	22	0	0
T28	0	230	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	605703	1861	0	0
T3	11925	76	0	0
T4	2288	17	0	0
T5	2024	7	0	0
T6	7482	0	0	0
T7	1905	0	0	0
T8	1830	0	0	0
T9	1330	0	0	0
T13	2273	11	0	0
T14	860	0	0	0
T15	0	18	0	0
T16	0	11	0	0
T22	3485	75	0	0
T25	0	22	0	0
T26	0	24	0	0
T28	0	241	0	0