Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	4	56	93.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	4	56	93.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	8414365	1			T18	8		T20	1		T24	8
all_values[1]	8414365	1			T18	8		T20	1		T24	8
all_values[2]	8414365	1			T18	8		T20	1		T24	8
all_values[3]	8414365	1			T18	8		T20	1		T24	8
all_values[4]	8414365	1			T18	8		T20	1		T24	8
all_values[5]	8414365	1			T18	8		T20	1		T24	8
all_values[6]	8414365	1			T18	8		T20	1		T24	8
all_values[7]	8414365	1			T18	8		T20	1		T24	8
all_values[8]	8414365	1			T18	8		T20	1		T24	8
all_values[9]	8414365	1			T18	8		T20	1		T24	8
all_values[10]	8414365	1			T18	8		T20	1		T24	8
all_values[11]	8414365	1			T18	8		T20	1		T24	8
all_values[12]	8414365	1			T18	8		T20	1		T24	8
all_values[13]	8414365	1			T18	8		T20	1		T24	8
all_values[14]	8414365	1			T18	8		T20	1		T24	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120931017

1

T18

73

T20

15

T24

73

auto[1]

5284458

1

T18

47

T24

47

T26

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120437881

1

T18

21

T20

15

T24

10

auto[1]

5777594

1

T18

99

T24

110

T26

102

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7283141	1			T20	1		T26	1		T60	4
all_values[0]	auto[0]	auto[1]	340642	1			T18	3		T24	5		T26	4
all_values[0]	auto[1]	auto[0]	741260	1			T7	2		T8	2		T9	1
all_values[0]	auto[1]	auto[1]	49322	1			T18	5		T24	3		T26	3
all_values[1]	auto[0]	auto[0]	7502198	1			T20	1		T24	1		T118	1
all_values[1]	auto[0]	auto[1]	354923	1			T18	5		T24	5		T26	7
all_values[1]	auto[1]	auto[0]	515556	1			T8	98		T9	1		T10	1
all_values[1]	auto[1]	auto[1]	41688	1			T18	3		T24	2		T26	1
all_values[2]	auto[0]	auto[0]	8026652	1			T18	1		T20	1		T24	2
all_values[2]	auto[0]	auto[1]	387501	1			T18	6		T24	2		T26	2
all_values[2]	auto[1]	auto[1]	212	1			T18	1		T24	4		T26	4
all_values[3]	auto[0]	auto[0]	8023499	1			T20	1		T26	1		T118	5
all_values[3]	auto[0]	auto[1]	390634	1			T18	6		T24	4		T26	4
all_values[3]	auto[1]	auto[1]	232	1			T18	2		T24	4		T26	3
all_values[4]	auto[0]	auto[0]	8024045	1			T18	2		T20	1		T24	1
all_values[4]	auto[0]	auto[1]	390069	1			T18	2		T24	2		T26	1
all_values[4]	auto[1]	auto[0]	52	1			T46	2		T40	30		T166	20
all_values[4]	auto[1]	auto[1]	199	1			T18	4		T24	5		T26	6
all_values[5]	auto[0]	auto[0]	8034486	1			T20	1		T24	1		T26	8
all_values[5]	auto[0]	auto[1]	379067	1			T18	3		T24	2		T60	5
all_values[5]	auto[1]	auto[0]	615	1			T40	615		-	-		-	-
all_values[5]	auto[1]	auto[1]	197	1			T18	5		T24	5		T60	3
all_values[6]	auto[0]	auto[0]	7233939	1			T18	8		T20	1		T24	1
all_values[6]	auto[0]	auto[1]	338598	1			T24	6		T26	5		T60	2
all_values[6]	auto[1]	auto[0]	783840	1			T7	1		T8	26		T9	1
all_values[6]	auto[1]	auto[1]	57988	1			T24	1		T26	1		T60	4
all_values[7]	auto[0]	auto[0]	7640719	1			T20	1		T60	1		T68	1
all_values[7]	auto[0]	auto[1]	375500	1			T18	4		T24	3		T26	5
all_values[7]	auto[1]	auto[0]	377048	1			T7	4		T8	900		T9	1
all_values[7]	auto[1]	auto[1]	21098	1			T18	4		T24	5		T26	3
all_values[8]	auto[0]	auto[0]	7050748	1			T20	1		T26	3		T68	1
all_values[8]	auto[0]	auto[1]	332712	1			T18	3		T24	5		T26	3
all_values[8]	auto[1]	auto[0]	967023	1			T7	14		T8	236		T9	1
all_values[8]	auto[1]	auto[1]	63882	1			T18	5		T24	3		T26	2
all_values[9]	auto[0]	auto[0]	7126212	1			T20	1		T24	1		T118	2
all_values[9]	auto[0]	auto[1]	295673	1			T18	6		T24	6		T26	6
all_values[9]	auto[1]	auto[0]	940292	1			T1	1		T2	1		T16	1
all_values[9]	auto[1]	auto[1]	52188	1			T18	2		T24	1		T26	2
all_values[10]	auto[0]	auto[0]	7909175	1			T20	1		T68	1		T119	3
all_values[10]	auto[0]	auto[1]	356813	1			T18	4		T24	6		T26	5
all_values[10]	auto[1]	auto[0]	148200	1			T13	2659		T14	3057		T15	678
all_values[10]	auto[1]	auto[1]	177	1			T18	4		T24	2		T26	3
all_values[11]	auto[0]	auto[0]	7500987	1			T18	4		T20	1		T24	1
all_values[11]	auto[0]	auto[1]	390647	1			T18	1		T24	4		T26	5
all_values[11]	auto[1]	auto[0]	522506	1			T13	4734		T14	5672		T15	12810
all_values[11]	auto[1]	auto[1]	225	1			T18	3		T24	3		T26	3
all_values[12]	auto[0]	auto[0]	8020938	1			T18	2		T20	1		T24	1
all_values[12]	auto[0]	auto[1]	393235	1			T18	4		T24	3		T26	6
all_values[12]	auto[1]	auto[1]	192	1			T18	2		T24	4		T26	2
all_values[13]	auto[0]	auto[0]	8046985	1			T18	1		T20	1		T60	2
all_values[13]	auto[0]	auto[1]	367145	1			T18	4		T24	5		T26	3
all_values[13]	auto[1]	auto[0]	9	1			T155	1		T157	1		T167	1
all_values[13]	auto[1]	auto[1]	226	1			T18	3		T24	3		T26	5
all_values[14]	auto[0]	auto[0]	8017756	1			T18	3		T20	1		T24	1
all_values[14]	auto[0]	auto[1]	396378	1			T18	1		T24	5		T26	6
all_values[14]	auto[1]	auto[1]	231	1			T18	4		T24	2		T26	2