Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.27 96.92 100.00 96.52 98.57 100.00 92.86


Total tests in report: 1645
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
55.08 55.08 46.24 46.24 38.42 38.42 58.86 58.86 96.52 96.52 41.05 41.05 76.41 76.41 28.05 28.05 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2908710578
73.78 18.70 84.81 38.57 61.78 23.36 62.26 3.40 96.52 0.00 73.44 32.38 91.42 15.01 46.22 18.17 /workspace/coverage/default/31.i2c_host_mode_toggle.3306430036
86.21 12.43 90.33 5.52 79.99 18.21 97.33 35.07 96.52 0.00 85.40 11.96 92.23 0.80 61.66 15.44 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1916302286
91.36 5.16 97.56 7.23 87.08 7.10 98.06 0.73 96.52 0.00 96.38 10.98 93.57 1.34 70.38 8.72 /workspace/coverage/default/18.i2c_target_stress_all.1595146920
93.44 2.08 98.24 0.68 92.37 5.29 98.30 0.24 96.52 0.00 97.48 1.10 93.57 0.00 77.63 7.25 /workspace/coverage/default/20.i2c_host_stress_all.400223216
94.82 1.38 98.24 0.00 93.78 1.41 98.79 0.49 96.52 0.00 97.59 0.11 97.32 3.75 81.51 3.89 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3351418285
95.20 0.38 98.24 0.00 94.04 0.27 99.27 0.49 96.52 0.00 97.59 0.00 97.32 0.00 83.40 1.89 /workspace/coverage/cover_reg_top/41.i2c_intr_test.4226476280
95.53 0.33 98.24 0.00 94.04 0.00 99.27 0.00 96.52 0.00 97.59 0.00 99.20 1.88 83.82 0.42 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2141201691
95.85 0.33 98.24 0.00 94.18 0.13 99.51 0.24 96.52 0.00 97.80 0.22 99.20 0.00 85.50 1.68 /workspace/coverage/default/29.i2c_host_override.2812980633
96.09 0.23 98.49 0.24 94.71 0.54 99.51 0.00 96.52 0.00 98.35 0.55 99.20 0.00 85.82 0.32 /workspace/coverage/default/19.i2c_host_perf.4109413337
96.29 0.20 98.49 0.00 95.18 0.47 99.51 0.00 96.52 0.00 98.35 0.00 99.20 0.00 86.76 0.95 /workspace/coverage/default/10.i2c_host_stress_all.1472932348
96.46 0.17 98.49 0.00 95.31 0.13 99.51 0.00 96.52 0.00 98.35 0.00 99.20 0.00 87.82 1.05 /workspace/coverage/default/0.i2c_target_glitch.3988626606
96.60 0.15 99.17 0.68 95.45 0.13 99.51 0.00 96.52 0.00 98.35 0.00 99.20 0.00 88.03 0.21 /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2251315585
96.74 0.14 99.17 0.00 95.45 0.00 99.51 0.00 96.52 0.00 98.35 0.00 99.20 0.00 88.97 0.95 /workspace/coverage/default/3.i2c_host_stress_all.2399336203
96.86 0.12 99.17 0.00 95.58 0.13 99.76 0.24 96.52 0.00 98.35 0.00 99.46 0.27 89.18 0.21 /workspace/coverage/default/0.i2c_sec_cm.4106764457
96.94 0.08 99.17 0.00 95.92 0.33 99.76 0.00 96.52 0.00 98.35 0.00 99.46 0.00 89.39 0.21 /workspace/coverage/default/40.i2c_host_stress_all_with_rand_reset.2840470628
97.02 0.08 99.17 0.00 95.92 0.00 99.76 0.00 96.52 0.00 98.35 0.00 100.00 0.54 89.39 0.00 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1743663735
97.09 0.08 99.17 0.00 95.92 0.00 99.76 0.00 96.52 0.00 98.35 0.00 100.00 0.00 89.92 0.53 /workspace/coverage/default/26.i2c_target_stress_all.2545774904
97.15 0.06 99.22 0.05 96.05 0.13 100.00 0.24 96.52 0.00 98.35 0.00 100.00 0.00 89.92 0.00 /workspace/coverage/default/12.i2c_alert_test.3690759862
97.20 0.05 99.27 0.05 96.25 0.20 100.00 0.00 96.52 0.00 98.46 0.11 100.00 0.00 89.92 0.00 /workspace/coverage/default/0.i2c_target_bad_addr.499392551
97.25 0.05 99.27 0.00 96.39 0.13 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 90.13 0.21 /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3138841323
97.30 0.05 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 90.44 0.32 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.169422527
97.34 0.05 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 90.76 0.32 /workspace/coverage/default/25.i2c_host_perf.3423540805
97.39 0.05 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 91.07 0.32 /workspace/coverage/default/28.i2c_target_tx_ovf.1526790544
97.42 0.03 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 91.28 0.21 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1606744236
97.45 0.03 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 91.49 0.21 /workspace/coverage/default/13.i2c_target_hrst.2732690530
97.48 0.03 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 91.70 0.21 /workspace/coverage/default/31.i2c_host_rx_oversample.3106332674
97.51 0.03 99.27 0.00 96.39 0.00 100.00 0.00 96.52 0.00 98.46 0.00 100.00 0.00 91.91 0.21 /workspace/coverage/default/42.i2c_host_fifo_reset_rx.377846664
97.53 0.03 99.27 0.00 96.45 0.07 100.00 0.00 96.52 0.00 98.57 0.11 100.00 0.00 91.91 0.00 /workspace/coverage/default/0.i2c_target_stretch.3636196780
97.56 0.02 99.27 0.00 96.52 0.07 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.02 0.11 /workspace/coverage/default/13.i2c_host_stress_all.2360393081
97.58 0.02 99.27 0.00 96.65 0.13 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.02 0.00 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.54035939
97.60 0.02 99.27 0.00 96.79 0.13 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.02 0.00 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.858771170
97.61 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.12 0.11 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3799241732
97.63 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.23 0.11 /workspace/coverage/default/0.i2c_host_perf.2488744955
97.64 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.33 0.11 /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2631102232
97.66 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.44 0.11 /workspace/coverage/default/11.i2c_target_hrst.2872330121
97.67 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.54 0.11 /workspace/coverage/default/24.i2c_target_unexp_stop.3458688557
97.69 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.65 0.11 /workspace/coverage/default/25.i2c_host_stress_all.2253161642
97.70 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.75 0.11 /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2723731799
97.72 0.02 99.27 0.00 96.79 0.00 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.86 0.11 /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1340438914
97.72 0.01 99.27 0.00 96.85 0.07 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.737884390
97.73 0.01 99.27 0.00 96.92 0.07 100.00 0.00 96.52 0.00 98.57 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1908038219

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1021720538
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1304811746
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3035898480
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1230203742
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.4186542139
/workspace/coverage/cover_reg_top/0.i2c_intr_test.1264878255
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1063914614
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.2500051264
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3349221726
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.898134693
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1726153666
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.289312643
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3437320687
/workspace/coverage/cover_reg_top/1.i2c_intr_test.1090081775
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4007350615
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.2168652988
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2027222947
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1586093056
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1935056544
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1081973011
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2632223744
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2062482939
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3429380289
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3603335074
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.296808004
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1867831927
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1684768105
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2930021385
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2161195406
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.3055212787
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1495380097
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.2975895371
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.996766393
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.198359577
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.4129456718
/workspace/coverage/cover_reg_top/13.i2c_intr_test.1421928880
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2898122355
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.705892543
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1424301983
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.4059910709
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3651110942
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2672141149
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.1503583803
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1545079216
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4090489338
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2766593228
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2036680664
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.2119362419
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1024462291
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4182384723
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.80596583
/workspace/coverage/cover_reg_top/16.i2c_intr_test.2551145036
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3636550943
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.242030851
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.323314616
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.867658889
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.537040274
/workspace/coverage/cover_reg_top/17.i2c_intr_test.661147237
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3690485972
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3802648201
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3700506877
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.1233632898
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3827413397
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.464439860
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4180278175
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3167543732
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.3716084790
/workspace/coverage/cover_reg_top/19.i2c_intr_test.573955532
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2756271931
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3918183099
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1973356162
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2694220738
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2211789240
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.583765263
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.3210104176
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3808904315
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3407332277
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.807572023
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3384161458
/workspace/coverage/cover_reg_top/20.i2c_intr_test.1910197775
/workspace/coverage/cover_reg_top/21.i2c_intr_test.3989236096
/workspace/coverage/cover_reg_top/22.i2c_intr_test.1979873386
/workspace/coverage/cover_reg_top/23.i2c_intr_test.1752792823
/workspace/coverage/cover_reg_top/24.i2c_intr_test.2420508294
/workspace/coverage/cover_reg_top/25.i2c_intr_test.124243615
/workspace/coverage/cover_reg_top/26.i2c_intr_test.3389906652
/workspace/coverage/cover_reg_top/27.i2c_intr_test.271050800
/workspace/coverage/cover_reg_top/28.i2c_intr_test.2688700122
/workspace/coverage/cover_reg_top/29.i2c_intr_test.933966887
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1531090664
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.102391884
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3520629369
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.947609799
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.1414656817
/workspace/coverage/cover_reg_top/3.i2c_intr_test.636446469
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1560517115
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.1981451986
/workspace/coverage/cover_reg_top/30.i2c_intr_test.61280696
/workspace/coverage/cover_reg_top/31.i2c_intr_test.2354566727
/workspace/coverage/cover_reg_top/32.i2c_intr_test.825536048
/workspace/coverage/cover_reg_top/33.i2c_intr_test.2065786064
/workspace/coverage/cover_reg_top/34.i2c_intr_test.955142831
/workspace/coverage/cover_reg_top/35.i2c_intr_test.273882602
/workspace/coverage/cover_reg_top/36.i2c_intr_test.4115310060
/workspace/coverage/cover_reg_top/37.i2c_intr_test.4004962152
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3081876912
/workspace/coverage/cover_reg_top/39.i2c_intr_test.3390642497
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3659574042
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2945189671
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.164578894
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3373480412
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1977346553
/workspace/coverage/cover_reg_top/4.i2c_intr_test.3621382567
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.107815319
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2500548839
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.206735537
/workspace/coverage/cover_reg_top/40.i2c_intr_test.1456175316
/workspace/coverage/cover_reg_top/42.i2c_intr_test.2656979603
/workspace/coverage/cover_reg_top/43.i2c_intr_test.1456912814
/workspace/coverage/cover_reg_top/44.i2c_intr_test.3260174120
/workspace/coverage/cover_reg_top/45.i2c_intr_test.913407485
/workspace/coverage/cover_reg_top/46.i2c_intr_test.1547995426
/workspace/coverage/cover_reg_top/47.i2c_intr_test.536725919
/workspace/coverage/cover_reg_top/48.i2c_intr_test.967796659
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2228715034
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.772737724
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.337344754
/workspace/coverage/cover_reg_top/5.i2c_intr_test.2777583622
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1743557258
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.557781076
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3942484157
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.586395386
/workspace/coverage/cover_reg_top/6.i2c_intr_test.118874497
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.400151550
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.293245442
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.807780775
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2650103098
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1233758360
/workspace/coverage/cover_reg_top/7.i2c_intr_test.3758283664
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3847691859
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.3494357350
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3071808277
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1503099041
/workspace/coverage/cover_reg_top/8.i2c_intr_test.1623614552
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1291741730
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.370792603
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2688219118
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2268933852
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1327778633
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2502752308
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Total test records in report: 1645
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T18 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2908710578 Feb 07 02:16:20 PM PST 24 Feb 07 02:16:22 PM PST 24 90600629 ps
T19 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2141201691 Feb 07 02:16:08 PM PST 24 Feb 07 02:16:11 PM PST 24 223279994 ps
T20 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3802648201 Feb 07 02:16:18 PM PST 24 Feb 07 02:16:22 PM PST 24 72673819 ps
T21 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2898122355 Feb 07 02:16:18 PM PST 24 Feb 07 02:16:21 PM PST 24 103449635 ps
T22 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2694220738 Feb 07 02:16:05 PM PST 24 Feb 07 02:16:12 PM PST 24 1107800959 ps
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