Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	8414365	1			T18	8		T20	1		T24	8
all_pins[1]	8414365	1			T18	8		T20	1		T24	8
all_pins[2]	8414365	1			T18	8		T20	1		T24	8
all_pins[3]	8414365	1			T18	8		T20	1		T24	8
all_pins[4]	8414365	1			T18	8		T20	1		T24	8
all_pins[5]	8414365	1			T18	8		T20	1		T24	8
all_pins[6]	8414365	1			T18	8		T20	1		T24	8
all_pins[7]	8414365	1			T18	8		T20	1		T24	8
all_pins[8]	8414365	1			T18	8		T20	1		T24	8
all_pins[9]	8414365	1			T18	8		T20	1		T24	8
all_pins[10]	8414365	1			T18	8		T20	1		T24	8
all_pins[11]	8414365	1			T18	8		T20	1		T24	8
all_pins[12]	8414365	1			T18	8		T20	1		T24	8
all_pins[13]	8414365	1			T18	8		T20	1		T24	8
all_pins[14]	8414365	1			T18	8		T20	1		T24	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	120853878	1			T18	92		T20	15		T24	104
values[0x1]	5361597	1			T18	28		T24	16		T26	19
transitions[0x0=>0x1]	3705615	1			T18	21		T24	15		T26	17
transitions[0x1=>0x0]	3705629	1			T18	21		T24	15		T26	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7623534	1			T18	5		T20	1		T24	8
all_pins[0]	values[0x1]	790831	1			T18	3		T26	2		T119	3
all_pins[0]	transitions[0x0=>0x1]	255282	1			T18	3		T26	2		T119	3
all_pins[0]	transitions[0x1=>0x0]	24334	1			T18	2		T24	1		T26	1
all_pins[1]	values[0x0]	7854482	1			T18	6		T20	1		T24	7
all_pins[1]	values[0x1]	559883	1			T18	2		T24	1		T26	1
all_pins[1]	transitions[0x0=>0x1]	559857	1			T18	2		T24	1		T26	1
all_pins[1]	transitions[0x1=>0x0]	82	1			T18	1		T24	1		T26	3
all_pins[2]	values[0x0]	8414257	1			T18	7		T20	1		T24	7
all_pins[2]	values[0x1]	108	1			T18	1		T24	1		T26	3
all_pins[2]	transitions[0x0=>0x1]	85	1			T18	1		T24	1		T26	3
all_pins[2]	transitions[0x1=>0x0]	86	1			T18	2		T24	1		T26	3
all_pins[3]	values[0x0]	8414256	1			T18	6		T20	1		T24	7
all_pins[3]	values[0x1]	109	1			T18	2		T24	1		T26	3
all_pins[3]	transitions[0x0=>0x1]	80	1			T18	2		T24	1		T26	2
all_pins[3]	transitions[0x1=>0x0]	132	1			T24	2		T120	1		T187	3
all_pins[4]	values[0x0]	8414204	1			T18	8		T20	1		T24	6
all_pins[4]	values[0x1]	161	1			T24	2		T26	1		T120	2
all_pins[4]	transitions[0x0=>0x1]	130	1			T24	2		T26	1		T120	2
all_pins[4]	transitions[0x1=>0x0]	758	1			T18	4		T24	3		T60	2
all_pins[5]	values[0x0]	8413576	1			T18	4		T20	1		T24	5
all_pins[5]	values[0x1]	789	1			T18	4		T24	3		T60	2
all_pins[5]	transitions[0x0=>0x1]	523	1			T18	4		T24	3		T60	2
all_pins[5]	transitions[0x1=>0x0]	845260	1			T60	2		T119	2		T122	1
all_pins[6]	values[0x0]	7568839	1			T18	8		T20	1		T24	8
all_pins[6]	values[0x1]	845526	1			T60	2		T119	2		T122	1
all_pins[6]	transitions[0x0=>0x1]	823858	1			T60	2		T119	2		T122	1
all_pins[6]	transitions[0x1=>0x0]	419302	1			T18	3		T26	1		T60	2
all_pins[7]	values[0x0]	7973395	1			T18	5		T20	1		T24	8
all_pins[7]	values[0x1]	440970	1			T18	3		T26	1		T60	2
all_pins[7]	transitions[0x0=>0x1]	370841	1			T18	1		T26	1		T60	2
all_pins[7]	transitions[0x1=>0x0]	988005	1			T60	1		T118	1		T119	1
all_pins[8]	values[0x0]	7356231	1			T18	6		T20	1		T24	8
all_pins[8]	values[0x1]	1058134	1			T18	2		T60	1		T118	1
all_pins[8]	transitions[0x0=>0x1]	251575	1			T18	2		T60	1		T118	1
all_pins[8]	transitions[0x1=>0x0]	186984	1			T18	1		T26	1		T118	2
all_pins[9]	values[0x0]	7420822	1			T18	7		T20	1		T24	8
all_pins[9]	values[0x1]	993543	1			T18	1		T26	1		T118	2
all_pins[9]	transitions[0x0=>0x1]	916801	1			T18	1		T118	2		T119	1
all_pins[9]	transitions[0x1=>0x0]	71841	1			T18	1		T26	1		T60	2
all_pins[10]	values[0x0]	8265782	1			T18	7		T20	1		T24	8
all_pins[10]	values[0x1]	148583	1			T18	1		T26	2		T60	2
all_pins[10]	transitions[0x0=>0x1]	3734	1			T18	1		T26	2		T60	2
all_pins[10]	transitions[0x1=>0x0]	377775	1			T18	3		T24	3		T60	1
all_pins[11]	values[0x0]	7891741	1			T18	5		T20	1		T24	5
all_pins[11]	values[0x1]	522624	1			T18	3		T24	3		T60	1
all_pins[11]	transitions[0x0=>0x1]	522600	1			T18	2		T24	3		T60	1
all_pins[11]	transitions[0x1=>0x0]	80	1			T24	1		T26	1		T60	2
all_pins[12]	values[0x0]	8414261	1			T18	7		T20	1		T24	7
all_pins[12]	values[0x1]	104	1			T18	1		T24	1		T26	1
all_pins[12]	transitions[0x0=>0x1]	75	1			T24	1		T26	1		T60	1
all_pins[12]	transitions[0x1=>0x0]	90	1			T18	1		T24	2		T26	4
all_pins[13]	values[0x0]	8414246	1			T18	6		T20	1		T24	6
all_pins[13]	values[0x1]	119	1			T18	2		T24	2		T26	4
all_pins[13]	transitions[0x0=>0x1]	96	1			T24	1		T26	4		T60	1
all_pins[13]	transitions[0x1=>0x0]	90	1			T18	1		T24	1		T118	2
all_pins[14]	values[0x0]	8414252	1			T18	5		T20	1		T24	6
all_pins[14]	values[0x1]	113	1			T18	3		T24	2		T60	1
all_pins[14]	transitions[0x0=>0x1]	78	1			T18	2		T24	2		T60	1
all_pins[14]	transitions[0x1=>0x0]	790810	1			T18	2		T26	2		T119	1