Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	476	1			T18	7		T24	7		T26	7
all_values[1]	476	1			T18	7		T24	7		T26	7
all_values[2]	476	1			T18	7		T24	7		T26	7
all_values[3]	476	1			T18	7		T24	7		T26	7
all_values[4]	476	1			T18	7		T24	7		T26	7
all_values[5]	476	1			T18	7		T24	7		T26	7
all_values[6]	476	1			T18	7		T24	7		T26	7
all_values[7]	476	1			T18	7		T24	7		T26	7
all_values[8]	476	1			T18	7		T24	7		T26	7
all_values[9]	476	1			T18	7		T24	7		T26	7
all_values[10]	476	1			T18	7		T24	7		T26	7
all_values[11]	476	1			T18	7		T24	7		T26	7
all_values[12]	476	1			T18	7		T24	7		T26	7
all_values[13]	476	1			T18	7		T24	7		T26	7
all_values[14]	476	1			T18	7		T24	7		T26	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3757

1

T18

58

T24

64

T26

57

auto[1]

3383

1

T18

47

T24

41

T26

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T18

20

T24

10

T26

17

auto[1]

6100

1

T18

85

T24

95

T26

88

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4236

1

T18

68

T24

57

T26

68

auto[1]

2904

1

T18

37

T24

48

T26

37

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T26	1		T60	4		T119	1
all_values[0]	auto[0]	auto[0]	auto[1]	108	1			T18	1		T24	2		T26	1
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T120	2		T137	1		T33	4
all_values[0]	auto[0]	auto[1]	auto[1]	103	1			T18	2		T24	1		T26	1
all_values[0]	auto[1]	auto[0]	auto[1]	103	1			T18	2		T24	3		T60	1
all_values[0]	auto[1]	auto[1]	auto[1]	96	1			T18	2		T24	1		T26	4
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T24	1		T118	1		T119	4
all_values[1]	auto[0]	auto[0]	auto[1]	114	1			T18	2		T24	1		T26	2
all_values[1]	auto[0]	auto[1]	auto[0]	13	1			T119	1		T188	1		T189	1
all_values[1]	auto[0]	auto[1]	auto[1]	116	1			T18	3		T24	3		T26	4
all_values[1]	auto[1]	auto[0]	auto[1]	121	1			T18	1		T24	1		T26	1
all_values[1]	auto[1]	auto[1]	auto[1]	79	1			T18	1		T24	1		T119	1
all_values[2]	auto[0]	auto[0]	auto[0]	37	1			T18	1		T24	2		T26	2
all_values[2]	auto[0]	auto[0]	auto[1]	106	1			T18	4		T24	1		T118	3
all_values[2]	auto[0]	auto[1]	auto[0]	32	1			T120	2		T187	1		T190	2
all_values[2]	auto[0]	auto[1]	auto[1]	113	1			T18	1		T26	2		T60	4
all_values[2]	auto[1]	auto[0]	auto[1]	95	1			T24	3		T26	1		T118	1
all_values[2]	auto[1]	auto[1]	auto[1]	93	1			T18	1		T24	1		T26	2
all_values[3]	auto[0]	auto[0]	auto[0]	36	1			T26	1		T118	2		T122	1
all_values[3]	auto[0]	auto[0]	auto[1]	102	1			T18	4		T24	1		T26	2
all_values[3]	auto[0]	auto[1]	auto[0]	37	1			T118	2		T191	1		T132	1
all_values[3]	auto[0]	auto[1]	auto[1]	99	1			T18	1		T24	2		T26	2
all_values[3]	auto[1]	auto[0]	auto[1]	104	1			T18	1		T24	3		T60	1
all_values[3]	auto[1]	auto[1]	auto[1]	98	1			T18	1		T24	1		T26	2
all_values[4]	auto[0]	auto[0]	auto[0]	46	1			T18	1		T24	1		T26	1
all_values[4]	auto[0]	auto[0]	auto[1]	106	1			T18	3		T24	1		T26	1
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T18	1		T119	1		T137	3
all_values[4]	auto[0]	auto[1]	auto[1]	111	1			T24	1		T60	4		T118	2
all_values[4]	auto[1]	auto[0]	auto[1]	91	1			T18	2		T24	2		T26	3
all_values[4]	auto[1]	auto[1]	auto[1]	91	1			T24	2		T26	2		T120	2
all_values[5]	auto[0]	auto[0]	auto[0]	62	1			T24	1		T26	5		T120	4
all_values[5]	auto[0]	auto[0]	auto[1]	92	1			T18	1		T24	2		T60	2
all_values[5]	auto[0]	auto[1]	auto[0]	41	1			T26	2		T33	3		T192	1
all_values[5]	auto[0]	auto[1]	auto[1]	94	1			T18	1		T24	2		T60	1
all_values[5]	auto[1]	auto[0]	auto[1]	93	1			T18	2		T24	1		T60	2
all_values[5]	auto[1]	auto[1]	auto[1]	94	1			T18	3		T24	1		T60	2
all_values[6]	auto[0]	auto[0]	auto[0]	40	1			T18	3		T24	1		T26	1
all_values[6]	auto[0]	auto[0]	auto[1]	110	1			T24	3		T26	1		T60	1
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T18	4		T26	1		T120	1
all_values[6]	auto[0]	auto[1]	auto[1]	108	1			T24	1		T26	2		T60	1
all_values[6]	auto[1]	auto[0]	auto[1]	95	1			T24	1		T60	2		T118	1
all_values[6]	auto[1]	auto[1]	auto[1]	94	1			T24	1		T26	2		T60	1
all_values[7]	auto[0]	auto[0]	auto[0]	36	1			T60	1		T122	1		T137	1
all_values[7]	auto[0]	auto[0]	auto[1]	116	1			T18	3		T24	3		T26	2
all_values[7]	auto[0]	auto[1]	auto[0]	22	1			T137	1		T188	1		T189	1
all_values[7]	auto[0]	auto[1]	auto[1]	101	1			T18	2		T26	2		T60	3
all_values[7]	auto[1]	auto[0]	auto[1]	123	1			T18	2		T24	3		T26	2
all_values[7]	auto[1]	auto[1]	auto[1]	78	1			T24	1		T26	1		T60	1
all_values[8]	auto[0]	auto[0]	auto[0]	34	1			T26	1		T138	1		T193	3
all_values[8]	auto[0]	auto[0]	auto[1]	117	1			T18	1		T24	1		T26	3
all_values[8]	auto[0]	auto[1]	auto[0]	30	1			T26	2		T119	2		T120	1
all_values[8]	auto[0]	auto[1]	auto[1]	93	1			T18	2		T24	2		T118	1
all_values[8]	auto[1]	auto[0]	auto[1]	126	1			T18	3		T24	4		T26	1
all_values[8]	auto[1]	auto[1]	auto[1]	76	1			T18	1		T119	1		T122	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T24	1		T118	2		T120	3
all_values[9]	auto[0]	auto[0]	auto[1]	120	1			T18	3		T24	5		T26	4
all_values[9]	auto[0]	auto[1]	auto[0]	29	1			T120	1		T187	1		T190	1
all_values[9]	auto[0]	auto[1]	auto[1]	110	1			T26	1		T118	1		T119	1
all_values[9]	auto[1]	auto[0]	auto[1]	107	1			T18	3		T24	1		T26	2
all_values[9]	auto[1]	auto[1]	auto[1]	74	1			T18	1		T60	1		T118	1
all_values[10]	auto[0]	auto[0]	auto[0]	41	1			T119	1		T122	1		T193	1
all_values[10]	auto[0]	auto[0]	auto[1]	101	1			T24	3		T26	1		T60	1
all_values[10]	auto[0]	auto[1]	auto[0]	42	1			T119	2		T120	4		T187	2
all_values[10]	auto[0]	auto[1]	auto[1]	115	1			T18	3		T24	2		T26	3
all_values[10]	auto[1]	auto[0]	auto[1]	94	1			T18	3		T24	2		T26	3
all_values[10]	auto[1]	auto[1]	auto[1]	83	1			T18	1		T60	1		T119	1
all_values[11]	auto[0]	auto[0]	auto[0]	43	1			T18	2		T24	1		T60	1
all_values[11]	auto[0]	auto[0]	auto[1]	109	1			T26	4		T60	3		T122	1
all_values[11]	auto[0]	auto[1]	auto[0]	27	1			T18	2		T122	1		T187	1
all_values[11]	auto[0]	auto[1]	auto[1]	95	1			T18	1		T24	1		T60	1
all_values[11]	auto[1]	auto[0]	auto[1]	108	1			T24	1		T26	3		T60	1
all_values[11]	auto[1]	auto[1]	auto[1]	94	1			T18	2		T24	4		T60	1
all_values[12]	auto[0]	auto[0]	auto[0]	38	1			T18	1		T24	1		T118	3
all_values[12]	auto[0]	auto[0]	auto[1]	93	1			T18	1		T26	2		T60	2
all_values[12]	auto[0]	auto[1]	auto[0]	30	1			T18	1		T118	1		T187	3
all_values[12]	auto[0]	auto[1]	auto[1]	123	1			T18	2		T24	2		T26	3
all_values[12]	auto[1]	auto[0]	auto[1]	94	1			T18	1		T24	4		T26	1
all_values[12]	auto[1]	auto[1]	auto[1]	98	1			T18	1		T26	1		T60	2
all_values[13]	auto[0]	auto[0]	auto[0]	39	1			T18	1		T60	2		T138	1
all_values[13]	auto[0]	auto[0]	auto[1]	101	1			T18	1		T24	1		T60	1
all_values[13]	auto[0]	auto[1]	auto[0]	41	1			T119	2		T187	2		T137	1
all_values[13]	auto[0]	auto[1]	auto[1]	99	1			T18	3		T24	2		T26	3
all_values[13]	auto[1]	auto[0]	auto[1]	101	1			T18	1		T24	1		T26	1
all_values[13]	auto[1]	auto[1]	auto[1]	95	1			T18	1		T24	3		T26	3
all_values[14]	auto[0]	auto[0]	auto[0]	30	1			T18	3		T24	1		T138	2
all_values[14]	auto[0]	auto[0]	auto[1]	108	1			T26	2		T60	1		T119	2
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T137	1		T191	1		T138	1
all_values[14]	auto[0]	auto[1]	auto[1]	113	1			T18	3		T24	4		T26	3
all_values[14]	auto[1]	auto[0]	auto[1]	109	1			T18	1		T26	2		T60	2
all_values[14]	auto[1]	auto[1]	auto[1]	97	1			T24	2		T60	2		T118	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal