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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.27 96.92 100.00 96.52 98.57 100.00 92.86


Total test records in report: 1645
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T1524 /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.72896984 Feb 07 02:22:13 PM PST 24 Feb 07 02:22:15 PM PST 24 432164284 ps
T1525 /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3807855960 Feb 07 02:23:53 PM PST 24 Feb 07 02:24:19 PM PST 24 10161748662 ps
T1526 /workspace/coverage/default/4.i2c_target_hrst.1127278188 Feb 07 02:19:14 PM PST 24 Feb 07 02:19:19 PM PST 24 1245935652 ps
T1527 /workspace/coverage/default/34.i2c_target_stress_all.2727853796 Feb 07 02:26:00 PM PST 24 Feb 07 02:26:42 PM PST 24 52804091304 ps
T1528 /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3339081826 Feb 07 02:20:47 PM PST 24 Feb 07 02:20:52 PM PST 24 161645842 ps
T1529 /workspace/coverage/default/12.i2c_target_smoke.1706431831 Feb 07 02:20:20 PM PST 24 Feb 07 02:20:34 PM PST 24 5067901266 ps
T1530 /workspace/coverage/default/17.i2c_target_stretch.1567116064 Feb 07 02:21:21 PM PST 24 Feb 07 02:23:46 PM PST 24 19542962431 ps
T1531 /workspace/coverage/default/15.i2c_host_mode_toggle.525258616 Feb 07 02:20:58 PM PST 24 Feb 07 02:23:06 PM PST 24 16552047044 ps
T1532 /workspace/coverage/default/13.i2c_host_error_intr.2472968740 Feb 07 02:20:48 PM PST 24 Feb 07 02:20:50 PM PST 24 56162614 ps
T1533 /workspace/coverage/default/47.i2c_host_fifo_watermark.79522211 Feb 07 02:29:13 PM PST 24 Feb 07 02:33:29 PM PST 24 22570182807 ps
T1534 /workspace/coverage/default/47.i2c_target_smoke.2585540307 Feb 07 02:29:17 PM PST 24 Feb 07 02:29:33 PM PST 24 1171451920 ps
T1535 /workspace/coverage/default/13.i2c_target_stretch.803686235 Feb 07 02:20:48 PM PST 24 Feb 07 02:25:24 PM PST 24 37980405636 ps
T1536 /workspace/coverage/default/1.i2c_target_tx_ovf.4076358155 Feb 07 02:18:34 PM PST 24 Feb 07 02:19:51 PM PST 24 13275417036 ps
T1537 /workspace/coverage/default/14.i2c_host_stretch_timeout.2043820817 Feb 07 02:20:44 PM PST 24 Feb 07 02:21:05 PM PST 24 1065751090 ps
T1538 /workspace/coverage/default/40.i2c_target_intr_smoke.1167524969 Feb 07 02:27:35 PM PST 24 Feb 07 02:27:44 PM PST 24 1699278156 ps
T1539 /workspace/coverage/default/40.i2c_host_mode_toggle.3336866245 Feb 07 02:27:35 PM PST 24 Feb 07 02:28:36 PM PST 24 1246050809 ps
T1540 /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3739101430 Feb 07 02:25:01 PM PST 24 Feb 07 02:25:11 PM PST 24 2076151488 ps
T1541 /workspace/coverage/default/27.i2c_target_hrst.630438905 Feb 07 02:24:10 PM PST 24 Feb 07 02:24:13 PM PST 24 1026444013 ps
T1542 /workspace/coverage/default/29.i2c_host_fifo_reset_rx.4216583858 Feb 07 02:24:24 PM PST 24 Feb 07 02:24:32 PM PST 24 594817080 ps
T1543 /workspace/coverage/default/34.i2c_host_error_intr.3286788645 Feb 07 02:25:39 PM PST 24 Feb 07 02:25:42 PM PST 24 41928446 ps
T1544 /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3175901554 Feb 07 02:26:08 PM PST 24 Feb 07 02:26:35 PM PST 24 10146719677 ps
T1545 /workspace/coverage/default/41.i2c_target_timeout.899888008 Feb 07 02:27:43 PM PST 24 Feb 07 02:27:52 PM PST 24 31745878814 ps
T1546 /workspace/coverage/default/26.i2c_target_perf.550288444 Feb 07 02:23:49 PM PST 24 Feb 07 02:23:55 PM PST 24 695680743 ps
T1547 /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3477537109 Feb 07 02:28:38 PM PST 24 Feb 07 02:28:39 PM PST 24 103402429 ps
T93 /workspace/coverage/default/2.i2c_sec_cm.2077656320 Feb 07 02:18:43 PM PST 24 Feb 07 02:18:44 PM PST 24 233462992 ps
T106 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2062482939 Feb 07 02:16:20 PM PST 24 Feb 07 02:16:25 PM PST 24 516480671 ps
T111 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1743663735 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:06 PM PST 24 37139737 ps
T1548 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1979873386 Feb 07 02:16:26 PM PST 24 Feb 07 02:16:32 PM PST 24 16678234 ps
T1549 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3081876912 Feb 07 02:16:25 PM PST 24 Feb 07 02:16:31 PM PST 24 27525206 ps
T127 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1414656817 Feb 07 02:16:08 PM PST 24 Feb 07 02:16:11 PM PST 24 19162242 ps
T128 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1743557258 Feb 07 02:16:04 PM PST 24 Feb 07 02:16:08 PM PST 24 43183703 ps
T1550 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3167543732 Feb 07 02:16:24 PM PST 24 Feb 07 02:16:28 PM PST 24 46501606 ps
T1551 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2065786064 Feb 07 02:16:22 PM PST 24 Feb 07 02:16:26 PM PST 24 41321138 ps
T1552 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2766593228 Feb 07 02:16:18 PM PST 24 Feb 07 02:16:21 PM PST 24 29592663 ps
T129 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3636550943 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:18 PM PST 24 53134796 ps
T130 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3407332277 Feb 07 02:16:09 PM PST 24 Feb 07 02:16:11 PM PST 24 96446062 ps
T1553 /workspace/coverage/cover_reg_top/32.i2c_intr_test.825536048 Feb 07 02:16:22 PM PST 24 Feb 07 02:16:25 PM PST 24 28049710 ps
T1554 /workspace/coverage/cover_reg_top/45.i2c_intr_test.913407485 Feb 07 02:16:21 PM PST 24 Feb 07 02:16:24 PM PST 24 46948071 ps
T1555 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.537040274 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:16 PM PST 24 50283962 ps
T1556 /workspace/coverage/cover_reg_top/30.i2c_intr_test.61280696 Feb 07 02:16:21 PM PST 24 Feb 07 02:16:23 PM PST 24 80248757 ps
T1557 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1291741730 Feb 07 02:16:12 PM PST 24 Feb 07 02:16:14 PM PST 24 26472546 ps
T1558 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4090489338 Feb 07 02:16:19 PM PST 24 Feb 07 02:16:22 PM PST 24 142243325 ps
T1559 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.198359577 Feb 07 02:16:18 PM PST 24 Feb 07 02:16:22 PM PST 24 83385150 ps
T1560 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1977346553 Feb 07 02:16:10 PM PST 24 Feb 07 02:16:13 PM PST 24 42073761 ps
T1561 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1867831927 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:19 PM PST 24 17217709 ps
T1562 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1230203742 Feb 07 02:16:16 PM PST 24 Feb 07 02:16:19 PM PST 24 54398662 ps
T1563 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3055212787 Feb 07 02:16:16 PM PST 24 Feb 07 02:16:19 PM PST 24 58854210 ps
T1564 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1485873530 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:20 PM PST 24 76065828 ps
T83 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.206735537 Feb 07 02:16:04 PM PST 24 Feb 07 02:16:09 PM PST 24 267439917 ps
T1565 /workspace/coverage/cover_reg_top/3.i2c_intr_test.636446469 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:07 PM PST 24 62085046 ps
T1566 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3651110942 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:17 PM PST 24 17351401 ps
T164 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.169422527 Feb 07 02:16:10 PM PST 24 Feb 07 02:16:13 PM PST 24 88768713 ps
T1567 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.107815319 Feb 07 02:16:04 PM PST 24 Feb 07 02:16:08 PM PST 24 63985873 ps
T80 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2027222947 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:08 PM PST 24 88621544 ps
T1568 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1935056544 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:17 PM PST 24 35021201 ps
T1569 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.464439860 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:19 PM PST 24 229249745 ps
T1570 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2650103098 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:20 PM PST 24 39688540 ps
T1571 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1752792823 Feb 07 02:16:23 PM PST 24 Feb 07 02:16:26 PM PST 24 14607219 ps
T1572 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.898134693 Feb 07 02:16:10 PM PST 24 Feb 07 02:16:14 PM PST 24 150188142 ps
T1573 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.867658889 Feb 07 02:16:16 PM PST 24 Feb 07 02:16:19 PM PST 24 79957202 ps
T1574 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3808904315 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:07 PM PST 24 44662749 ps
T1575 /workspace/coverage/cover_reg_top/34.i2c_intr_test.955142831 Feb 07 02:16:27 PM PST 24 Feb 07 02:16:33 PM PST 24 24914494 ps
T1576 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.705892543 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:19 PM PST 24 91026407 ps
T1577 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1090081775 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:07 PM PST 24 105183123 ps
T1578 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2975895371 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:19 PM PST 24 367138803 ps
T1579 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3520629369 Feb 07 02:16:01 PM PST 24 Feb 07 02:16:03 PM PST 24 17815750 ps
T1580 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1503583803 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:21 PM PST 24 61408306 ps
T1581 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3989236096 Feb 07 02:16:24 PM PST 24 Feb 07 02:16:27 PM PST 24 17489794 ps
T1582 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3437320687 Feb 07 02:16:12 PM PST 24 Feb 07 02:16:14 PM PST 24 29034056 ps
T1583 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3260174120 Feb 07 02:16:23 PM PST 24 Feb 07 02:16:26 PM PST 24 15591678 ps
T1584 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2500051264 Feb 07 02:16:04 PM PST 24 Feb 07 02:16:09 PM PST 24 137903177 ps
T1585 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4013276407 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:08 PM PST 24 97053444 ps
T1586 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1421928880 Feb 07 02:16:16 PM PST 24 Feb 07 02:16:18 PM PST 24 17797466 ps
T1587 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.293245442 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:07 PM PST 24 28914928 ps
T1588 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.102391884 Feb 07 02:16:08 PM PST 24 Feb 07 02:16:14 PM PST 24 1166073212 ps
T1589 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1910197775 Feb 07 02:16:26 PM PST 24 Feb 07 02:16:32 PM PST 24 137400909 ps
T1590 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1081973011 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:16 PM PST 24 73681093 ps
T112 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.586395386 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:06 PM PST 24 49926244 ps
T1591 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2168652988 Feb 07 02:16:13 PM PST 24 Feb 07 02:16:15 PM PST 24 333685117 ps
T77 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.737884390 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:20 PM PST 24 227668691 ps
T1592 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.323314616 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:17 PM PST 24 82969362 ps
T1593 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.80596583 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:19 PM PST 24 20033828 ps
T1594 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2656979603 Feb 07 02:16:27 PM PST 24 Feb 07 02:16:33 PM PST 24 91529338 ps
T1595 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2777583622 Feb 07 02:16:09 PM PST 24 Feb 07 02:16:12 PM PST 24 40629379 ps
T1596 /workspace/coverage/cover_reg_top/19.i2c_intr_test.573955532 Feb 07 02:16:20 PM PST 24 Feb 07 02:16:22 PM PST 24 37638747 ps
T113 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.4186542139 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:07 PM PST 24 43987439 ps
T1597 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1684768105 Feb 07 02:16:18 PM PST 24 Feb 07 02:16:21 PM PST 24 51220999 ps
T1598 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1063914614 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:06 PM PST 24 33322329 ps
T86 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2688219118 Feb 07 02:16:09 PM PST 24 Feb 07 02:16:12 PM PST 24 304978224 ps
T1599 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1304811746 Feb 07 02:16:04 PM PST 24 Feb 07 02:16:11 PM PST 24 286051201 ps
T1600 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2420508294 Feb 07 02:16:21 PM PST 24 Feb 07 02:16:24 PM PST 24 15150146 ps
T114 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1233632898 Feb 07 02:16:25 PM PST 24 Feb 07 02:16:31 PM PST 24 19166685 ps
T1601 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1586093056 Feb 07 02:16:19 PM PST 24 Feb 07 02:16:22 PM PST 24 25565546 ps
T1602 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1547995426 Feb 07 02:16:25 PM PST 24 Feb 07 02:16:31 PM PST 24 50846841 ps
T1603 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3918183099 Feb 07 02:16:28 PM PST 24 Feb 07 02:16:34 PM PST 24 60284604 ps
T78 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4180278175 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:18 PM PST 24 49120142 ps
T1604 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2632223744 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:18 PM PST 24 330677567 ps
T1605 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2268933852 Feb 07 02:16:13 PM PST 24 Feb 07 02:16:15 PM PST 24 28038717 ps
T115 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3349221726 Feb 07 02:16:07 PM PST 24 Feb 07 02:16:10 PM PST 24 63433827 ps
T1606 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1726153666 Feb 07 02:16:11 PM PST 24 Feb 07 02:16:14 PM PST 24 16163209 ps
T1607 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4007350615 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:06 PM PST 24 19876077 ps
T1608 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3390642497 Feb 07 02:16:25 PM PST 24 Feb 07 02:16:28 PM PST 24 44444108 ps
T1609 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2672141149 Feb 07 02:16:21 PM PST 24 Feb 07 02:16:23 PM PST 24 29964913 ps
T1610 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.164578894 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:17 PM PST 24 70176048 ps
T1611 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2211789240 Feb 07 02:16:06 PM PST 24 Feb 07 02:16:09 PM PST 24 63299281 ps
T1612 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3942484157 Feb 07 02:16:06 PM PST 24 Feb 07 02:16:10 PM PST 24 23625697 ps
T1613 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2119362419 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:20 PM PST 24 146281816 ps
T1614 /workspace/coverage/cover_reg_top/27.i2c_intr_test.271050800 Feb 07 02:16:23 PM PST 24 Feb 07 02:16:26 PM PST 24 79484957 ps
T1615 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2688700122 Feb 07 02:16:24 PM PST 24 Feb 07 02:16:27 PM PST 24 63514730 ps
T1616 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1495380097 Feb 07 02:16:16 PM PST 24 Feb 07 02:16:18 PM PST 24 19221301 ps
T1617 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2228715034 Feb 07 02:16:21 PM PST 24 Feb 07 02:16:24 PM PST 24 61678141 ps
T1618 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3071808277 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:17 PM PST 24 69286421 ps
T1619 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.242030851 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:19 PM PST 24 181040144 ps
T1620 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2945189671 Feb 07 02:16:07 PM PST 24 Feb 07 02:16:14 PM PST 24 900822115 ps
T116 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1531090664 Feb 07 02:16:06 PM PST 24 Feb 07 02:16:10 PM PST 24 139620394 ps
T1621 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1424301983 Feb 07 02:16:14 PM PST 24 Feb 07 02:16:17 PM PST 24 33039958 ps
T1622 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1981451986 Feb 07 02:16:01 PM PST 24 Feb 07 02:16:04 PM PST 24 145848587 ps
T1623 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3716084790 Feb 07 02:16:23 PM PST 24 Feb 07 02:16:27 PM PST 24 29401049 ps
T1624 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.947609799 Feb 07 02:15:59 PM PST 24 Feb 07 02:16:01 PM PST 24 35338989 ps
T1625 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2161195406 Feb 07 02:16:20 PM PST 24 Feb 07 02:16:23 PM PST 24 46384672 ps
T1626 /workspace/coverage/cover_reg_top/40.i2c_intr_test.1456175316 Feb 07 02:16:27 PM PST 24 Feb 07 02:16:33 PM PST 24 27238007 ps
T1627 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2500548839 Feb 07 02:16:01 PM PST 24 Feb 07 02:16:04 PM PST 24 145112758 ps
T1628 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1024462291 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:19 PM PST 24 455471361 ps
T1629 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.337344754 Feb 07 02:16:08 PM PST 24 Feb 07 02:16:11 PM PST 24 60895119 ps
T1630 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3621382567 Feb 07 02:16:02 PM PST 24 Feb 07 02:16:04 PM PST 24 17174238 ps
T1631 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3758283664 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:06 PM PST 24 18124425 ps
T1632 /workspace/coverage/cover_reg_top/48.i2c_intr_test.967796659 Feb 07 02:16:27 PM PST 24 Feb 07 02:16:33 PM PST 24 16376277 ps
T117 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4059910709 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:19 PM PST 24 15041660 ps
T165 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3429380289 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:18 PM PST 24 125838452 ps
T1633 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1264878255 Feb 07 02:16:04 PM PST 24 Feb 07 02:16:07 PM PST 24 25083534 ps
T87 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.233865278 Feb 07 02:16:06 PM PST 24 Feb 07 02:16:11 PM PST 24 148213702 ps
T81 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.858771170 Feb 07 02:16:19 PM PST 24 Feb 07 02:16:23 PM PST 24 105899020 ps
T1634 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1021720538 Feb 07 02:16:02 PM PST 24 Feb 07 02:16:05 PM PST 24 60232446 ps
T1635 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2036680664 Feb 07 02:16:18 PM PST 24 Feb 07 02:16:21 PM PST 24 18996025 ps
T1636 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1560517115 Feb 07 02:16:05 PM PST 24 Feb 07 02:16:08 PM PST 24 28114966 ps
T1637 /workspace/coverage/cover_reg_top/36.i2c_intr_test.4115310060 Feb 07 02:16:24 PM PST 24 Feb 07 02:16:27 PM PST 24 73681167 ps
T1638 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.807572023 Feb 07 02:16:03 PM PST 24 Feb 07 02:16:07 PM PST 24 173399065 ps
T1639 /workspace/coverage/cover_reg_top/6.i2c_intr_test.118874497 Feb 07 02:16:12 PM PST 24 Feb 07 02:16:14 PM PST 24 132707443 ps
T123 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1327778633 Feb 07 02:16:17 PM PST 24 Feb 07 02:16:19 PM PST 24 63210303 ps
T1640 /workspace/coverage/cover_reg_top/35.i2c_intr_test.273882602 Feb 07 02:16:25 PM PST 24 Feb 07 02:16:31 PM PST 24 21978322 ps
T1641 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3847691859 Feb 07 02:16:02 PM PST 24 Feb 07 02:16:05 PM PST 24 77870914 ps
T1642 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2930021385 Feb 07 02:16:19 PM PST 24 Feb 07 02:16:23 PM PST 24 203605657 ps
T1643 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3690485972 Feb 07 02:16:20 PM PST 24 Feb 07 02:16:23 PM PST 24 88269698 ps
T1644 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.557781076 Feb 07 02:16:15 PM PST 24 Feb 07 02:16:18 PM PST 24 229852416 ps
T1645 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1503099041 Feb 07 02:16:16 PM PST 24 Feb 07 02:16:19 PM PST 24 49257470 ps

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2908710578
Short name T18
Test name
Test status
Simulation time 90600629 ps
CPU time 0.67 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202320 kb
Host smart-d25b43c3-631b-4c5e-9dfb-ca644de0c986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908710578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2908710578
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3306430036
Short name T8
Test name
Test status
Simulation time 6143185634 ps
CPU time 47.58 seconds
Started Feb 07 02:25:18 PM PST 24
Finished Feb 07 02:26:07 PM PST 24
Peak memory 272288 kb
Host smart-e351bbf7-a0cd-44f9-936f-361c2f64aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306430036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3306430036
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1916302286
Short name T27
Test name
Test status
Simulation time 75447045 ps
CPU time 1.28 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202516 kb
Host smart-1630e51b-ee27-410f-8079-d87a58ca28ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916302286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1916302286
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.1595146920
Short name T13
Test name
Test status
Simulation time 67202940647 ps
CPU time 225.96 seconds
Started Feb 07 02:21:33 PM PST 24
Finished Feb 07 02:25:21 PM PST 24
Peak memory 867908 kb
Host smart-1e6cbbd1-6cc8-4e08-9994-5071de24f950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595146920 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.1595146920
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.400223216
Short name T30
Test name
Test status
Simulation time 50748402992 ps
CPU time 3555.28 seconds
Started Feb 07 02:22:04 PM PST 24
Finished Feb 07 03:21:21 PM PST 24
Peak memory 4058344 kb
Host smart-536665bb-ccad-4981-afe3-d6852c12037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400223216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.400223216
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3351418285
Short name T74
Test name
Test status
Simulation time 419303028 ps
CPU time 2.08 seconds
Started Feb 07 02:16:11 PM PST 24
Finished Feb 07 02:16:15 PM PST 24
Peak memory 202556 kb
Host smart-d7d80c75-8f6e-4089-88c5-7a55c21ce43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351418285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3351418285
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.4226476280
Short name T26
Test name
Test status
Simulation time 27130229 ps
CPU time 0.65 seconds
Started Feb 07 02:16:24 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 202264 kb
Host smart-0f5670f6-a1bf-470d-bd42-bc20443812c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226476280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.4226476280
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2141201691
Short name T19
Test name
Test status
Simulation time 223279994 ps
CPU time 1.3 seconds
Started Feb 07 02:16:08 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 202468 kb
Host smart-74a8b957-3979-4734-a949-e168ca643ce4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141201691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2141201691
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/29.i2c_host_override.2812980633
Short name T152
Test name
Test status
Simulation time 57177254 ps
CPU time 0.64 seconds
Started Feb 07 02:24:27 PM PST 24
Finished Feb 07 02:24:28 PM PST 24
Peak memory 202692 kb
Host smart-8a46e6c3-3daa-4c2c-ab62-82ad93c7bfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812980633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2812980633
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4109413337
Short name T40
Test name
Test status
Simulation time 5246090092 ps
CPU time 10.78 seconds
Started Feb 07 02:21:51 PM PST 24
Finished Feb 07 02:22:03 PM PST 24
Peak memory 235540 kb
Host smart-2e64dfe1-9a54-46ea-84da-526a6dce75c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109413337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4109413337
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1472932348
Short name T175
Test name
Test status
Simulation time 24439335149 ps
CPU time 2498.63 seconds
Started Feb 07 02:19:58 PM PST 24
Finished Feb 07 03:01:38 PM PST 24
Peak memory 2236696 kb
Host smart-8a405579-56d5-4e7e-b72b-8b7e550bbd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472932348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1472932348
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3988626606
Short name T52
Test name
Test status
Simulation time 760182756 ps
CPU time 3.9 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:38 PM PST 24
Peak memory 203924 kb
Host smart-278ce34e-75a1-4b03-a902-242567361f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988626606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3988626606
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2251315585
Short name T3
Test name
Test status
Simulation time 10126805104 ps
CPU time 51.3 seconds
Started Feb 07 02:22:24 PM PST 24
Finished Feb 07 02:23:16 PM PST 24
Peak memory 462220 kb
Host smart-031cf484-bdf9-4faf-8e5f-c0a18600412f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251315585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2251315585
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.2399336203
Short name T33
Test name
Test status
Simulation time 73486480107 ps
CPU time 2047.42 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:53:13 PM PST 24
Peak memory 3709288 kb
Host smart-3e501601-811b-482e-89dd-f506be3e4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399336203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.2399336203
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.4106764457
Short name T70
Test name
Test status
Simulation time 67348640 ps
CPU time 0.89 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:18:32 PM PST 24
Peak memory 220360 kb
Host smart-7f84e77c-4272-496b-abfd-6c2fbe32445f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106764457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.4106764457
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all_with_rand_reset.2840470628
Short name T84
Test name
Test status
Simulation time 10768788788 ps
CPU time 62.38 seconds
Started Feb 07 02:27:31 PM PST 24
Finished Feb 07 02:28:37 PM PST 24
Peak memory 260636 kb
Host smart-5b18a83a-934d-4ee0-9d58-b2b3cd9610d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840470628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.i2c_host_stress_all_with_rand_reset.2840470628
Directory /workspace/40.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1743663735
Short name T111
Test name
Test status
Simulation time 37139737 ps
CPU time 0.71 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:06 PM PST 24
Peak memory 202416 kb
Host smart-98a0ac6d-952d-48a0-bdec-07adc65584a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743663735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1743663735
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.2545774904
Short name T159
Test name
Test status
Simulation time 22650076403 ps
CPU time 46.73 seconds
Started Feb 07 02:23:48 PM PST 24
Finished Feb 07 02:24:38 PM PST 24
Peak memory 214836 kb
Host smart-5310bade-a14c-4818-b342-09b38891de91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545774904 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.2545774904
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3690759862
Short name T263
Test name
Test status
Simulation time 68202184 ps
CPU time 0.6 seconds
Started Feb 07 02:20:35 PM PST 24
Finished Feb 07 02:20:36 PM PST 24
Peak memory 203240 kb
Host smart-dbdd930c-2792-46c1-8755-e6e4ff548e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690759862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3690759862
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.499392551
Short name T293
Test name
Test status
Simulation time 1117042567 ps
CPU time 4.58 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:37 PM PST 24
Peak memory 203688 kb
Host smart-ba4847a0-93d9-451d-918d-989f91a23e85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499392551 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.499392551
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3138841323
Short name T201
Test name
Test status
Simulation time 870126703 ps
CPU time 0.88 seconds
Started Feb 07 02:20:16 PM PST 24
Finished Feb 07 02:20:18 PM PST 24
Peak memory 203352 kb
Host smart-2bc60cb2-cca3-4c66-bc07-5b9aa76aef5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138841323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3138841323
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.169422527
Short name T164
Test name
Test status
Simulation time 88768713 ps
CPU time 1.3 seconds
Started Feb 07 02:16:10 PM PST 24
Finished Feb 07 02:16:13 PM PST 24
Peak memory 202488 kb
Host smart-1e150855-2e72-4f2a-99e5-00282a9eeda7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169422527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.169422527
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3423540805
Short name T154
Test name
Test status
Simulation time 6078772954 ps
CPU time 25.16 seconds
Started Feb 07 02:23:18 PM PST 24
Finished Feb 07 02:23:45 PM PST 24
Peak memory 221276 kb
Host smart-238e2e38-812e-4d6a-958b-9aa81b6a1564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423540805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3423540805
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_target_tx_ovf.1526790544
Short name T14
Test name
Test status
Simulation time 12327012499 ps
CPU time 204.45 seconds
Started Feb 07 02:24:22 PM PST 24
Finished Feb 07 02:27:47 PM PST 24
Peak memory 453276 kb
Host smart-e6d671ec-7b52-40ae-a58e-5c61afdb6a1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526790544 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_tx_ovf.1526790544
Directory /workspace/28.i2c_target_tx_ovf/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1606744236
Short name T191
Test name
Test status
Simulation time 22672536 ps
CPU time 0.64 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:16 PM PST 24
Peak memory 202260 kb
Host smart-c6e3452a-c018-45db-ba17-5762c76bbd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606744236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1606744236
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2732690530
Short name T1161
Test name
Test status
Simulation time 1413724504 ps
CPU time 2.14 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 203584 kb
Host smart-d3bffeb5-57fd-43c8-9d39-3d4478302397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732690530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2732690530
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.3106332674
Short name T178
Test name
Test status
Simulation time 8499395313 ps
CPU time 164.98 seconds
Started Feb 07 02:25:05 PM PST 24
Finished Feb 07 02:27:51 PM PST 24
Peak memory 268892 kb
Host smart-6c64503a-776e-4b8c-9698-148abd417718
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106332674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample
.3106332674
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.377846664
Short name T10
Test name
Test status
Simulation time 785983578 ps
CPU time 10 seconds
Started Feb 07 02:27:54 PM PST 24
Finished Feb 07 02:28:06 PM PST 24
Peak memory 232680 kb
Host smart-6420f6de-7b41-4aab-940d-82f038b205da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377846664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
377846664
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3636196780
Short name T53
Test name
Test status
Simulation time 35643459414 ps
CPU time 2722.82 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 03:03:57 PM PST 24
Peak memory 7427772 kb
Host smart-67e4e149-cac0-403f-aae3-91878f093a19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636196780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3636196780
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.2360393081
Short name T42
Test name
Test status
Simulation time 22181639856 ps
CPU time 379.87 seconds
Started Feb 07 02:20:41 PM PST 24
Finished Feb 07 02:27:01 PM PST 24
Peak memory 638904 kb
Host smart-838e6c30-b95d-4740-85c3-bf571650d4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360393081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2360393081
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.54035939
Short name T69
Test name
Test status
Simulation time 293741217 ps
CPU time 1.72 seconds
Started Feb 07 02:15:56 PM PST 24
Finished Feb 07 02:15:59 PM PST 24
Peak memory 202520 kb
Host smart-43dbf9f0-606e-4d72-bb4b-604a12df9aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54035939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.54035939
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.858771170
Short name T81
Test name
Test status
Simulation time 105899020 ps
CPU time 1.81 seconds
Started Feb 07 02:16:19 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202584 kb
Host smart-9602ab6e-dfff-44e5-a42b-79f4deb74f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858771170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.858771170
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3799241732
Short name T119
Test name
Test status
Simulation time 18188844 ps
CPU time 0.7 seconds
Started Feb 07 02:16:19 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202268 kb
Host smart-b4ca1589-a9e6-4f26-9db9-cee8126741dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799241732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3799241732
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2488744955
Short name T166
Test name
Test status
Simulation time 7843325358 ps
CPU time 62.95 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:19:38 PM PST 24
Peak memory 261652 kb
Host smart-6b1f406b-be91-4123-a318-881c7475ada8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488744955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2488744955
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2631102232
Short name T1193
Test name
Test status
Simulation time 10128362276 ps
CPU time 9.45 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:43 PM PST 24
Peak memory 260656 kb
Host smart-5c0815c4-181b-4171-8e12-3fb5d810ed66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631102232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2631102232
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2872330121
Short name T1100
Test name
Test status
Simulation time 1208793428 ps
CPU time 2.24 seconds
Started Feb 07 02:20:17 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 203604 kb
Host smart-de3366bd-7028-4a2d-80e1-f19cfc980005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872330121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2872330121
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.3458688557
Short name T170
Test name
Test status
Simulation time 1249767600 ps
CPU time 4.92 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:23:12 PM PST 24
Peak memory 204256 kb
Host smart-7aedb998-cb92-405c-8278-473a980507a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458688557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_target_unexp_stop.3458688557
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2253161642
Short name T980
Test name
Test status
Simulation time 29963844529 ps
CPU time 1970.44 seconds
Started Feb 07 02:23:15 PM PST 24
Finished Feb 07 02:56:09 PM PST 24
Peak memory 1039960 kb
Host smart-107f6421-bc91-4367-be1d-a6f273a859cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253161642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2253161642
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2723731799
Short name T203
Test name
Test status
Simulation time 404464732 ps
CPU time 0.99 seconds
Started Feb 07 02:25:11 PM PST 24
Finished Feb 07 02:25:13 PM PST 24
Peak memory 203532 kb
Host smart-6f50c54f-9a4a-44c9-af8a-2c63c4b92aff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723731799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2723731799
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1340438914
Short name T195
Test name
Test status
Simulation time 10057642378 ps
CPU time 60.65 seconds
Started Feb 07 02:25:12 PM PST 24
Finished Feb 07 02:26:13 PM PST 24
Peak memory 527296 kb
Host smart-86a6b1de-69f0-435c-8896-201b5c127a4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340438914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1340438914
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.737884390
Short name T77
Test name
Test status
Simulation time 227668691 ps
CPU time 1.19 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:20 PM PST 24
Peak memory 202548 kb
Host smart-058e69f7-0f0b-4f46-b840-af567251ed96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737884390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.737884390
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1908038219
Short name T63
Test name
Test status
Simulation time 10062770549 ps
CPU time 23.53 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:56 PM PST 24
Peak memory 340536 kb
Host smart-a9e7c0a6-f55b-4e6a-8509-b4ca6f57608b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908038219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1908038219
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1021720538
Short name T1634
Test name
Test status
Simulation time 60232446 ps
CPU time 0.9 seconds
Started Feb 07 02:16:02 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 202352 kb
Host smart-42216652-58e9-426a-b302-2e505fe432bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021720538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1021720538
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1304811746
Short name T1599
Test name
Test status
Simulation time 286051201 ps
CPU time 4.06 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 202460 kb
Host smart-4c138219-4bd5-4385-8947-8f91df1d0130
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304811746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1304811746
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3035898480
Short name T23
Test name
Test status
Simulation time 58363613 ps
CPU time 0.74 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202312 kb
Host smart-5d26613d-29fe-4d53-8007-20fe28d894a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035898480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3035898480
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1230203742
Short name T1562
Test name
Test status
Simulation time 54398662 ps
CPU time 0.69 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202448 kb
Host smart-6511657b-4474-4855-8e77-76e2d8b2eea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230203742 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1230203742
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.4186542139
Short name T113
Test name
Test status
Simulation time 43987439 ps
CPU time 0.65 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202352 kb
Host smart-f78eb86e-db80-4bca-a765-a532366fd8e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186542139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.4186542139
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1264878255
Short name T1633
Test name
Test status
Simulation time 25083534 ps
CPU time 0.65 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 200352 kb
Host smart-42e6d402-bd7c-4cc6-b1f2-798274879e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264878255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1264878255
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1063914614
Short name T1598
Test name
Test status
Simulation time 33322329 ps
CPU time 0.75 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:06 PM PST 24
Peak memory 202368 kb
Host smart-23415b95-eb14-4078-a00b-426110169621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063914614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1063914614
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2500051264
Short name T1584
Test name
Test status
Simulation time 137903177 ps
CPU time 1.84 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:09 PM PST 24
Peak memory 202584 kb
Host smart-badfad2a-a785-4d8b-a6ed-4eb67c5bb3a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500051264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2500051264
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3349221726
Short name T115
Test name
Test status
Simulation time 63433827 ps
CPU time 0.9 seconds
Started Feb 07 02:16:07 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 202244 kb
Host smart-a61f47cf-ceb6-4960-80aa-2296ad7c1186
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349221726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3349221726
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.898134693
Short name T1572
Test name
Test status
Simulation time 150188142 ps
CPU time 2.46 seconds
Started Feb 07 02:16:10 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 202556 kb
Host smart-4e421fbf-d963-420c-b4e3-65acabaff676
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898134693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.898134693
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1726153666
Short name T1606
Test name
Test status
Simulation time 16163209 ps
CPU time 0.63 seconds
Started Feb 07 02:16:11 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 201156 kb
Host smart-fe6f666a-4fa7-4ea9-8c3e-f0493e480b8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726153666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1726153666
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.289312643
Short name T67
Test name
Test status
Simulation time 35256300 ps
CPU time 1.03 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 202472 kb
Host smart-e0c8bd7c-3d1f-44cb-be3c-3ca7a1caa3f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289312643 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.289312643
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3437320687
Short name T1582
Test name
Test status
Simulation time 29034056 ps
CPU time 0.73 seconds
Started Feb 07 02:16:12 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 202336 kb
Host smart-927f4f3d-13c8-4778-83d5-f6c08e236e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437320687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3437320687
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1090081775
Short name T1577
Test name
Test status
Simulation time 105183123 ps
CPU time 0.64 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202268 kb
Host smart-caec9d5d-e16b-4016-a458-14e827575895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090081775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1090081775
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4007350615
Short name T1607
Test name
Test status
Simulation time 19876077 ps
CPU time 0.78 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:06 PM PST 24
Peak memory 202408 kb
Host smart-b83d6895-af01-4c24-9ea2-71ae6ba58c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007350615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.4007350615
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2168652988
Short name T1591
Test name
Test status
Simulation time 333685117 ps
CPU time 1.4 seconds
Started Feb 07 02:16:13 PM PST 24
Finished Feb 07 02:16:15 PM PST 24
Peak memory 202580 kb
Host smart-8ae1152d-e01c-4c47-bbf2-6dbb6557b062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168652988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2168652988
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2027222947
Short name T80
Test name
Test status
Simulation time 88621544 ps
CPU time 1.24 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 202556 kb
Host smart-faf00d98-5916-4286-87b4-9b7ec51e3c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027222947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2027222947
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1586093056
Short name T1601
Test name
Test status
Simulation time 25565546 ps
CPU time 0.79 seconds
Started Feb 07 02:16:19 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202476 kb
Host smart-781863ed-5a2f-49c1-9da3-97767586e0f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586093056 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1586093056
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1935056544
Short name T1568
Test name
Test status
Simulation time 35021201 ps
CPU time 0.65 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:17 PM PST 24
Peak memory 201872 kb
Host smart-62bbfda5-5a66-4458-ad7c-76abc9d834e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935056544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1935056544
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1081973011
Short name T1590
Test name
Test status
Simulation time 73681093 ps
CPU time 0.61 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:16 PM PST 24
Peak memory 202308 kb
Host smart-4cac5a79-46c9-406e-b698-d999594e4f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081973011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1081973011
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2632223744
Short name T1604
Test name
Test status
Simulation time 330677567 ps
CPU time 0.82 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202340 kb
Host smart-7c9346a9-ca1c-4c8c-820b-60bd6877385e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632223744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2632223744
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2062482939
Short name T106
Test name
Test status
Simulation time 516480671 ps
CPU time 2.49 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:25 PM PST 24
Peak memory 202616 kb
Host smart-4c38d5ff-b9d3-47c5-a35a-eda7825898cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062482939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2062482939
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3429380289
Short name T165
Test name
Test status
Simulation time 125838452 ps
CPU time 1.88 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202560 kb
Host smart-48acdcfb-0aec-48a7-9dd5-4b05e2aefcb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429380289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3429380289
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3603335074
Short name T136
Test name
Test status
Simulation time 19108257 ps
CPU time 0.73 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202424 kb
Host smart-cf5555cf-7d8f-4288-b6ca-1c3b265b766f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603335074 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3603335074
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.296808004
Short name T109
Test name
Test status
Simulation time 19870522 ps
CPU time 0.65 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:20 PM PST 24
Peak memory 202316 kb
Host smart-6625261b-b2fe-4b86-900f-159b724f1fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296808004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.296808004
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1867831927
Short name T1561
Test name
Test status
Simulation time 17217709 ps
CPU time 0.65 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202292 kb
Host smart-df5df541-773c-4ef4-8b79-4400217a8865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867831927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1867831927
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1684768105
Short name T1597
Test name
Test status
Simulation time 51220999 ps
CPU time 0.8 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:21 PM PST 24
Peak memory 202336 kb
Host smart-326b8fc8-724e-4989-b6b2-0aba517eeaf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684768105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1684768105
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2930021385
Short name T1642
Test name
Test status
Simulation time 203605657 ps
CPU time 1.45 seconds
Started Feb 07 02:16:19 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202660 kb
Host smart-ef87cf8a-8fe5-4e1d-b13e-3eb04c973150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930021385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2930021385
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2161195406
Short name T1625
Test name
Test status
Simulation time 46384672 ps
CPU time 1.17 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202660 kb
Host smart-918ad5ff-76f1-49dd-9304-9650094d3140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161195406 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2161195406
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3055212787
Short name T1563
Test name
Test status
Simulation time 58854210 ps
CPU time 0.74 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202192 kb
Host smart-db5fe6f3-94c0-404e-9943-dd801ae88660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055212787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3055212787
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1495380097
Short name T1616
Test name
Test status
Simulation time 19221301 ps
CPU time 0.78 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202352 kb
Host smart-d4be09c9-acbf-44d4-b388-0add96339454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495380097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1495380097
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2975895371
Short name T1578
Test name
Test status
Simulation time 367138803 ps
CPU time 1.9 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202532 kb
Host smart-b50c8aad-5cad-490e-a761-db6d927f6c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975895371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2975895371
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.996766393
Short name T105
Test name
Test status
Simulation time 410704610 ps
CPU time 1.97 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202536 kb
Host smart-74118481-472f-4892-a67a-0d5981a47f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996766393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.996766393
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.198359577
Short name T1559
Test name
Test status
Simulation time 83385150 ps
CPU time 1.12 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202596 kb
Host smart-3062fae7-cc81-46ed-8bae-27e22e6fdb9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198359577 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.198359577
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.4129456718
Short name T103
Test name
Test status
Simulation time 46616595 ps
CPU time 0.62 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 201744 kb
Host smart-cfa4af61-2fc2-44e1-b1f7-b7302c4b36ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129456718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.4129456718
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1421928880
Short name T1586
Test name
Test status
Simulation time 17797466 ps
CPU time 0.71 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202252 kb
Host smart-b66d159d-5f3e-4090-aced-cbc2d40ff44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421928880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1421928880
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2898122355
Short name T21
Test name
Test status
Simulation time 103449635 ps
CPU time 0.82 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:21 PM PST 24
Peak memory 202364 kb
Host smart-bac3c0c4-0331-40be-985f-37af250e25ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898122355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2898122355
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.705892543
Short name T1576
Test name
Test status
Simulation time 91026407 ps
CPU time 1.38 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202592 kb
Host smart-9816372b-ba5c-4fd8-9617-6b199a66081f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705892543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.705892543
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1424301983
Short name T1621
Test name
Test status
Simulation time 33039958 ps
CPU time 0.92 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:17 PM PST 24
Peak memory 202412 kb
Host smart-d1bce198-4b60-4c36-8b2e-3a6259512ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424301983 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1424301983
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4059910709
Short name T117
Test name
Test status
Simulation time 15041660 ps
CPU time 0.64 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202348 kb
Host smart-e55dec74-c65e-40fb-a0ac-f289b688db47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059910709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4059910709
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3651110942
Short name T1566
Test name
Test status
Simulation time 17351401 ps
CPU time 0.69 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:17 PM PST 24
Peak memory 202292 kb
Host smart-a7beb50d-f9e2-43bb-97d4-021e204e657a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651110942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3651110942
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2672141149
Short name T1609
Test name
Test status
Simulation time 29964913 ps
CPU time 0.74 seconds
Started Feb 07 02:16:21 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202352 kb
Host smart-671a6748-ea19-46e5-aaf6-f8be0b6c77ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672141149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2672141149
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1503583803
Short name T1580
Test name
Test status
Simulation time 61408306 ps
CPU time 1.42 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:21 PM PST 24
Peak memory 202548 kb
Host smart-4c751e17-b771-404f-b128-d7bd301992b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503583803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1503583803
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1545079216
Short name T79
Test name
Test status
Simulation time 311577683 ps
CPU time 1.7 seconds
Started Feb 07 02:16:19 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202588 kb
Host smart-485fb95c-fb24-4667-a80a-ee94a907c729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545079216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1545079216
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4090489338
Short name T1558
Test name
Test status
Simulation time 142243325 ps
CPU time 0.69 seconds
Started Feb 07 02:16:19 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202444 kb
Host smart-122b3e5a-5976-478a-a3fa-3f4de25b3274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090489338 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.4090489338
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2766593228
Short name T1552
Test name
Test status
Simulation time 29592663 ps
CPU time 0.64 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:21 PM PST 24
Peak memory 201712 kb
Host smart-dd57d138-70c2-478d-9d0c-263d8b2204a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766593228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2766593228
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2036680664
Short name T1635
Test name
Test status
Simulation time 18996025 ps
CPU time 0.76 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:21 PM PST 24
Peak memory 202316 kb
Host smart-01ca282e-fb24-4325-be5c-d1e13d10335a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036680664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2036680664
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2119362419
Short name T1613
Test name
Test status
Simulation time 146281816 ps
CPU time 1.45 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:20 PM PST 24
Peak memory 202592 kb
Host smart-1871815a-d231-44fa-8d44-2221195279d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119362419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2119362419
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1024462291
Short name T1628
Test name
Test status
Simulation time 455471361 ps
CPU time 1.93 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202500 kb
Host smart-f33dfa41-52f8-41c8-b084-4ec4032775b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024462291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1024462291
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4182384723
Short name T25
Test name
Test status
Simulation time 71015644 ps
CPU time 0.84 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:21 PM PST 24
Peak memory 202388 kb
Host smart-3e26afdc-56d5-496b-b287-dd660cb8584b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182384723 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4182384723
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.80596583
Short name T1593
Test name
Test status
Simulation time 20033828 ps
CPU time 0.65 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 201496 kb
Host smart-088358af-d849-48f7-b6d4-c829ed32c111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80596583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.80596583
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2551145036
Short name T120
Test name
Test status
Simulation time 51818366 ps
CPU time 0.65 seconds
Started Feb 07 02:16:13 PM PST 24
Finished Feb 07 02:16:16 PM PST 24
Peak memory 202308 kb
Host smart-5dbdcd83-be72-42cb-a9f9-58f160db72d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551145036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2551145036
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3636550943
Short name T129
Test name
Test status
Simulation time 53134796 ps
CPU time 1.05 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202504 kb
Host smart-c398a6ca-edc5-4061-b3e9-64080fca0c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636550943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3636550943
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.242030851
Short name T1619
Test name
Test status
Simulation time 181040144 ps
CPU time 1.88 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202556 kb
Host smart-a821b629-a22b-48bf-b29b-c8c8744b03c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242030851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.242030851
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.323314616
Short name T1592
Test name
Test status
Simulation time 82969362 ps
CPU time 1.21 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:17 PM PST 24
Peak memory 202568 kb
Host smart-15dfd859-e2cd-4ab0-a24b-6292c8ea7b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323314616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.323314616
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.867658889
Short name T1573
Test name
Test status
Simulation time 79957202 ps
CPU time 0.84 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202496 kb
Host smart-7123ae31-7517-4403-a5d4-b0874c07a595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867658889 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.867658889
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.537040274
Short name T1555
Test name
Test status
Simulation time 50283962 ps
CPU time 0.62 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:16 PM PST 24
Peak memory 202340 kb
Host smart-8fbd08fa-7eba-4f3f-9c8a-77b626f97326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537040274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.537040274
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.661147237
Short name T193
Test name
Test status
Simulation time 97054795 ps
CPU time 0.63 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202300 kb
Host smart-482f472f-47d9-422f-8a16-11bb011a5a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661147237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.661147237
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3690485972
Short name T1643
Test name
Test status
Simulation time 88269698 ps
CPU time 0.73 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202380 kb
Host smart-ea6ef7b4-d268-4395-abf4-30e0b300ff81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690485972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3690485972
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3802648201
Short name T20
Test name
Test status
Simulation time 72673819 ps
CPU time 1.76 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202548 kb
Host smart-a3ce0e5b-ad88-4863-b4cb-f3bfea40c701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802648201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3802648201
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3700506877
Short name T135
Test name
Test status
Simulation time 97753814 ps
CPU time 1.03 seconds
Started Feb 07 02:16:24 PM PST 24
Finished Feb 07 02:16:28 PM PST 24
Peak memory 202496 kb
Host smart-1c4acd68-8eb4-4dfb-a118-e56bf440148a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700506877 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3700506877
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1233632898
Short name T114
Test name
Test status
Simulation time 19166685 ps
CPU time 0.68 seconds
Started Feb 07 02:16:25 PM PST 24
Finished Feb 07 02:16:31 PM PST 24
Peak memory 202324 kb
Host smart-1aaa7773-c052-488f-9d05-910433660d9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233632898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1233632898
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3827413397
Short name T124
Test name
Test status
Simulation time 71829835 ps
CPU time 0.97 seconds
Started Feb 07 02:16:26 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 202524 kb
Host smart-418bb4f0-d4ed-48f1-b1df-19627cc13648
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827413397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3827413397
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.464439860
Short name T1569
Test name
Test status
Simulation time 229249745 ps
CPU time 2.33 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202600 kb
Host smart-239abac6-55ff-449a-bd33-8bfb18c87a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464439860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.464439860
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4180278175
Short name T78
Test name
Test status
Simulation time 49120142 ps
CPU time 1.21 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202584 kb
Host smart-12f8fcda-4f4f-4b20-8061-6483cc2d6144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180278175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.4180278175
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3167543732
Short name T1550
Test name
Test status
Simulation time 46501606 ps
CPU time 0.89 seconds
Started Feb 07 02:16:24 PM PST 24
Finished Feb 07 02:16:28 PM PST 24
Peak memory 202396 kb
Host smart-8a0c135b-c760-43d3-93a8-cc0c7bdfc8fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167543732 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3167543732
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3716084790
Short name T1623
Test name
Test status
Simulation time 29401049 ps
CPU time 0.66 seconds
Started Feb 07 02:16:23 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 202344 kb
Host smart-7b0e40bb-8293-4381-a6dd-581f3696caba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716084790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3716084790
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.573955532
Short name T1596
Test name
Test status
Simulation time 37638747 ps
CPU time 0.63 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202324 kb
Host smart-3c6853ce-372a-4ab2-8aad-769aeafe70ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573955532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.573955532
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2756271931
Short name T126
Test name
Test status
Simulation time 67885494 ps
CPU time 0.85 seconds
Started Feb 07 02:16:23 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 202388 kb
Host smart-104868f8-a4ee-4340-9882-c79e27539abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756271931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2756271931
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3918183099
Short name T1603
Test name
Test status
Simulation time 60284604 ps
CPU time 1.21 seconds
Started Feb 07 02:16:28 PM PST 24
Finished Feb 07 02:16:34 PM PST 24
Peak memory 202592 kb
Host smart-f2981118-f382-4a31-8c72-0c77ac6c4fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918183099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3918183099
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1973356162
Short name T76
Test name
Test status
Simulation time 152228518 ps
CPU time 1.24 seconds
Started Feb 07 02:16:26 PM PST 24
Finished Feb 07 02:16:33 PM PST 24
Peak memory 202528 kb
Host smart-d2901f83-0dde-41e6-9c29-caf642e74880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973356162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1973356162
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2694220738
Short name T22
Test name
Test status
Simulation time 1107800959 ps
CPU time 4.06 seconds
Started Feb 07 02:16:05 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 202592 kb
Host smart-b9a77246-b661-4eeb-9e00-c1d4e2ae29dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694220738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2694220738
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2211789240
Short name T1611
Test name
Test status
Simulation time 63299281 ps
CPU time 0.7 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:09 PM PST 24
Peak memory 202136 kb
Host smart-3a5ab294-b428-4261-8307-cf19f951d3df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211789240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2211789240
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.583765263
Short name T121
Test name
Test status
Simulation time 26668944 ps
CPU time 0.82 seconds
Started Feb 07 02:16:08 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 202500 kb
Host smart-48298487-0d9a-4e2b-b639-2d324e172a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583765263 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.583765263
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3210104176
Short name T107
Test name
Test status
Simulation time 62992677 ps
CPU time 0.69 seconds
Started Feb 07 02:16:07 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 202324 kb
Host smart-9408f359-a9e2-4bb2-a824-7ed719aebe88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210104176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3210104176
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3808904315
Short name T1574
Test name
Test status
Simulation time 44662749 ps
CPU time 0.67 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202268 kb
Host smart-856c0dba-039a-43ef-8155-e1c8aceee41d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808904315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3808904315
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3407332277
Short name T130
Test name
Test status
Simulation time 96446062 ps
CPU time 0.77 seconds
Started Feb 07 02:16:09 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 202356 kb
Host smart-8bb1abc0-ae7d-465e-9cf1-de6addfbec73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407332277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3407332277
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.807572023
Short name T1638
Test name
Test status
Simulation time 173399065 ps
CPU time 1.24 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202640 kb
Host smart-85df541a-61b0-446a-ab64-1e63958af4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807572023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.807572023
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3384161458
Short name T73
Test name
Test status
Simulation time 107171871 ps
CPU time 1.83 seconds
Started Feb 07 02:16:02 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 202568 kb
Host smart-cd14e2dc-b8c3-4011-bc2e-48dd75765557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384161458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3384161458
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1910197775
Short name T1589
Test name
Test status
Simulation time 137400909 ps
CPU time 0.68 seconds
Started Feb 07 02:16:26 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 202224 kb
Host smart-aaeb752b-9577-4493-8f1d-d639d2486e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910197775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1910197775
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3989236096
Short name T1581
Test name
Test status
Simulation time 17489794 ps
CPU time 0.67 seconds
Started Feb 07 02:16:24 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 202304 kb
Host smart-ce847ffe-0843-4fe5-aba3-b9cf052e10bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989236096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3989236096
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1979873386
Short name T1548
Test name
Test status
Simulation time 16678234 ps
CPU time 0.68 seconds
Started Feb 07 02:16:26 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 202224 kb
Host smart-66f572db-9706-45d3-b7b5-aa3d9bf85518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979873386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1979873386
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1752792823
Short name T1571
Test name
Test status
Simulation time 14607219 ps
CPU time 0.68 seconds
Started Feb 07 02:16:23 PM PST 24
Finished Feb 07 02:16:26 PM PST 24
Peak memory 202312 kb
Host smart-249271f3-e506-4909-ad0a-71c563103765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752792823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1752792823
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2420508294
Short name T1600
Test name
Test status
Simulation time 15150146 ps
CPU time 0.64 seconds
Started Feb 07 02:16:21 PM PST 24
Finished Feb 07 02:16:24 PM PST 24
Peak memory 202360 kb
Host smart-30cb504f-df21-4fdd-a15d-b7cdb2220732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420508294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2420508294
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.124243615
Short name T187
Test name
Test status
Simulation time 22046281 ps
CPU time 0.69 seconds
Started Feb 07 02:16:26 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 202236 kb
Host smart-a0ade192-4ea9-41dc-a139-4df424d4ec86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124243615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.124243615
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3389906652
Short name T24
Test name
Test status
Simulation time 62539244 ps
CPU time 0.67 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 202272 kb
Host smart-7e49dfb6-2c3d-40e7-b565-d9ab23776bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389906652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3389906652
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.271050800
Short name T1614
Test name
Test status
Simulation time 79484957 ps
CPU time 0.71 seconds
Started Feb 07 02:16:23 PM PST 24
Finished Feb 07 02:16:26 PM PST 24
Peak memory 202296 kb
Host smart-b10468ec-3a08-4609-a7da-dc070516a475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271050800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.271050800
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2688700122
Short name T1615
Test name
Test status
Simulation time 63514730 ps
CPU time 0.67 seconds
Started Feb 07 02:16:24 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 202288 kb
Host smart-ae8d3e0a-d869-43b3-b6d3-279109e03723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688700122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2688700122
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.933966887
Short name T138
Test name
Test status
Simulation time 39229335 ps
CPU time 0.68 seconds
Started Feb 07 02:16:26 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 202276 kb
Host smart-fd839726-0b29-4441-8e18-5034aa79e231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933966887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.933966887
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1531090664
Short name T116
Test name
Test status
Simulation time 139620394 ps
CPU time 1.23 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 202524 kb
Host smart-95713508-2814-4e4c-810b-bba9a8ffb2b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531090664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1531090664
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.102391884
Short name T1588
Test name
Test status
Simulation time 1166073212 ps
CPU time 4.19 seconds
Started Feb 07 02:16:08 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 202624 kb
Host smart-2107870d-03cd-4316-adb3-19f1c840367c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102391884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.102391884
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3520629369
Short name T1579
Test name
Test status
Simulation time 17815750 ps
CPU time 0.64 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:03 PM PST 24
Peak memory 201172 kb
Host smart-5df30e55-bb42-401f-81af-f597cd61a27a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520629369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3520629369
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.947609799
Short name T1624
Test name
Test status
Simulation time 35338989 ps
CPU time 0.92 seconds
Started Feb 07 02:15:59 PM PST 24
Finished Feb 07 02:16:01 PM PST 24
Peak memory 202388 kb
Host smart-d35c3975-07ce-4316-900a-470d02d1bcfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947609799 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.947609799
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1414656817
Short name T127
Test name
Test status
Simulation time 19162242 ps
CPU time 0.7 seconds
Started Feb 07 02:16:08 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 201896 kb
Host smart-87d382ff-45e9-4145-b8c7-d8d07fb591ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414656817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1414656817
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.636446469
Short name T1565
Test name
Test status
Simulation time 62085046 ps
CPU time 0.67 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202276 kb
Host smart-1b9c92ad-8472-4e7f-9f13-e861d5105cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636446469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.636446469
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1560517115
Short name T1636
Test name
Test status
Simulation time 28114966 ps
CPU time 0.78 seconds
Started Feb 07 02:16:05 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 202384 kb
Host smart-6c8777b6-88f5-4d08-a410-c452c7e23212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560517115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1560517115
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1981451986
Short name T1622
Test name
Test status
Simulation time 145848587 ps
CPU time 2.67 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:04 PM PST 24
Peak memory 202572 kb
Host smart-8e8ea11b-bc57-40d5-bd21-c5207d7cfafb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981451986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1981451986
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.61280696
Short name T1556
Test name
Test status
Simulation time 80248757 ps
CPU time 0.66 seconds
Started Feb 07 02:16:21 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202256 kb
Host smart-7f3990e3-0c2f-4dc2-ab46-76ab48ecc029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61280696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.61280696
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2354566727
Short name T137
Test name
Test status
Simulation time 23241149 ps
CPU time 0.63 seconds
Started Feb 07 02:16:20 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202312 kb
Host smart-425fd873-c00a-4f08-b116-2c7a5afba9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354566727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2354566727
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.825536048
Short name T1553
Test name
Test status
Simulation time 28049710 ps
CPU time 0.67 seconds
Started Feb 07 02:16:22 PM PST 24
Finished Feb 07 02:16:25 PM PST 24
Peak memory 202248 kb
Host smart-44e55121-8991-448c-82cf-2aab9f1a6b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825536048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.825536048
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2065786064
Short name T1551
Test name
Test status
Simulation time 41321138 ps
CPU time 0.68 seconds
Started Feb 07 02:16:22 PM PST 24
Finished Feb 07 02:16:26 PM PST 24
Peak memory 202264 kb
Host smart-b452d228-d7a6-4526-afaf-c277d8e84884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065786064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2065786064
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.955142831
Short name T1575
Test name
Test status
Simulation time 24914494 ps
CPU time 0.69 seconds
Started Feb 07 02:16:27 PM PST 24
Finished Feb 07 02:16:33 PM PST 24
Peak memory 202288 kb
Host smart-6b894e8c-ff35-4e51-88ec-15d678fcd695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955142831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.955142831
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.273882602
Short name T1640
Test name
Test status
Simulation time 21978322 ps
CPU time 0.67 seconds
Started Feb 07 02:16:25 PM PST 24
Finished Feb 07 02:16:31 PM PST 24
Peak memory 202268 kb
Host smart-bea3e247-c74a-441b-9656-46dde41b4c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273882602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.273882602
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.4115310060
Short name T1637
Test name
Test status
Simulation time 73681167 ps
CPU time 0.65 seconds
Started Feb 07 02:16:24 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 202264 kb
Host smart-4d7541cd-dc0d-45dc-8b52-85fd7e176100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115310060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.4115310060
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.4004962152
Short name T60
Test name
Test status
Simulation time 48901700 ps
CPU time 0.65 seconds
Started Feb 07 02:16:27 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 202228 kb
Host smart-d7382a85-aa6c-4c1d-aca5-f7346426ee87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004962152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.4004962152
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3081876912
Short name T1549
Test name
Test status
Simulation time 27525206 ps
CPU time 0.67 seconds
Started Feb 07 02:16:25 PM PST 24
Finished Feb 07 02:16:31 PM PST 24
Peak memory 202260 kb
Host smart-6815c060-cb69-4d02-b3dc-5155902031cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081876912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3081876912
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3390642497
Short name T1608
Test name
Test status
Simulation time 44444108 ps
CPU time 0.63 seconds
Started Feb 07 02:16:25 PM PST 24
Finished Feb 07 02:16:28 PM PST 24
Peak memory 202264 kb
Host smart-e331c27d-71ee-4fb6-8030-d2d8057cb62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390642497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3390642497
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3659574042
Short name T110
Test name
Test status
Simulation time 23976751 ps
CPU time 0.92 seconds
Started Feb 07 02:16:10 PM PST 24
Finished Feb 07 02:16:13 PM PST 24
Peak memory 202392 kb
Host smart-2d4832f8-1097-47a6-8ec7-f87339c1de6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659574042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3659574042
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2945189671
Short name T1620
Test name
Test status
Simulation time 900822115 ps
CPU time 4.54 seconds
Started Feb 07 02:16:07 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 202532 kb
Host smart-b53c2d9e-57bd-4bc6-8f50-2380cffdb97d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945189671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2945189671
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.164578894
Short name T1610
Test name
Test status
Simulation time 70176048 ps
CPU time 0.7 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:17 PM PST 24
Peak memory 202356 kb
Host smart-54c57e76-4186-4751-ba9b-6e7766b842b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164578894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.164578894
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3373480412
Short name T104
Test name
Test status
Simulation time 42820932 ps
CPU time 1.12 seconds
Started Feb 07 02:16:08 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 202596 kb
Host smart-fb0518c9-efb1-4d9f-b4dd-4de05eb52401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373480412 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3373480412
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1977346553
Short name T1560
Test name
Test status
Simulation time 42073761 ps
CPU time 0.72 seconds
Started Feb 07 02:16:10 PM PST 24
Finished Feb 07 02:16:13 PM PST 24
Peak memory 202328 kb
Host smart-a26ff138-94e8-4216-8a21-a4e6ec359ea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977346553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1977346553
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3621382567
Short name T1630
Test name
Test status
Simulation time 17174238 ps
CPU time 0.69 seconds
Started Feb 07 02:16:02 PM PST 24
Finished Feb 07 02:16:04 PM PST 24
Peak memory 202312 kb
Host smart-f0177712-6671-4eb5-a916-020934b4ce7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621382567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3621382567
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.107815319
Short name T1567
Test name
Test status
Simulation time 63985873 ps
CPU time 1.02 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 202528 kb
Host smart-4838644d-3c37-49c6-9553-df0379fbe136
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107815319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.107815319
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2500548839
Short name T1627
Test name
Test status
Simulation time 145112758 ps
CPU time 2.09 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:04 PM PST 24
Peak memory 202536 kb
Host smart-5a1b7c20-f47e-4190-96e5-4ebe8bebf0fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500548839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2500548839
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.206735537
Short name T83
Test name
Test status
Simulation time 267439917 ps
CPU time 1.89 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:09 PM PST 24
Peak memory 202528 kb
Host smart-1384bbf3-31ba-4d1c-9fdf-2f40a7f2cb08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206735537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.206735537
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.1456175316
Short name T1626
Test name
Test status
Simulation time 27238007 ps
CPU time 0.72 seconds
Started Feb 07 02:16:27 PM PST 24
Finished Feb 07 02:16:33 PM PST 24
Peak memory 202292 kb
Host smart-2d350ddb-4ded-4a5b-acdf-f8617aa7ddf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456175316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1456175316
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2656979603
Short name T1594
Test name
Test status
Simulation time 91529338 ps
CPU time 0.7 seconds
Started Feb 07 02:16:27 PM PST 24
Finished Feb 07 02:16:33 PM PST 24
Peak memory 202288 kb
Host smart-36f7e0b3-d915-4772-a227-97f35c6b77da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656979603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2656979603
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1456912814
Short name T190
Test name
Test status
Simulation time 65295837 ps
CPU time 0.68 seconds
Started Feb 07 02:16:23 PM PST 24
Finished Feb 07 02:16:26 PM PST 24
Peak memory 202312 kb
Host smart-ba7061a1-cd19-4db1-935e-7938d041e7cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456912814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1456912814
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3260174120
Short name T1583
Test name
Test status
Simulation time 15591678 ps
CPU time 0.64 seconds
Started Feb 07 02:16:23 PM PST 24
Finished Feb 07 02:16:26 PM PST 24
Peak memory 202312 kb
Host smart-30607553-6ba8-4c55-92e3-f52aa5ee30fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260174120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3260174120
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.913407485
Short name T1554
Test name
Test status
Simulation time 46948071 ps
CPU time 0.61 seconds
Started Feb 07 02:16:21 PM PST 24
Finished Feb 07 02:16:24 PM PST 24
Peak memory 202300 kb
Host smart-8ca68b10-4e5a-43ce-8638-37b2ad5ec676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913407485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.913407485
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1547995426
Short name T1602
Test name
Test status
Simulation time 50846841 ps
CPU time 0.62 seconds
Started Feb 07 02:16:25 PM PST 24
Finished Feb 07 02:16:31 PM PST 24
Peak memory 202280 kb
Host smart-82166c1c-2d67-4cf0-87a8-be4dee525af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547995426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1547995426
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.536725919
Short name T118
Test name
Test status
Simulation time 28526284 ps
CPU time 0.69 seconds
Started Feb 07 02:16:27 PM PST 24
Finished Feb 07 02:16:34 PM PST 24
Peak memory 202292 kb
Host smart-fd79a361-1ce0-4f9c-9a5b-86543eae9790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536725919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.536725919
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.967796659
Short name T1632
Test name
Test status
Simulation time 16376277 ps
CPU time 0.66 seconds
Started Feb 07 02:16:27 PM PST 24
Finished Feb 07 02:16:33 PM PST 24
Peak memory 202296 kb
Host smart-424d2fe1-c1ab-4187-9d00-97b50834d258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967796659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.967796659
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2228715034
Short name T1617
Test name
Test status
Simulation time 61678141 ps
CPU time 0.64 seconds
Started Feb 07 02:16:21 PM PST 24
Finished Feb 07 02:16:24 PM PST 24
Peak memory 202304 kb
Host smart-06a92816-bba0-48ba-baf7-8d424109e878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228715034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2228715034
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.772737724
Short name T134
Test name
Test status
Simulation time 45655794 ps
CPU time 0.93 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 202420 kb
Host smart-14249eb4-27a7-495a-8c47-be8b55833ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772737724 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.772737724
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.337344754
Short name T1629
Test name
Test status
Simulation time 60895119 ps
CPU time 0.68 seconds
Started Feb 07 02:16:08 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 201652 kb
Host smart-b61b3a72-5e08-4dcb-881e-c86c45a963c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337344754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.337344754
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2777583622
Short name T1595
Test name
Test status
Simulation time 40629379 ps
CPU time 0.64 seconds
Started Feb 07 02:16:09 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 202272 kb
Host smart-3ccbe705-f563-4f89-ab4b-67d1c6626971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777583622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2777583622
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1743557258
Short name T128
Test name
Test status
Simulation time 43183703 ps
CPU time 0.93 seconds
Started Feb 07 02:16:04 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 202288 kb
Host smart-07b36626-faad-4cf6-baa7-2b2f55ecfc78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743557258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1743557258
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.557781076
Short name T1644
Test name
Test status
Simulation time 229852416 ps
CPU time 1.26 seconds
Started Feb 07 02:16:15 PM PST 24
Finished Feb 07 02:16:18 PM PST 24
Peak memory 202540 kb
Host smart-2796111b-9ceb-451f-9c7c-b92f36a0c72d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557781076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.557781076
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3942484157
Short name T1612
Test name
Test status
Simulation time 23625697 ps
CPU time 0.82 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 202428 kb
Host smart-f9d07878-05ae-4c32-b44e-1a9072a84890
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942484157 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3942484157
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.586395386
Short name T112
Test name
Test status
Simulation time 49926244 ps
CPU time 0.65 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:06 PM PST 24
Peak memory 201576 kb
Host smart-c0d19f4b-6828-40b1-bdae-7987c7fc7cd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586395386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.586395386
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.118874497
Short name T1639
Test name
Test status
Simulation time 132707443 ps
CPU time 0.66 seconds
Started Feb 07 02:16:12 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 202300 kb
Host smart-7417479d-7f42-405b-8ce4-4d07c707526c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118874497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.118874497
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.400151550
Short name T125
Test name
Test status
Simulation time 29333561 ps
CPU time 0.75 seconds
Started Feb 07 02:16:09 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 202368 kb
Host smart-ae6773dd-a8d3-46f2-b9e0-26295cfccdfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400151550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.400151550
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.293245442
Short name T1587
Test name
Test status
Simulation time 28914928 ps
CPU time 1.41 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:07 PM PST 24
Peak memory 202620 kb
Host smart-2bf860dc-9366-40d3-89f6-e744914ffd90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293245442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.293245442
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.807780775
Short name T82
Test name
Test status
Simulation time 190023628 ps
CPU time 1.82 seconds
Started Feb 07 02:16:21 PM PST 24
Finished Feb 07 02:16:25 PM PST 24
Peak memory 202524 kb
Host smart-e8b70b50-6268-4723-96f9-0394ef5796f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807780775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.807780775
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2650103098
Short name T1570
Test name
Test status
Simulation time 39688540 ps
CPU time 1.06 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:20 PM PST 24
Peak memory 202272 kb
Host smart-dcbd7b86-df6c-4e20-9e2d-22e3e8c1f027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650103098 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2650103098
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1233758360
Short name T108
Test name
Test status
Simulation time 23400406 ps
CPU time 0.69 seconds
Started Feb 07 02:16:05 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 202304 kb
Host smart-e7ca41d7-87e2-4372-bf92-32a5cd3e404f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233758360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1233758360
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3758283664
Short name T1631
Test name
Test status
Simulation time 18124425 ps
CPU time 0.67 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:06 PM PST 24
Peak memory 202364 kb
Host smart-f2b36f9d-4ce3-4515-82a9-d1b578289a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758283664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3758283664
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3847691859
Short name T1641
Test name
Test status
Simulation time 77870914 ps
CPU time 0.95 seconds
Started Feb 07 02:16:02 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 202428 kb
Host smart-0c10f34d-b049-444c-b860-49d6c98c3b41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847691859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3847691859
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3494357350
Short name T75
Test name
Test status
Simulation time 553755268 ps
CPU time 2.29 seconds
Started Feb 07 02:16:18 PM PST 24
Finished Feb 07 02:16:23 PM PST 24
Peak memory 202592 kb
Host smart-85e412f8-318c-43a0-8eab-47ff84a6e4c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494357350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3494357350
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3071808277
Short name T1618
Test name
Test status
Simulation time 69286421 ps
CPU time 1.29 seconds
Started Feb 07 02:16:14 PM PST 24
Finished Feb 07 02:16:17 PM PST 24
Peak memory 202532 kb
Host smart-2eae9ed7-0336-4cce-b3dc-05e01f3ed999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071808277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3071808277
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1503099041
Short name T1645
Test name
Test status
Simulation time 49257470 ps
CPU time 0.88 seconds
Started Feb 07 02:16:16 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 202496 kb
Host smart-71e7dd81-2a3a-4d31-bd83-b9ee98da5221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503099041 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1503099041
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1623614552
Short name T122
Test name
Test status
Simulation time 20475794 ps
CPU time 0.74 seconds
Started Feb 07 02:16:02 PM PST 24
Finished Feb 07 02:16:06 PM PST 24
Peak memory 202364 kb
Host smart-a5ef014d-6b2a-47f0-ae70-188a246a4f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623614552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1623614552
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1291741730
Short name T1557
Test name
Test status
Simulation time 26472546 ps
CPU time 0.89 seconds
Started Feb 07 02:16:12 PM PST 24
Finished Feb 07 02:16:14 PM PST 24
Peak memory 202392 kb
Host smart-93a26a79-197b-4543-ba46-10adc20a8f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291741730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1291741730
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.370792603
Short name T68
Test name
Test status
Simulation time 36255775 ps
CPU time 1.87 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:04 PM PST 24
Peak memory 202516 kb
Host smart-2f14f5cf-d04e-4fd4-872b-e047190c84bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370792603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.370792603
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2688219118
Short name T86
Test name
Test status
Simulation time 304978224 ps
CPU time 1.3 seconds
Started Feb 07 02:16:09 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 202568 kb
Host smart-077952e9-5f02-4ada-a06c-4da0de94188f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688219118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2688219118
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2268933852
Short name T1605
Test name
Test status
Simulation time 28038717 ps
CPU time 0.89 seconds
Started Feb 07 02:16:13 PM PST 24
Finished Feb 07 02:16:15 PM PST 24
Peak memory 202452 kb
Host smart-40c5b373-0a58-4854-9f86-54ae91453d41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268933852 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2268933852
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1327778633
Short name T123
Test name
Test status
Simulation time 63210303 ps
CPU time 0.68 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:19 PM PST 24
Peak memory 201396 kb
Host smart-988e2514-9a95-45d1-a9ea-7eafc6b0f71f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327778633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1327778633
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2502752308
Short name T205
Test name
Test status
Simulation time 30042580 ps
CPU time 0.65 seconds
Started Feb 07 02:16:09 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 202356 kb
Host smart-6603f925-50da-4902-a5fa-a31e68e888f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502752308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2502752308
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4013276407
Short name T1585
Test name
Test status
Simulation time 97053444 ps
CPU time 1.07 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 202600 kb
Host smart-08baacc7-3313-4db1-98d8-9bfc0ccf32f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013276407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.4013276407
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1485873530
Short name T1564
Test name
Test status
Simulation time 76065828 ps
CPU time 1.05 seconds
Started Feb 07 02:16:17 PM PST 24
Finished Feb 07 02:16:20 PM PST 24
Peak memory 202428 kb
Host smart-575c7ec4-28eb-4c74-9e5e-9d53a93429c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485873530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1485873530
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.233865278
Short name T87
Test name
Test status
Simulation time 148213702 ps
CPU time 1.83 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 202528 kb
Host smart-f5bb54ef-493f-42db-946c-bd5dab1fc588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233865278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.233865278
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1299271425
Short name T1183
Test name
Test status
Simulation time 26635840 ps
CPU time 0.59 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:32 PM PST 24
Peak memory 202420 kb
Host smart-1110f33e-4ff3-4374-9de8-611e443c1b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299271425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1299271425
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3656323056
Short name T818
Test name
Test status
Simulation time 140463226 ps
CPU time 1.23 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:37 PM PST 24
Peak memory 219956 kb
Host smart-49ed905f-cb8b-47ef-89ae-193a8aa2d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656323056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3656323056
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3232156429
Short name T899
Test name
Test status
Simulation time 462752102 ps
CPU time 8.56 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:40 PM PST 24
Peak memory 306280 kb
Host smart-60d7724b-b72f-4f62-9879-328d008b3060
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232156429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3232156429
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.4005129124
Short name T1388
Test name
Test status
Simulation time 3799597537 ps
CPU time 107.49 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:20:19 PM PST 24
Peak memory 914236 kb
Host smart-00f4ea74-5296-4929-bf2b-a9be06a24b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005129124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.4005129124
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.4276310078
Short name T901
Test name
Test status
Simulation time 5194003484 ps
CPU time 149.43 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:21:01 PM PST 24
Peak memory 945276 kb
Host smart-2f866374-fd07-4528-9011-fdea612ab995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276310078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.4276310078
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.989709864
Short name T568
Test name
Test status
Simulation time 477843652 ps
CPU time 1.2 seconds
Started Feb 07 02:18:28 PM PST 24
Finished Feb 07 02:18:30 PM PST 24
Peak memory 203520 kb
Host smart-6151242d-09f8-4e60-866d-b8c239fb05b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989709864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.989709864
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2590259034
Short name T1314
Test name
Test status
Simulation time 174368285 ps
CPU time 3.72 seconds
Started Feb 07 02:18:29 PM PST 24
Finished Feb 07 02:18:33 PM PST 24
Peak memory 203612 kb
Host smart-560b148f-241c-4086-8ae1-3866b9f149ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590259034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2590259034
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1732271430
Short name T673
Test name
Test status
Simulation time 42791109244 ps
CPU time 375.93 seconds
Started Feb 07 02:18:28 PM PST 24
Finished Feb 07 02:24:45 PM PST 24
Peak memory 1860956 kb
Host smart-f3d6602d-0dda-4e1a-b1e0-1737d6acfbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732271430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1732271430
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1097618274
Short name T831
Test name
Test status
Simulation time 2368793192 ps
CPU time 116.05 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:20:29 PM PST 24
Peak memory 228328 kb
Host smart-f503937c-1926-476c-9a2c-e399d132e11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097618274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1097618274
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.2268658068
Short name T562
Test name
Test status
Simulation time 47602945 ps
CPU time 0.6 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:33 PM PST 24
Peak memory 202572 kb
Host smart-121a8509-ef03-4e2c-bd9c-10a7beff4434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268658068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2268658068
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.9251286
Short name T1307
Test name
Test status
Simulation time 9862045906 ps
CPU time 98.35 seconds
Started Feb 07 02:18:25 PM PST 24
Finished Feb 07 02:20:05 PM PST 24
Peak memory 287836 kb
Host smart-fd86b9eb-0f55-4dbd-b6ba-63abb6861d14
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9251286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.9251286
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.4256596820
Short name T1391
Test name
Test status
Simulation time 10484996193 ps
CPU time 103.2 seconds
Started Feb 07 02:18:25 PM PST 24
Finished Feb 07 02:20:09 PM PST 24
Peak memory 352144 kb
Host smart-d23f3f1c-518f-4f99-b98a-76b26d285bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256596820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.4256596820
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2634738781
Short name T189
Test name
Test status
Simulation time 40744034181 ps
CPU time 3335.19 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 03:14:11 PM PST 24
Peak memory 3859204 kb
Host smart-22d51636-f2ea-4ac8-a16c-4f0640b5befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634738781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2634738781
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all_with_rand_reset.2721190374
Short name T85
Test name
Test status
Simulation time 37865947216 ps
CPU time 1153.54 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:37:45 PM PST 24
Peak memory 1663752 kb
Host smart-b1a25b88-67c8-46fc-aaaa-ce339a6d80a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721190374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.i2c_host_stress_all_with_rand_reset.2721190374
Directory /workspace/0.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.326894637
Short name T1209
Test name
Test status
Simulation time 2006236199 ps
CPU time 16.31 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:48 PM PST 24
Peak memory 218236 kb
Host smart-75785d19-b7df-4950-af2c-58ca9716da1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326894637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.326894637
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.558856052
Short name T1373
Test name
Test status
Simulation time 10190151474 ps
CPU time 43 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 462516 kb
Host smart-3b31d260-d8de-4427-b199-ea6d905bf327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558856052 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.558856052
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2111585920
Short name T1279
Test name
Test status
Simulation time 9085519390 ps
CPU time 2.76 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 203628 kb
Host smart-454e3e98-e728-44c1-92b4-a4484e078419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111585920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2111585920
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1007428852
Short name T1489
Test name
Test status
Simulation time 4257270291 ps
CPU time 7.54 seconds
Started Feb 07 02:18:29 PM PST 24
Finished Feb 07 02:18:37 PM PST 24
Peak memory 208828 kb
Host smart-d1c436ab-df02-4ec4-bf79-790a3b8f96b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007428852 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1007428852
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.330707405
Short name T1310
Test name
Test status
Simulation time 18985665151 ps
CPU time 744.22 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:31:00 PM PST 24
Peak memory 4575340 kb
Host smart-5d3b8991-bc7f-4768-89be-d910bd2dc3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330707405 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.330707405
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.2618432670
Short name T1445
Test name
Test status
Simulation time 602372617 ps
CPU time 3.55 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:18:35 PM PST 24
Peak memory 203536 kb
Host smart-b535b298-9c07-43f9-88a7-12af3f62ad97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618432670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.2618432670
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.4063692619
Short name T751
Test name
Test status
Simulation time 1173167930 ps
CPU time 31.71 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:19:07 PM PST 24
Peak memory 203620 kb
Host smart-019cc552-3383-4af2-a8f5-028e4ef5915a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063692619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.4063692619
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.2427884510
Short name T1451
Test name
Test status
Simulation time 143690651588 ps
CPU time 101.77 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:20:16 PM PST 24
Peak memory 245960 kb
Host smart-e9aac7de-0fe7-44dd-95a1-d57f14610704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427884510 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.2427884510
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3289810266
Short name T1294
Test name
Test status
Simulation time 2164564577 ps
CPU time 88.21 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:20:03 PM PST 24
Peak memory 204068 kb
Host smart-596dae67-adb9-4267-b2c2-f5c15d330dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289810266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3289810266
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1490056414
Short name T1102
Test name
Test status
Simulation time 10419112712 ps
CPU time 21.06 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:54 PM PST 24
Peak memory 639268 kb
Host smart-9f9a9c85-93c3-4cd1-a38f-13c648b58cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490056414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1490056414
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.76043602
Short name T1092
Test name
Test status
Simulation time 1449572300 ps
CPU time 6.34 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:18:37 PM PST 24
Peak memory 208168 kb
Host smart-12f4a66a-af0e-4893-a91f-9db2d8f28667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76043602 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_timeout.76043602
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_ovf.2800983375
Short name T1500
Test name
Test status
Simulation time 24976455677 ps
CPU time 142.71 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:20:58 PM PST 24
Peak memory 438392 kb
Host smart-ba4907f8-58fd-420a-8e7b-3b75a564f230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800983375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_tx_ovf.2800983375
Directory /workspace/0.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.1337605938
Short name T880
Test name
Test status
Simulation time 3228758808 ps
CPU time 6.83 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:39 PM PST 24
Peak memory 209584 kb
Host smart-e6c8c288-12e8-49fd-872f-a0cd8d164d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337605938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.1337605938
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1398476424
Short name T1037
Test name
Test status
Simulation time 41583557 ps
CPU time 0.59 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:33 PM PST 24
Peak memory 203244 kb
Host smart-82099453-4312-47eb-8eff-2b234d3e16e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398476424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1398476424
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.26658254
Short name T1040
Test name
Test status
Simulation time 55817789 ps
CPU time 1.42 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:33 PM PST 24
Peak memory 220020 kb
Host smart-204d70b7-7a2b-4fc6-bcdd-429d1c6c1e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26658254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.26658254
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3894447471
Short name T1031
Test name
Test status
Simulation time 341693870 ps
CPU time 6.43 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:39 PM PST 24
Peak memory 274852 kb
Host smart-6db48980-3538-44b9-a997-4b42c616556b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894447471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3894447471
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.514881000
Short name T1081
Test name
Test status
Simulation time 13535700768 ps
CPU time 367.83 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:24:39 PM PST 24
Peak memory 1181412 kb
Host smart-68014635-5e60-4381-a154-c83a8283218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514881000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.514881000
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3564626291
Short name T1197
Test name
Test status
Simulation time 5300352562 ps
CPU time 311.84 seconds
Started Feb 07 02:18:28 PM PST 24
Finished Feb 07 02:23:40 PM PST 24
Peak memory 1472536 kb
Host smart-ec478901-c969-435b-9c0b-fd012ca8f384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564626291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3564626291
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2133548329
Short name T49
Test name
Test status
Simulation time 170793205 ps
CPU time 0.84 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:33 PM PST 24
Peak memory 203352 kb
Host smart-bdb9f06d-efed-4b10-bd15-149792fd2493
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133548329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2133548329
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2985221402
Short name T1273
Test name
Test status
Simulation time 192295838 ps
CPU time 5.54 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:40 PM PST 24
Peak memory 237236 kb
Host smart-7ffd646b-c98d-4650-91a8-8c684a868eb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985221402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2985221402
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3306989694
Short name T842
Test name
Test status
Simulation time 7003874508 ps
CPU time 861.67 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:32:55 PM PST 24
Peak memory 1864368 kb
Host smart-e9eb4db2-5bce-41ea-862b-459985136424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306989694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3306989694
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2362026758
Short name T788
Test name
Test status
Simulation time 22906689994 ps
CPU time 66.1 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:19:41 PM PST 24
Peak memory 326224 kb
Host smart-868b16b2-eecd-433e-a302-3fd6b2055c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362026758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2362026758
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3670981699
Short name T596
Test name
Test status
Simulation time 28884455 ps
CPU time 0.61 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:32 PM PST 24
Peak memory 202604 kb
Host smart-e2aadd27-178e-4fef-b9bc-f89537675549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670981699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3670981699
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.235660129
Short name T378
Test name
Test status
Simulation time 18125418535 ps
CPU time 926.79 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:33:59 PM PST 24
Peak memory 306820 kb
Host smart-8b2a990d-1fc8-400f-a061-a8ce8cafa183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235660129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.235660129
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.944013981
Short name T34
Test name
Test status
Simulation time 2642607950 ps
CPU time 237.18 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:22:29 PM PST 24
Peak memory 303128 kb
Host smart-de136a0b-b3b9-4155-beaf-205b320518b8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944013981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.944013981
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.460007196
Short name T1127
Test name
Test status
Simulation time 11449452943 ps
CPU time 58.05 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:19:34 PM PST 24
Peak memory 272260 kb
Host smart-15c85558-7a23-41b3-95d5-79b533bfc1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460007196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.460007196
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.712580584
Short name T1195
Test name
Test status
Simulation time 16906512861 ps
CPU time 1720.24 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:47:13 PM PST 24
Peak memory 4044400 kb
Host smart-9a6c179c-ec10-4de8-8381-21f999298df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712580584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.712580584
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2257840740
Short name T1068
Test name
Test status
Simulation time 1343980376 ps
CPU time 18.75 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:53 PM PST 24
Peak memory 211848 kb
Host smart-d214d6cb-73e0-498c-9d67-9a25c4be9641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257840740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2257840740
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2971640086
Short name T92
Test name
Test status
Simulation time 69493395 ps
CPU time 0.83 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:35 PM PST 24
Peak memory 220176 kb
Host smart-1321f840-ed11-4f1a-a555-bc7dd91c8557
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971640086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2971640086
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.826921135
Short name T1091
Test name
Test status
Simulation time 1210515631 ps
CPU time 5.03 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:39 PM PST 24
Peak memory 203628 kb
Host smart-0bd3395f-d3a9-4ba5-8a2a-b6bf873187f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826921135 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.826921135
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1176344355
Short name T744
Test name
Test status
Simulation time 10568275210 ps
CPU time 8.42 seconds
Started Feb 07 02:18:35 PM PST 24
Finished Feb 07 02:18:45 PM PST 24
Peak memory 282588 kb
Host smart-3548aec1-9317-4069-be02-970989b5d113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176344355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1176344355
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1978959364
Short name T51
Test name
Test status
Simulation time 848200192 ps
CPU time 4.07 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 203848 kb
Host smart-2112b8cc-0489-45fb-9a86-671a2dd34dc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978959364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1978959364
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.493582991
Short name T172
Test name
Test status
Simulation time 385727385 ps
CPU time 2.16 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:38 PM PST 24
Peak memory 203676 kb
Host smart-2747ac08-2f2d-4e83-9ce4-7f3b03726749
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493582991 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.493582991
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2199248303
Short name T250
Test name
Test status
Simulation time 4475162601 ps
CPU time 4.73 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:39 PM PST 24
Peak memory 207800 kb
Host smart-2433b47f-3bd0-4f26-9d8a-da5720c275bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199248303 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2199248303
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.796108155
Short name T1088
Test name
Test status
Simulation time 18503421944 ps
CPU time 45.39 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:19:21 PM PST 24
Peak memory 707840 kb
Host smart-eb6c4884-46ea-4569-8957-d4e358430434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796108155 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.796108155
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.2223472071
Short name T1021
Test name
Test status
Simulation time 933176540 ps
CPU time 3.28 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:38 PM PST 24
Peak memory 203588 kb
Host smart-396e71c1-5738-4a41-8c1e-0e894dbac1a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223472071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.2223472071
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1919174768
Short name T893
Test name
Test status
Simulation time 6088157090 ps
CPU time 19.54 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:54 PM PST 24
Peak memory 203736 kb
Host smart-717940c9-46b5-4ffa-b529-7c893126da6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919174768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1919174768
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.2943955618
Short name T742
Test name
Test status
Simulation time 193630703476 ps
CPU time 707.83 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:30:23 PM PST 24
Peak memory 2853500 kb
Host smart-fd5acf6b-74fa-48c9-80c6-23ce4e1df26e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943955618 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.2943955618
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2424803351
Short name T1120
Test name
Test status
Simulation time 10247271859 ps
CPU time 38.11 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:19:11 PM PST 24
Peak memory 223720 kb
Host smart-2e625d44-08c8-4f89-a6f6-162c8d72087a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424803351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2424803351
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2814182769
Short name T732
Test name
Test status
Simulation time 23058305605 ps
CPU time 578.67 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:28:12 PM PST 24
Peak memory 4739800 kb
Host smart-dfcfedb9-3c64-490f-9a8d-a8e72ec7da1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814182769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2814182769
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3596527076
Short name T1101
Test name
Test status
Simulation time 15925770218 ps
CPU time 898.53 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:33:32 PM PST 24
Peak memory 3919964 kb
Host smart-ece35f55-a213-4360-bc4e-849e0e7b2e2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596527076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3596527076
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2834631427
Short name T435
Test name
Test status
Simulation time 7346683245 ps
CPU time 7.22 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:41 PM PST 24
Peak memory 203804 kb
Host smart-a37d4870-3a10-40c1-a93e-3593dfbe4147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834631427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2834631427
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_ovf.4076358155
Short name T1536
Test name
Test status
Simulation time 13275417036 ps
CPU time 75.5 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:19:51 PM PST 24
Peak memory 303580 kb
Host smart-a5e16886-8135-43fa-8c4b-75a8a390c901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076358155 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_tx_ovf.4076358155
Directory /workspace/1.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.982233903
Short name T1469
Test name
Test status
Simulation time 7381266436 ps
CPU time 9.32 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:41 PM PST 24
Peak memory 203792 kb
Host smart-bf64d3cd-d002-4f96-8b10-9895b12d6822
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982233903 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_unexp_stop.982233903
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3882946932
Short name T749
Test name
Test status
Simulation time 17789941 ps
CPU time 0.6 seconds
Started Feb 07 02:20:03 PM PST 24
Finished Feb 07 02:20:05 PM PST 24
Peak memory 202376 kb
Host smart-88aded48-c2ab-4897-b894-9f2f55ed511b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882946932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3882946932
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1697561905
Short name T857
Test name
Test status
Simulation time 40188434 ps
CPU time 1.27 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:03 PM PST 24
Peak memory 219648 kb
Host smart-cb424e76-a187-4b52-ae01-0664a1ece915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697561905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1697561905
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3262352
Short name T298
Test name
Test status
Simulation time 463121341 ps
CPU time 23.03 seconds
Started Feb 07 02:19:51 PM PST 24
Finished Feb 07 02:20:14 PM PST 24
Peak memory 275776 kb
Host smart-d8437f4b-7369-4c57-af5c-bc661e63662e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.3262352
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3633422932
Short name T968
Test name
Test status
Simulation time 2027140670 ps
CPU time 51.27 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 403520 kb
Host smart-45071ac2-28ca-4f18-b14f-84bc8185b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633422932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3633422932
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.671004613
Short name T1219
Test name
Test status
Simulation time 10783444180 ps
CPU time 638.74 seconds
Started Feb 07 02:19:51 PM PST 24
Finished Feb 07 02:30:31 PM PST 24
Peak memory 1523508 kb
Host smart-9ae497f6-4fcd-4afe-b1bb-46fe8be25a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671004613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.671004613
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.885871860
Short name T790
Test name
Test status
Simulation time 576929004 ps
CPU time 1.12 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:02 PM PST 24
Peak memory 203572 kb
Host smart-4fe51c61-143a-464e-abf6-41acce01771e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885871860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.885871860
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.4230819467
Short name T626
Test name
Test status
Simulation time 405375664 ps
CPU time 5.84 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:07 PM PST 24
Peak memory 242232 kb
Host smart-79bc0ea6-b9e2-4772-aaca-03c567916777
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230819467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.4230819467
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1121580810
Short name T1486
Test name
Test status
Simulation time 31845411806 ps
CPU time 458.7 seconds
Started Feb 07 02:19:50 PM PST 24
Finished Feb 07 02:27:29 PM PST 24
Peak memory 1792204 kb
Host smart-1788fe7e-b555-4739-8560-7bd3631d928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121580810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1121580810
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2268721555
Short name T1409
Test name
Test status
Simulation time 2266159344 ps
CPU time 97.65 seconds
Started Feb 07 02:19:58 PM PST 24
Finished Feb 07 02:21:37 PM PST 24
Peak memory 366644 kb
Host smart-82b77da5-56a0-463c-8132-add1aa2a76a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268721555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2268721555
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3213756269
Short name T369
Test name
Test status
Simulation time 18995470 ps
CPU time 0.64 seconds
Started Feb 07 02:19:54 PM PST 24
Finished Feb 07 02:19:55 PM PST 24
Peak memory 202584 kb
Host smart-6aaadc6c-0e53-4a94-bfb1-736773012575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213756269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3213756269
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3690332778
Short name T884
Test name
Test status
Simulation time 28481999461 ps
CPU time 437.59 seconds
Started Feb 07 02:19:54 PM PST 24
Finished Feb 07 02:27:12 PM PST 24
Peak memory 220112 kb
Host smart-947c037e-295d-47c8-b951-4be5b2e84d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690332778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3690332778
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.562072858
Short name T983
Test name
Test status
Simulation time 4385326994 ps
CPU time 94.13 seconds
Started Feb 07 02:19:55 PM PST 24
Finished Feb 07 02:21:30 PM PST 24
Peak memory 296276 kb
Host smart-80fa300e-391e-4a96-98b5-4222e8152492
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562072858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample.
562072858
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3544902442
Short name T783
Test name
Test status
Simulation time 5373391985 ps
CPU time 80.85 seconds
Started Feb 07 02:19:50 PM PST 24
Finished Feb 07 02:21:12 PM PST 24
Peak memory 347068 kb
Host smart-fa40af20-09a1-476c-bada-4a1ca6891531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544902442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3544902442
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2933721094
Short name T332
Test name
Test status
Simulation time 1617478427 ps
CPU time 11.8 seconds
Started Feb 07 02:19:56 PM PST 24
Finished Feb 07 02:20:09 PM PST 24
Peak memory 219876 kb
Host smart-26970065-71d6-4c5c-82a0-08de2658dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933721094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2933721094
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2469268630
Short name T38
Test name
Test status
Simulation time 9878098658 ps
CPU time 3.7 seconds
Started Feb 07 02:19:56 PM PST 24
Finished Feb 07 02:20:01 PM PST 24
Peak memory 203768 kb
Host smart-f2304946-b862-4007-9985-374bf13f8482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469268630 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2469268630
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3257434323
Short name T520
Test name
Test status
Simulation time 10151657096 ps
CPU time 65.56 seconds
Started Feb 07 02:20:03 PM PST 24
Finished Feb 07 02:21:10 PM PST 24
Peak memory 494056 kb
Host smart-3d285813-26df-48c1-8777-4c4f10112d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257434323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3257434323
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1711613408
Short name T544
Test name
Test status
Simulation time 10241512624 ps
CPU time 26.92 seconds
Started Feb 07 02:19:58 PM PST 24
Finished Feb 07 02:20:25 PM PST 24
Peak memory 361544 kb
Host smart-bfd0e996-39f9-4121-afec-06e1ebf647be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711613408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1711613408
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1068056430
Short name T1123
Test name
Test status
Simulation time 494742829 ps
CPU time 2.42 seconds
Started Feb 07 02:19:56 PM PST 24
Finished Feb 07 02:19:59 PM PST 24
Peak memory 203648 kb
Host smart-59590256-390b-4675-af68-295369481572
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068056430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1068056430
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.773308775
Short name T59
Test name
Test status
Simulation time 6891584826 ps
CPU time 6.72 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:07 PM PST 24
Peak memory 207932 kb
Host smart-f3a1eaf1-5297-49af-b1e9-88c32de62f8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773308775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.773308775
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2413308222
Short name T998
Test name
Test status
Simulation time 16446707948 ps
CPU time 500.82 seconds
Started Feb 07 02:19:58 PM PST 24
Finished Feb 07 02:28:19 PM PST 24
Peak memory 3948964 kb
Host smart-d817f607-89eb-4277-a0af-c54212173d09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413308222 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2413308222
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.3496844822
Short name T1258
Test name
Test status
Simulation time 3244948387 ps
CPU time 5.03 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:05 PM PST 24
Peak memory 213672 kb
Host smart-3cd591be-e352-4222-a5cf-77b63539f66a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496844822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.3496844822
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1431453108
Short name T387
Test name
Test status
Simulation time 971850867 ps
CPU time 24.37 seconds
Started Feb 07 02:19:55 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 203612 kb
Host smart-5ef90fbd-1a1f-4d82-8828-0fff031feb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431453108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1431453108
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.317769728
Short name T982
Test name
Test status
Simulation time 51791592346 ps
CPU time 102.44 seconds
Started Feb 07 02:19:57 PM PST 24
Finished Feb 07 02:21:40 PM PST 24
Peak memory 244684 kb
Host smart-2dbf0248-7bbe-49c9-a470-68d7ee5fb8cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317769728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_target_stress_all.317769728
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2818709412
Short name T711
Test name
Test status
Simulation time 560471672 ps
CPU time 8.26 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:20:10 PM PST 24
Peak memory 204536 kb
Host smart-8e4a9db5-8782-48df-82e6-938082219257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818709412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2818709412
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2209319613
Short name T1290
Test name
Test status
Simulation time 10244545930 ps
CPU time 88.66 seconds
Started Feb 07 02:20:03 PM PST 24
Finished Feb 07 02:21:33 PM PST 24
Peak memory 1588976 kb
Host smart-fb8eb727-afd3-469d-a3e8-802c2abed7af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209319613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2209319613
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2812966215
Short name T456
Test name
Test status
Simulation time 13399412835 ps
CPU time 67.6 seconds
Started Feb 07 02:19:58 PM PST 24
Finished Feb 07 02:21:07 PM PST 24
Peak memory 745068 kb
Host smart-d23008c0-b2a2-4ad7-af73-bf62e1a1bf84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812966215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2812966215
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1811404461
Short name T924
Test name
Test status
Simulation time 3607545518 ps
CPU time 7.41 seconds
Started Feb 07 02:19:58 PM PST 24
Finished Feb 07 02:20:06 PM PST 24
Peak memory 203740 kb
Host smart-08342355-c7f9-4056-b19d-b5c879437af2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811404461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1811404461
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_ovf.3843773346
Short name T506
Test name
Test status
Simulation time 5489974109 ps
CPU time 112.32 seconds
Started Feb 07 02:19:56 PM PST 24
Finished Feb 07 02:21:49 PM PST 24
Peak memory 343336 kb
Host smart-89335c24-d47e-4097-b9d5-53751b76380b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843773346 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_tx_ovf.3843773346
Directory /workspace/10.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.1388273370
Short name T1173
Test name
Test status
Simulation time 1136223614 ps
CPU time 6 seconds
Started Feb 07 02:19:57 PM PST 24
Finished Feb 07 02:20:04 PM PST 24
Peak memory 203536 kb
Host smart-4b6bd54c-02b3-430e-82f8-077d8136aea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388273370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.1388273370
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1336141186
Short name T1465
Test name
Test status
Simulation time 23518868 ps
CPU time 0.64 seconds
Started Feb 07 02:20:09 PM PST 24
Finished Feb 07 02:20:11 PM PST 24
Peak memory 202392 kb
Host smart-4ab87786-98b5-450a-b95c-d678e0441a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336141186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1336141186
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.483103043
Short name T1360
Test name
Test status
Simulation time 37388610 ps
CPU time 1.11 seconds
Started Feb 07 02:20:10 PM PST 24
Finished Feb 07 02:20:12 PM PST 24
Peak memory 211884 kb
Host smart-a7668faf-0ef9-4302-992f-02e9bccae132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483103043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.483103043
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.982794390
Short name T64
Test name
Test status
Simulation time 460885473 ps
CPU time 24.45 seconds
Started Feb 07 02:20:05 PM PST 24
Finished Feb 07 02:20:30 PM PST 24
Peak memory 301000 kb
Host smart-3938e9df-e668-4fed-9929-2082203b9320
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982794390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.982794390
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1258946524
Short name T669
Test name
Test status
Simulation time 20120149090 ps
CPU time 329.15 seconds
Started Feb 07 02:20:12 PM PST 24
Finished Feb 07 02:25:42 PM PST 24
Peak memory 1106544 kb
Host smart-7d97df5f-9f27-4181-bed6-0c2d53535a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258946524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1258946524
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3425706538
Short name T173
Test name
Test status
Simulation time 24301768017 ps
CPU time 814.02 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:33:43 PM PST 24
Peak memory 1669932 kb
Host smart-12d36043-72b6-4b7e-a1b9-c64c8a3d46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425706538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3425706538
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3982028611
Short name T875
Test name
Test status
Simulation time 123040458 ps
CPU time 0.99 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:20:10 PM PST 24
Peak memory 203544 kb
Host smart-f95d39cc-d3da-471d-960b-50a8c655d029
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982028611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3982028611
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1525656313
Short name T1414
Test name
Test status
Simulation time 360999642 ps
CPU time 10.13 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:20:19 PM PST 24
Peak memory 203636 kb
Host smart-ada1ea42-2a23-4197-8650-419904e33caf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525656313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1525656313
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2570985158
Short name T1268
Test name
Test status
Simulation time 35844789900 ps
CPU time 294.53 seconds
Started Feb 07 02:20:03 PM PST 24
Finished Feb 07 02:24:59 PM PST 24
Peak memory 1009028 kb
Host smart-d83093f8-ef5c-4fa6-8030-b7327c1ee427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570985158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2570985158
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.1585576347
Short name T622
Test name
Test status
Simulation time 1259263725 ps
CPU time 67.66 seconds
Started Feb 07 02:20:13 PM PST 24
Finished Feb 07 02:21:21 PM PST 24
Peak memory 244408 kb
Host smart-010f1cb1-5bbf-46b3-b5b4-721599f0d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585576347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1585576347
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.4066672405
Short name T619
Test name
Test status
Simulation time 34330025 ps
CPU time 0.63 seconds
Started Feb 07 02:20:03 PM PST 24
Finished Feb 07 02:20:05 PM PST 24
Peak memory 202612 kb
Host smart-79cf27f0-a7e8-4b07-a01e-5cde275d5987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066672405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.4066672405
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.750734395
Short name T1288
Test name
Test status
Simulation time 458580670 ps
CPU time 9.95 seconds
Started Feb 07 02:20:10 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 211804 kb
Host smart-a0cc7e00-b15a-4619-b078-585e4a2dae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750734395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.750734395
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.4040722316
Short name T1047
Test name
Test status
Simulation time 8886748457 ps
CPU time 128.35 seconds
Started Feb 07 02:19:57 PM PST 24
Finished Feb 07 02:22:06 PM PST 24
Peak memory 261684 kb
Host smart-65a64442-70d1-437c-8144-757f48717f2a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040722316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample
.4040722316
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2154423075
Short name T812
Test name
Test status
Simulation time 1789957721 ps
CPU time 90.15 seconds
Started Feb 07 02:20:03 PM PST 24
Finished Feb 07 02:21:34 PM PST 24
Peak memory 228156 kb
Host smart-105ae974-f680-4a79-a35f-77df9368fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154423075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2154423075
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1949856197
Short name T595
Test name
Test status
Simulation time 3247647840 ps
CPU time 14.3 seconds
Started Feb 07 02:20:10 PM PST 24
Finished Feb 07 02:20:25 PM PST 24
Peak memory 216620 kb
Host smart-90fc6584-08d8-4032-a6da-03dd14ef8f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949856197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1949856197
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3616582934
Short name T274
Test name
Test status
Simulation time 4248584407 ps
CPU time 4.39 seconds
Started Feb 07 02:20:13 PM PST 24
Finished Feb 07 02:20:18 PM PST 24
Peak memory 203740 kb
Host smart-7c03e11a-66b3-4af8-8277-5928fbda60f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616582934 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3616582934
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3475732078
Short name T339
Test name
Test status
Simulation time 10093567341 ps
CPU time 25.3 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:20:34 PM PST 24
Peak memory 342184 kb
Host smart-5bff09b2-739b-4dd4-8e55-f82e4a658188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475732078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3475732078
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1622468966
Short name T345
Test name
Test status
Simulation time 10118641093 ps
CPU time 66.64 seconds
Started Feb 07 02:20:11 PM PST 24
Finished Feb 07 02:21:18 PM PST 24
Peak memory 565968 kb
Host smart-7f115e67-8c99-44c7-b993-727f399c0054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622468966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1622468966
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1208622839
Short name T472
Test name
Test status
Simulation time 928261658 ps
CPU time 4.18 seconds
Started Feb 07 02:20:07 PM PST 24
Finished Feb 07 02:20:12 PM PST 24
Peak memory 203620 kb
Host smart-19a79cda-9bdb-43e6-93b0-5ea1300ef526
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208622839 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1208622839
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.739062449
Short name T1062
Test name
Test status
Simulation time 6733365146 ps
CPU time 13.45 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:20:23 PM PST 24
Peak memory 424212 kb
Host smart-fd25334d-e107-4f3d-924c-b92055fed6c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739062449 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.739062449
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.507826252
Short name T1295
Test name
Test status
Simulation time 650594326 ps
CPU time 3.8 seconds
Started Feb 07 02:20:13 PM PST 24
Finished Feb 07 02:20:17 PM PST 24
Peak memory 207560 kb
Host smart-ac8caf75-2926-449d-ae2f-36983ce2b493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507826252 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_perf.507826252
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.417356027
Short name T1111
Test name
Test status
Simulation time 2178246708 ps
CPU time 12.26 seconds
Started Feb 07 02:20:11 PM PST 24
Finished Feb 07 02:20:24 PM PST 24
Peak memory 203764 kb
Host smart-f5c1b4a6-97d6-4254-9606-d7bf3ba3eeba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417356027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.417356027
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.1985639759
Short name T1334
Test name
Test status
Simulation time 48742369819 ps
CPU time 153.09 seconds
Started Feb 07 02:20:15 PM PST 24
Finished Feb 07 02:22:49 PM PST 24
Peak memory 567588 kb
Host smart-a00029e9-aa16-443b-b957-b2984c2181b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985639759 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.1985639759
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2840604068
Short name T1374
Test name
Test status
Simulation time 2416651965 ps
CPU time 10.76 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 204284 kb
Host smart-e0d6dc18-8a1d-47b5-b7be-41f183319385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840604068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2840604068
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1080969742
Short name T483
Test name
Test status
Simulation time 34746533511 ps
CPU time 93.66 seconds
Started Feb 07 02:20:07 PM PST 24
Finished Feb 07 02:21:42 PM PST 24
Peak memory 1351708 kb
Host smart-b30e2480-e085-40b0-a58f-87a7568ff902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080969742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1080969742
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.4281751601
Short name T1266
Test name
Test status
Simulation time 15208456957 ps
CPU time 664.68 seconds
Started Feb 07 02:20:10 PM PST 24
Finished Feb 07 02:31:16 PM PST 24
Peak memory 3669220 kb
Host smart-3ee225ae-5ab2-4f0e-b39f-5ae03554d764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281751601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.4281751601
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2809670005
Short name T585
Test name
Test status
Simulation time 9380897165 ps
CPU time 7.06 seconds
Started Feb 07 02:20:08 PM PST 24
Finished Feb 07 02:20:16 PM PST 24
Peak memory 212316 kb
Host smart-8cfb2fb0-bb47-4bbd-bb3d-c218befebe25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809670005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2809670005
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_ovf.4071060176
Short name T1346
Test name
Test status
Simulation time 9353682302 ps
CPU time 46.23 seconds
Started Feb 07 02:20:09 PM PST 24
Finished Feb 07 02:20:56 PM PST 24
Peak memory 228052 kb
Host smart-3782e836-275e-4482-98e9-9d7a6cd70b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071060176 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_tx_ovf.4071060176
Directory /workspace/11.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.196625209
Short name T1324
Test name
Test status
Simulation time 3191936997 ps
CPU time 6.86 seconds
Started Feb 07 02:20:11 PM PST 24
Finished Feb 07 02:20:18 PM PST 24
Peak memory 203788 kb
Host smart-c37b4e2c-a3c4-45b9-a309-24468880c306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196625209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_unexp_stop.196625209
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.1463839656
Short name T484
Test name
Test status
Simulation time 36661883 ps
CPU time 1.14 seconds
Started Feb 07 02:20:27 PM PST 24
Finished Feb 07 02:20:29 PM PST 24
Peak memory 220008 kb
Host smart-6fb13ebc-4f78-428c-b890-87bb4724bc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463839656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1463839656
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3494414869
Short name T1404
Test name
Test status
Simulation time 1878198526 ps
CPU time 25.11 seconds
Started Feb 07 02:20:18 PM PST 24
Finished Feb 07 02:20:44 PM PST 24
Peak memory 306348 kb
Host smart-198288f7-4a53-4f7b-81ba-3850867a93e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494414869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3494414869
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1111928218
Short name T1221
Test name
Test status
Simulation time 15031947366 ps
CPU time 143.56 seconds
Started Feb 07 02:20:16 PM PST 24
Finished Feb 07 02:22:41 PM PST 24
Peak memory 1079004 kb
Host smart-be7fe672-1df2-429a-b177-46cbe94b299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111928218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1111928218
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2072683044
Short name T177
Test name
Test status
Simulation time 10183802096 ps
CPU time 372.06 seconds
Started Feb 07 02:20:11 PM PST 24
Finished Feb 07 02:26:24 PM PST 24
Peak memory 1118000 kb
Host smart-25dbbe08-8607-445b-93a6-f27c0e81d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072683044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2072683044
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.4276562695
Short name T730
Test name
Test status
Simulation time 254257038 ps
CPU time 14.46 seconds
Started Feb 07 02:20:18 PM PST 24
Finished Feb 07 02:20:33 PM PST 24
Peak memory 255400 kb
Host smart-272c9641-bee0-4268-89e5-0376c44a6cf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276562695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.4276562695
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2942386498
Short name T1505
Test name
Test status
Simulation time 7037867837 ps
CPU time 326.66 seconds
Started Feb 07 02:20:15 PM PST 24
Finished Feb 07 02:25:42 PM PST 24
Peak memory 1081840 kb
Host smart-29e8a06f-0715-40c1-afb5-fb2c5a1555e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942386498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2942386498
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1657931919
Short name T1452
Test name
Test status
Simulation time 1437857212 ps
CPU time 24.67 seconds
Started Feb 07 02:20:37 PM PST 24
Finished Feb 07 02:21:02 PM PST 24
Peak memory 242260 kb
Host smart-bac240ac-1f35-43af-b1f2-2ebcad94e070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657931919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1657931919
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3003296725
Short name T566
Test name
Test status
Simulation time 17828628 ps
CPU time 0.65 seconds
Started Feb 07 02:20:18 PM PST 24
Finished Feb 07 02:20:19 PM PST 24
Peak memory 202604 kb
Host smart-ff49a050-6c0e-47c3-91c6-f08069048032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003296725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3003296725
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3267857726
Short name T144
Test name
Test status
Simulation time 3328308947 ps
CPU time 12.51 seconds
Started Feb 07 02:20:18 PM PST 24
Finished Feb 07 02:20:31 PM PST 24
Peak memory 211932 kb
Host smart-6c9af059-42d5-4bc1-8c53-afa540d3da4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267857726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3267857726
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_rx_oversample.4265339741
Short name T1071
Test name
Test status
Simulation time 5966165233 ps
CPU time 243.93 seconds
Started Feb 07 02:20:17 PM PST 24
Finished Feb 07 02:24:22 PM PST 24
Peak memory 289128 kb
Host smart-2f369746-aedb-4bfd-9e02-5378b5ba4a60
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265339741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_rx_oversample
.4265339741
Directory /workspace/12.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2806113599
Short name T1359
Test name
Test status
Simulation time 3492955650 ps
CPU time 45.61 seconds
Started Feb 07 02:20:18 PM PST 24
Finished Feb 07 02:21:04 PM PST 24
Peak memory 275796 kb
Host smart-a253044c-91e8-41bd-a5cc-86c4de2ee978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806113599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2806113599
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3093639066
Short name T192
Test name
Test status
Simulation time 11615626147 ps
CPU time 1097.54 seconds
Started Feb 07 02:20:32 PM PST 24
Finished Feb 07 02:38:50 PM PST 24
Peak memory 1508132 kb
Host smart-be9c2cab-8cb0-4dfb-9c0e-94f764bbd101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093639066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3093639066
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2128084231
Short name T636
Test name
Test status
Simulation time 3739302427 ps
CPU time 10.18 seconds
Started Feb 07 02:20:26 PM PST 24
Finished Feb 07 02:20:37 PM PST 24
Peak memory 217652 kb
Host smart-6a357d88-3aaf-45f8-94b0-d4e35c665156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128084231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2128084231
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2080711412
Short name T445
Test name
Test status
Simulation time 3795865524 ps
CPU time 3.47 seconds
Started Feb 07 02:20:27 PM PST 24
Finished Feb 07 02:20:31 PM PST 24
Peak memory 203772 kb
Host smart-78eb12a3-269c-434f-aba8-6e4c0f568aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080711412 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2080711412
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1495353746
Short name T197
Test name
Test status
Simulation time 10162790731 ps
CPU time 22.64 seconds
Started Feb 07 02:20:36 PM PST 24
Finished Feb 07 02:20:59 PM PST 24
Peak memory 322416 kb
Host smart-14265b51-21d9-4e4f-9d50-24641a8fdf97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495353746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1495353746
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.972468618
Short name T1087
Test name
Test status
Simulation time 10275699806 ps
CPU time 31.09 seconds
Started Feb 07 02:20:27 PM PST 24
Finished Feb 07 02:20:59 PM PST 24
Peak memory 456768 kb
Host smart-afa24c69-ef87-4bf5-b4dd-3ec34beedc34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972468618 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.972468618
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3195610951
Short name T529
Test name
Test status
Simulation time 2084724142 ps
CPU time 2.67 seconds
Started Feb 07 02:20:24 PM PST 24
Finished Feb 07 02:20:27 PM PST 24
Peak memory 203660 kb
Host smart-abe5ad00-d858-4026-a365-f165e3a5f7cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195610951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3195610951
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3962104217
Short name T1370
Test name
Test status
Simulation time 1353956619 ps
CPU time 6.12 seconds
Started Feb 07 02:20:25 PM PST 24
Finished Feb 07 02:20:32 PM PST 24
Peak memory 213136 kb
Host smart-87ed4442-1485-45ac-a43b-b93236972164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962104217 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3962104217
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2572652921
Short name T1055
Test name
Test status
Simulation time 26074032058 ps
CPU time 7.11 seconds
Started Feb 07 02:20:25 PM PST 24
Finished Feb 07 02:20:33 PM PST 24
Peak memory 203728 kb
Host smart-99008eca-14f5-4662-ad0b-76d9f9b53fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572652921 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2572652921
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.901293879
Short name T1320
Test name
Test status
Simulation time 3119399264 ps
CPU time 4.74 seconds
Started Feb 07 02:20:32 PM PST 24
Finished Feb 07 02:20:38 PM PST 24
Peak memory 211488 kb
Host smart-d98fcdf0-51ed-4c4c-a5a6-6cd1c189fdac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901293879 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_perf.901293879
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1706431831
Short name T1529
Test name
Test status
Simulation time 5067901266 ps
CPU time 13.13 seconds
Started Feb 07 02:20:20 PM PST 24
Finished Feb 07 02:20:34 PM PST 24
Peak memory 203744 kb
Host smart-6abbcf1a-762e-4c40-8375-edf6327b3937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706431831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1706431831
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3804847406
Short name T1293
Test name
Test status
Simulation time 1257911406 ps
CPU time 15.46 seconds
Started Feb 07 02:20:30 PM PST 24
Finished Feb 07 02:20:46 PM PST 24
Peak memory 211784 kb
Host smart-5962f180-9386-4fd6-b455-1d82ca7bac34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804847406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3804847406
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.303336499
Short name T623
Test name
Test status
Simulation time 58253914888 ps
CPU time 1312.89 seconds
Started Feb 07 02:20:25 PM PST 24
Finished Feb 07 02:42:18 PM PST 24
Peak memory 6888140 kb
Host smart-581bebe4-5d83-4072-bdb3-b4645a78bc33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303336499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.303336499
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2842001578
Short name T1461
Test name
Test status
Simulation time 32912556809 ps
CPU time 3133.36 seconds
Started Feb 07 02:20:26 PM PST 24
Finished Feb 07 03:12:41 PM PST 24
Peak memory 7825676 kb
Host smart-12a95c3d-4967-4694-9a22-9b6575b00060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842001578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2842001578
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.591279388
Short name T1312
Test name
Test status
Simulation time 4119469852 ps
CPU time 7.56 seconds
Started Feb 07 02:20:19 PM PST 24
Finished Feb 07 02:20:28 PM PST 24
Peak memory 209364 kb
Host smart-3323e1c0-23a3-4119-8c0e-61a2b1ed8cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591279388 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.591279388
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_ovf.1464335593
Short name T1082
Test name
Test status
Simulation time 26158651558 ps
CPU time 178.15 seconds
Started Feb 07 02:20:27 PM PST 24
Finished Feb 07 02:23:26 PM PST 24
Peak memory 434384 kb
Host smart-8dd576c3-a7c7-4be0-a16f-982eb1901b7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464335593 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_tx_ovf.1464335593
Directory /workspace/12.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.4260028942
Short name T962
Test name
Test status
Simulation time 1352996961 ps
CPU time 6.98 seconds
Started Feb 07 02:20:25 PM PST 24
Finished Feb 07 02:20:33 PM PST 24
Peak memory 205956 kb
Host smart-ca1d2bfe-437b-4891-8eff-cd741767ae73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260028942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.4260028942
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.368835804
Short name T1424
Test name
Test status
Simulation time 37294054 ps
CPU time 0.59 seconds
Started Feb 07 02:20:37 PM PST 24
Finished Feb 07 02:20:38 PM PST 24
Peak memory 202384 kb
Host smart-639611ca-46fc-441f-8485-4079f580c6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368835804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.368835804
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2472968740
Short name T1532
Test name
Test status
Simulation time 56162614 ps
CPU time 1.48 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:20:50 PM PST 24
Peak memory 211468 kb
Host smart-e0bb7278-3f58-4214-970b-df4624506395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472968740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2472968740
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3241780998
Short name T1501
Test name
Test status
Simulation time 838516887 ps
CPU time 8.98 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:20:58 PM PST 24
Peak memory 293976 kb
Host smart-da4af10d-7570-46a0-a0e7-98cde67e9507
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241780998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3241780998
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.845638167
Short name T478
Test name
Test status
Simulation time 12800280459 ps
CPU time 287.17 seconds
Started Feb 07 02:20:45 PM PST 24
Finished Feb 07 02:25:33 PM PST 24
Peak memory 999428 kb
Host smart-80a03da5-37f5-44b8-a691-810b5c8b036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845638167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.845638167
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.4121620997
Short name T9
Test name
Test status
Simulation time 20873056510 ps
CPU time 294.11 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:25:44 PM PST 24
Peak memory 1486400 kb
Host smart-58cfeb94-d42d-4fec-a17b-e1741292f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121620997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.4121620997
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2627601778
Short name T1014
Test name
Test status
Simulation time 95064528 ps
CPU time 0.84 seconds
Started Feb 07 02:20:50 PM PST 24
Finished Feb 07 02:20:51 PM PST 24
Peak memory 203420 kb
Host smart-1d1207c8-0330-458a-90d2-16b8afa38c69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627601778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2627601778
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3389492349
Short name T462
Test name
Test status
Simulation time 2517207194 ps
CPU time 12.15 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:21:01 PM PST 24
Peak memory 203688 kb
Host smart-2e0afed8-ff65-4248-9a60-ccaf3276bc41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389492349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3389492349
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2396011779
Short name T726
Test name
Test status
Simulation time 23980467496 ps
CPU time 299.68 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:25:49 PM PST 24
Peak memory 1547876 kb
Host smart-87762916-1e63-46b5-8db5-2d80d6a18b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396011779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2396011779
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.529645363
Short name T1245
Test name
Test status
Simulation time 2704919584 ps
CPU time 175.74 seconds
Started Feb 07 02:20:43 PM PST 24
Finished Feb 07 02:23:40 PM PST 24
Peak memory 467880 kb
Host smart-8845d8b3-8b99-43fb-9deb-28e0c2ccf71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529645363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.529645363
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3813611569
Short name T981
Test name
Test status
Simulation time 45914867 ps
CPU time 0.62 seconds
Started Feb 07 02:20:37 PM PST 24
Finished Feb 07 02:20:38 PM PST 24
Peak memory 202568 kb
Host smart-d068e57b-4bdb-42dc-823d-c9957d5d1810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813611569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3813611569
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.4098372428
Short name T1238
Test name
Test status
Simulation time 26568626768 ps
CPU time 1826.37 seconds
Started Feb 07 02:20:43 PM PST 24
Finished Feb 07 02:51:10 PM PST 24
Peak memory 508752 kb
Host smart-b92cc35d-a103-4146-a253-0c969c53d063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098372428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.4098372428
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.819482299
Short name T1012
Test name
Test status
Simulation time 6031390433 ps
CPU time 117.06 seconds
Started Feb 07 02:20:35 PM PST 24
Finished Feb 07 02:22:33 PM PST 24
Peak memory 358340 kb
Host smart-d04fba2f-4624-4c99-b330-c9b234261627
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819482299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample.
819482299
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2744545111
Short name T891
Test name
Test status
Simulation time 7602799624 ps
CPU time 92.79 seconds
Started Feb 07 02:20:34 PM PST 24
Finished Feb 07 02:22:08 PM PST 24
Peak memory 231224 kb
Host smart-c21bf4da-a9cd-48a2-a41d-84421b10b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744545111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2744545111
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3355452420
Short name T766
Test name
Test status
Simulation time 4167266278 ps
CPU time 17.87 seconds
Started Feb 07 02:20:42 PM PST 24
Finished Feb 07 02:21:01 PM PST 24
Peak memory 219648 kb
Host smart-40d7a67b-1bab-4c3c-bf1e-cf5ad13985d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355452420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3355452420
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1198339711
Short name T553
Test name
Test status
Simulation time 786335922 ps
CPU time 3.34 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:20:53 PM PST 24
Peak memory 203652 kb
Host smart-776e8eff-0b2d-4e96-a175-e4b70bb0a07c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198339711 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1198339711
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3701120727
Short name T834
Test name
Test status
Simulation time 10067632066 ps
CPU time 12.31 seconds
Started Feb 07 02:20:45 PM PST 24
Finished Feb 07 02:20:58 PM PST 24
Peak memory 281868 kb
Host smart-30666709-55ac-4aa2-9921-5b4a2050f2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701120727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3701120727
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1040344387
Short name T1311
Test name
Test status
Simulation time 10565774196 ps
CPU time 14.08 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:21:03 PM PST 24
Peak memory 295296 kb
Host smart-e5afd2be-152f-4d12-9689-2c6f49fe1cff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040344387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1040344387
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1978149134
Short name T1035
Test name
Test status
Simulation time 5407473024 ps
CPU time 6.18 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:20:55 PM PST 24
Peak memory 203752 kb
Host smart-45f9b8d8-0773-4402-a9e9-d97c82f60e98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978149134 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1978149134
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1115604604
Short name T362
Test name
Test status
Simulation time 12268451399 ps
CPU time 258.7 seconds
Started Feb 07 02:20:41 PM PST 24
Finished Feb 07 02:25:01 PM PST 24
Peak memory 2771640 kb
Host smart-fb654053-c66a-49d6-a8bb-7fdc82aadde8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115604604 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1115604604
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.3940330528
Short name T1165
Test name
Test status
Simulation time 3139886051 ps
CPU time 4.39 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:20:54 PM PST 24
Peak memory 205532 kb
Host smart-b341a32a-1d2e-487e-8fef-e82cc4ca1148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940330528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.3940330528
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3136382120
Short name T1344
Test name
Test status
Simulation time 1740221585 ps
CPU time 17.74 seconds
Started Feb 07 02:20:41 PM PST 24
Finished Feb 07 02:20:59 PM PST 24
Peak memory 203520 kb
Host smart-9605aec4-83ca-4848-a376-1f40ddac9053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136382120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3136382120
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.1520759805
Short name T380
Test name
Test status
Simulation time 83196418518 ps
CPU time 237.84 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:24:47 PM PST 24
Peak memory 2016296 kb
Host smart-4a6806f7-d048-45ca-91b3-e8d683aa7d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520759805 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.1520759805
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3480716718
Short name T1215
Test name
Test status
Simulation time 5622450450 ps
CPU time 72.39 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:22:02 PM PST 24
Peak memory 203740 kb
Host smart-5cf52040-fc5d-46f5-95d6-7dd48af58983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480716718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3480716718
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.297498750
Short name T1255
Test name
Test status
Simulation time 12688490450 ps
CPU time 119.36 seconds
Started Feb 07 02:20:34 PM PST 24
Finished Feb 07 02:22:34 PM PST 24
Peak memory 2106496 kb
Host smart-b9dd281e-bce1-4353-b3b1-6ef93e4b59ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297498750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.297498750
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.803686235
Short name T1535
Test name
Test status
Simulation time 37980405636 ps
CPU time 275.25 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:25:24 PM PST 24
Peak memory 1924016 kb
Host smart-7ee0aad6-dc2b-4ef7-8e92-b8afb4909136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803686235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.803686235
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3501991257
Short name T542
Test name
Test status
Simulation time 1411372152 ps
CPU time 6.13 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:20:53 PM PST 24
Peak memory 203648 kb
Host smart-77854914-dfd0-48e2-bdae-0bae278f2587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501991257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3501991257
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_ovf.1453584883
Short name T310
Test name
Test status
Simulation time 3263041920 ps
CPU time 153.82 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:23:22 PM PST 24
Peak memory 453236 kb
Host smart-c24f8d0f-ec2e-42a5-bf1a-b9ffd738a4c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453584883 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_tx_ovf.1453584883
Directory /workspace/13.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.3150070069
Short name T1490
Test name
Test status
Simulation time 1958028100 ps
CPU time 5.16 seconds
Started Feb 07 02:20:50 PM PST 24
Finished Feb 07 02:20:56 PM PST 24
Peak memory 203640 kb
Host smart-6cd9aafa-a1fb-48f7-b6b7-28cba522e1c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150070069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.3150070069
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.20536085
Short name T91
Test name
Test status
Simulation time 17385574 ps
CPU time 0.57 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:20:48 PM PST 24
Peak memory 202432 kb
Host smart-a0ff5626-feca-4243-b049-5d8811c80abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20536085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.20536085
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1293647123
Short name T464
Test name
Test status
Simulation time 40589134 ps
CPU time 1.32 seconds
Started Feb 07 02:20:43 PM PST 24
Finished Feb 07 02:20:45 PM PST 24
Peak memory 211856 kb
Host smart-9681596a-1ba3-4806-b99c-6375f39de46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293647123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1293647123
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.305693360
Short name T524
Test name
Test status
Simulation time 1866519977 ps
CPU time 23.34 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:21:10 PM PST 24
Peak memory 277940 kb
Host smart-a5699287-9bb7-4af9-9ab1-f7b45f404152
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305693360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.305693360
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2706242296
Short name T1240
Test name
Test status
Simulation time 12268008849 ps
CPU time 127.07 seconds
Started Feb 07 02:20:36 PM PST 24
Finished Feb 07 02:22:44 PM PST 24
Peak memory 939616 kb
Host smart-a3f5f762-ee41-47b5-84b0-073d35521ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706242296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2706242296
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.606353942
Short name T471
Test name
Test status
Simulation time 55262131656 ps
CPU time 384.09 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:27:11 PM PST 24
Peak memory 1653992 kb
Host smart-522b6b63-8e8f-4418-84d8-2f6260066d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606353942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.606353942
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1616577644
Short name T782
Test name
Test status
Simulation time 420422056 ps
CPU time 0.88 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:20:48 PM PST 24
Peak memory 203392 kb
Host smart-286f95b5-0504-4bac-9f77-ec61234c0c21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616577644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1616577644
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2561885151
Short name T684
Test name
Test status
Simulation time 212495904 ps
CPU time 12.58 seconds
Started Feb 07 02:20:38 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 245036 kb
Host smart-3068cbb7-65c7-451b-a72a-17d40aad5ba0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561885151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2561885151
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.578654384
Short name T277
Test name
Test status
Simulation time 3385459718 ps
CPU time 272.4 seconds
Started Feb 07 02:20:40 PM PST 24
Finished Feb 07 02:25:13 PM PST 24
Peak memory 960604 kb
Host smart-9391bd6e-969a-4126-9f93-70ba4a3d5910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578654384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.578654384
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1878069908
Short name T1223
Test name
Test status
Simulation time 11138541466 ps
CPU time 85.67 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:22:13 PM PST 24
Peak memory 358312 kb
Host smart-9b266e84-487d-433a-8dae-49e0a4c41f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878069908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1878069908
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1589878447
Short name T1203
Test name
Test status
Simulation time 41159236 ps
CPU time 0.63 seconds
Started Feb 07 02:20:41 PM PST 24
Finished Feb 07 02:20:42 PM PST 24
Peak memory 202612 kb
Host smart-cd61b3be-3ed6-483d-ab45-d91783928997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589878447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1589878447
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.805957250
Short name T7
Test name
Test status
Simulation time 26486526890 ps
CPU time 96.83 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:22:24 PM PST 24
Peak memory 220140 kb
Host smart-6a77fe83-5a4d-4d86-93ee-d1b0ebe0ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805957250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.805957250
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_rx_oversample.1134417979
Short name T1077
Test name
Test status
Simulation time 5238444041 ps
CPU time 131.28 seconds
Started Feb 07 02:20:37 PM PST 24
Finished Feb 07 02:22:49 PM PST 24
Peak memory 344604 kb
Host smart-c0a28d08-a9fd-4b43-baea-2dd7b387be4e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134417979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_rx_oversample
.1134417979
Directory /workspace/14.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.264132172
Short name T1503
Test name
Test status
Simulation time 8693344390 ps
CPU time 68.28 seconds
Started Feb 07 02:20:40 PM PST 24
Finished Feb 07 02:21:49 PM PST 24
Peak memory 341408 kb
Host smart-f7f34fab-6c1a-473a-b922-dc8dfe819ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264132172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.264132172
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1463847911
Short name T46
Test name
Test status
Simulation time 134725825144 ps
CPU time 1437.34 seconds
Started Feb 07 02:20:45 PM PST 24
Finished Feb 07 02:44:43 PM PST 24
Peak memory 964796 kb
Host smart-12fb9fd6-b4eb-4e3b-a954-af6d57dd5478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463847911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1463847911
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2043820817
Short name T1537
Test name
Test status
Simulation time 1065751090 ps
CPU time 20.6 seconds
Started Feb 07 02:20:44 PM PST 24
Finished Feb 07 02:21:05 PM PST 24
Peak memory 215928 kb
Host smart-8cda1601-395d-4563-ade6-6af401e48f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043820817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2043820817
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1465344387
Short name T249
Test name
Test status
Simulation time 2905681753 ps
CPU time 3.22 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 203716 kb
Host smart-1f4888dd-144a-4219-bf0a-2aaa42764116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465344387 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1465344387
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.4066739990
Short name T1124
Test name
Test status
Simulation time 10329306353 ps
CPU time 4.57 seconds
Started Feb 07 02:20:44 PM PST 24
Finished Feb 07 02:20:49 PM PST 24
Peak memory 227476 kb
Host smart-55cc4d03-3eb1-4fd1-b940-5247555e1289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066739990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.4066739990
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3403348217
Short name T498
Test name
Test status
Simulation time 10086095803 ps
CPU time 88.37 seconds
Started Feb 07 02:20:41 PM PST 24
Finished Feb 07 02:22:10 PM PST 24
Peak memory 764300 kb
Host smart-7e6bd333-ba6c-40fa-a6e0-9a88da4a952d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403348217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3403348217
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2276932905
Short name T794
Test name
Test status
Simulation time 439272834 ps
CPU time 2.38 seconds
Started Feb 07 02:20:52 PM PST 24
Finished Feb 07 02:20:55 PM PST 24
Peak memory 203644 kb
Host smart-d963bc88-b776-413b-b5e3-c419cd55b93e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276932905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2276932905
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.4016750101
Short name T575
Test name
Test status
Simulation time 1474777394 ps
CPU time 6.37 seconds
Started Feb 07 02:20:40 PM PST 24
Finished Feb 07 02:20:48 PM PST 24
Peak memory 203648 kb
Host smart-d7a94186-5ad5-42fb-8256-1bf35dacce32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016750101 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.4016750101
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.3522542168
Short name T686
Test name
Test status
Simulation time 20538710210 ps
CPU time 810.25 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:34:20 PM PST 24
Peak memory 4900996 kb
Host smart-644d3978-1dc7-4bc4-a02c-a0a49d135d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522542168 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.3522542168
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.3513690814
Short name T632
Test name
Test status
Simulation time 849889929 ps
CPU time 4.09 seconds
Started Feb 07 02:20:40 PM PST 24
Finished Feb 07 02:20:45 PM PST 24
Peak memory 203620 kb
Host smart-f37d9d20-c435-47ac-a637-a83879b287f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513690814 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.3513690814
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2992951826
Short name T697
Test name
Test status
Simulation time 4460752833 ps
CPU time 10.99 seconds
Started Feb 07 02:20:44 PM PST 24
Finished Feb 07 02:20:55 PM PST 24
Peak memory 203736 kb
Host smart-5fa51901-b006-4633-8d5c-c6108f5c3cc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992951826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2992951826
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.612238355
Short name T294
Test name
Test status
Simulation time 8469669743 ps
CPU time 21.32 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:21:10 PM PST 24
Peak memory 217084 kb
Host smart-30b8b26c-c414-4d8d-9ea0-c260c5a02d75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612238355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.612238355
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.691394427
Short name T288
Test name
Test status
Simulation time 49305683329 ps
CPU time 354.65 seconds
Started Feb 07 02:20:41 PM PST 24
Finished Feb 07 02:26:36 PM PST 24
Peak memory 2976480 kb
Host smart-5700efde-a4cf-462f-892d-42216d6f53b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691394427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.691394427
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.266539078
Short name T573
Test name
Test status
Simulation time 46828747626 ps
CPU time 1085.65 seconds
Started Feb 07 02:20:40 PM PST 24
Finished Feb 07 02:38:46 PM PST 24
Peak memory 2350636 kb
Host smart-89d8a057-eb57-43a4-abf4-1e6f50cc8c03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266539078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.266539078
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.44437583
Short name T1132
Test name
Test status
Simulation time 8792719953 ps
CPU time 8.7 seconds
Started Feb 07 02:20:42 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 212880 kb
Host smart-230612aa-312d-41ee-b839-883006fa1638
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44437583 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_timeout.44437583
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_ovf.3481516472
Short name T1057
Test name
Test status
Simulation time 15109333789 ps
CPU time 200.01 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:24:09 PM PST 24
Peak memory 473996 kb
Host smart-28e1f02c-8f5b-497c-ab68-3c3e054520bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481516472 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_tx_ovf.3481516472
Directory /workspace/14.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.275027290
Short name T261
Test name
Test status
Simulation time 2735114143 ps
CPU time 6.1 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:20:56 PM PST 24
Peak memory 203724 kb
Host smart-5c08cc8c-a096-468e-a009-9614e7758d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275027290 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_unexp_stop.275027290
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1163676832
Short name T866
Test name
Test status
Simulation time 18694613 ps
CPU time 0.61 seconds
Started Feb 07 02:20:59 PM PST 24
Finished Feb 07 02:21:00 PM PST 24
Peak memory 202348 kb
Host smart-3007d77a-7c7b-4b5c-a9be-3e28d47d4ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163676832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1163676832
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2069871488
Short name T44
Test name
Test status
Simulation time 94096244 ps
CPU time 1.25 seconds
Started Feb 07 02:20:52 PM PST 24
Finished Feb 07 02:20:54 PM PST 24
Peak memory 211884 kb
Host smart-9ac6786c-b40b-474f-81a7-9f70261d70bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069871488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2069871488
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.907044467
Short name T1205
Test name
Test status
Simulation time 517379666 ps
CPU time 4.96 seconds
Started Feb 07 02:20:51 PM PST 24
Finished Feb 07 02:20:57 PM PST 24
Peak memory 257192 kb
Host smart-e0365f61-de73-4cf5-92a1-c9715ebb7e05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907044467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.907044467
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.752291039
Short name T606
Test name
Test status
Simulation time 5972564013 ps
CPU time 59.94 seconds
Started Feb 07 02:20:52 PM PST 24
Finished Feb 07 02:21:53 PM PST 24
Peak memory 344492 kb
Host smart-e82fcf2f-037f-4b65-ab31-1727b13e7c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752291039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.752291039
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.657916482
Short name T779
Test name
Test status
Simulation time 16753905460 ps
CPU time 198.24 seconds
Started Feb 07 02:20:48 PM PST 24
Finished Feb 07 02:24:07 PM PST 24
Peak memory 1173356 kb
Host smart-364169f8-691a-4281-9bd8-1909f2ba45dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657916482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.657916482
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3043448526
Short name T1113
Test name
Test status
Simulation time 81956654 ps
CPU time 0.82 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:20:48 PM PST 24
Peak memory 203428 kb
Host smart-83637949-6aaf-48f1-9d96-b3f2349d13ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043448526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3043448526
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3339081826
Short name T1528
Test name
Test status
Simulation time 161645842 ps
CPU time 4.63 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 230204 kb
Host smart-bccbd5ae-ee13-48e3-a1e5-f2131ce0aabd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339081826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3339081826
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.471901421
Short name T1265
Test name
Test status
Simulation time 4315110687 ps
CPU time 177.83 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:23:45 PM PST 24
Peak memory 1198368 kb
Host smart-f7cbf41a-742a-4873-836f-ebccf2ecfbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471901421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.471901421
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.525258616
Short name T1531
Test name
Test status
Simulation time 16552047044 ps
CPU time 127.18 seconds
Started Feb 07 02:20:58 PM PST 24
Finished Feb 07 02:23:06 PM PST 24
Peak memory 240448 kb
Host smart-8b8dd2b0-2194-4a7d-94e5-be25eafd2895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525258616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.525258616
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1640030708
Short name T941
Test name
Test status
Simulation time 24321137 ps
CPU time 0.61 seconds
Started Feb 07 02:20:52 PM PST 24
Finished Feb 07 02:20:54 PM PST 24
Peak memory 202664 kb
Host smart-7620d7dd-65ed-4bd7-930d-77bf091464c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640030708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1640030708
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3293612658
Short name T565
Test name
Test status
Simulation time 3608488674 ps
CPU time 28.92 seconds
Started Feb 07 02:20:52 PM PST 24
Finished Feb 07 02:21:21 PM PST 24
Peak memory 220200 kb
Host smart-93587707-6a83-4603-9b30-52d8a814acf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293612658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3293612658
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.2002433668
Short name T382
Test name
Test status
Simulation time 1274560688 ps
CPU time 36.68 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:21:23 PM PST 24
Peak memory 268764 kb
Host smart-8b5be022-2f28-444e-9e9d-df2cccf3bbe1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002433668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample
.2002433668
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1802359066
Short name T820
Test name
Test status
Simulation time 2541836730 ps
CPU time 104.23 seconds
Started Feb 07 02:20:51 PM PST 24
Finished Feb 07 02:22:36 PM PST 24
Peak memory 371180 kb
Host smart-d3e2ea6f-f3bd-4d31-8a90-70c13d77bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802359066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1802359066
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.2133212293
Short name T457
Test name
Test status
Simulation time 17079768611 ps
CPU time 1408.64 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:44:16 PM PST 24
Peak memory 1244228 kb
Host smart-e430ac4e-2236-4ad4-901a-baf4a70d75b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133212293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.2133212293
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3031222975
Short name T417
Test name
Test status
Simulation time 3406717562 ps
CPU time 35.06 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:21:25 PM PST 24
Peak memory 211864 kb
Host smart-01e14322-2110-4ec9-b55b-3e8f50c92547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031222975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3031222975
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.808933627
Short name T318
Test name
Test status
Simulation time 1489918521 ps
CPU time 6.13 seconds
Started Feb 07 02:20:56 PM PST 24
Finished Feb 07 02:21:02 PM PST 24
Peak memory 203596 kb
Host smart-30f98af5-8e8e-452e-a529-eaf50fde7be5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808933627 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.808933627
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2967359398
Short name T290
Test name
Test status
Simulation time 10215668922 ps
CPU time 29.2 seconds
Started Feb 07 02:20:56 PM PST 24
Finished Feb 07 02:21:26 PM PST 24
Peak memory 409740 kb
Host smart-2348d899-53c2-4f1d-a785-62285b0cd090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967359398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2967359398
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.463504975
Short name T367
Test name
Test status
Simulation time 10151809799 ps
CPU time 58.39 seconds
Started Feb 07 02:21:01 PM PST 24
Finished Feb 07 02:22:00 PM PST 24
Peak memory 586888 kb
Host smart-ad5a8702-832d-49af-99cd-c69715a129b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463504975 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.463504975
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3766646769
Short name T1313
Test name
Test status
Simulation time 2652226605 ps
CPU time 2.29 seconds
Started Feb 07 02:20:59 PM PST 24
Finished Feb 07 02:21:02 PM PST 24
Peak memory 203724 kb
Host smart-afdfae17-8f86-4c7e-9807-8eb7e306a51f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766646769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3766646769
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.664269474
Short name T1041
Test name
Test status
Simulation time 2728190845 ps
CPU time 5.84 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:20:54 PM PST 24
Peak memory 203800 kb
Host smart-ed8187fc-5d2b-4ba7-8a6a-f12201bb1d1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664269474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.664269474
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1003441583
Short name T363
Test name
Test status
Simulation time 6290078381 ps
CPU time 67.48 seconds
Started Feb 07 02:20:58 PM PST 24
Finished Feb 07 02:22:06 PM PST 24
Peak memory 1323972 kb
Host smart-1ebb48fc-5fd7-44ae-a150-47229112116a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003441583 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1003441583
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.525050911
Short name T997
Test name
Test status
Simulation time 624985603 ps
CPU time 3.53 seconds
Started Feb 07 02:20:57 PM PST 24
Finished Feb 07 02:21:01 PM PST 24
Peak memory 206684 kb
Host smart-9a5253ac-2a2a-426a-995a-7ad06c2df5c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525050911 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_perf.525050911
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1683998560
Short name T663
Test name
Test status
Simulation time 5797865908 ps
CPU time 43.01 seconds
Started Feb 07 02:20:49 PM PST 24
Finished Feb 07 02:21:33 PM PST 24
Peak memory 203708 kb
Host smart-2e0c56ea-82af-42f5-a694-d18fd73d8e83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683998560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1683998560
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2004679038
Short name T582
Test name
Test status
Simulation time 988295688 ps
CPU time 6.93 seconds
Started Feb 07 02:20:47 PM PST 24
Finished Feb 07 02:20:55 PM PST 24
Peak memory 203592 kb
Host smart-320bf3a5-dc99-4772-a807-8680413f4677
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004679038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2004679038
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3040248418
Short name T753
Test name
Test status
Simulation time 53768030706 ps
CPU time 527.98 seconds
Started Feb 07 02:20:52 PM PST 24
Finished Feb 07 02:29:41 PM PST 24
Peak memory 3273360 kb
Host smart-2bc61b93-ae4c-49a0-bac7-563099c4a024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040248418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3040248418
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1335374762
Short name T648
Test name
Test status
Simulation time 6683813198 ps
CPU time 44.44 seconds
Started Feb 07 02:20:46 PM PST 24
Finished Feb 07 02:21:31 PM PST 24
Peak memory 649156 kb
Host smart-cbc8b41a-9398-4c06-b486-3458b1403902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335374762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1335374762
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1019593934
Short name T364
Test name
Test status
Simulation time 1648065490 ps
CPU time 7.27 seconds
Started Feb 07 02:20:56 PM PST 24
Finished Feb 07 02:21:04 PM PST 24
Peak memory 213808 kb
Host smart-71850985-7f70-483b-acdb-c860ed26dd0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019593934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1019593934
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_ovf.2878114597
Short name T806
Test name
Test status
Simulation time 11978319791 ps
CPU time 88.32 seconds
Started Feb 07 02:21:00 PM PST 24
Finished Feb 07 02:22:28 PM PST 24
Peak memory 303868 kb
Host smart-e4158448-1260-46d3-9448-67b59fbe7ad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878114597 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_tx_ovf.2878114597
Directory /workspace/15.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.4102205226
Short name T315
Test name
Test status
Simulation time 1500461504 ps
CPU time 7.03 seconds
Started Feb 07 02:20:57 PM PST 24
Finished Feb 07 02:21:05 PM PST 24
Peak memory 203608 kb
Host smart-0011179a-d799-4b3c-a9ed-37b9dbe0ec9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102205226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.4102205226
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.17056965
Short name T88
Test name
Test status
Simulation time 51779968 ps
CPU time 0.6 seconds
Started Feb 07 02:21:20 PM PST 24
Finished Feb 07 02:21:22 PM PST 24
Peak memory 202388 kb
Host smart-a9038114-0462-4ff1-8e20-2d9f43c4363c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.17056965
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3141665680
Short name T824
Test name
Test status
Simulation time 153826772 ps
CPU time 2.1 seconds
Started Feb 07 02:21:18 PM PST 24
Finished Feb 07 02:21:22 PM PST 24
Peak memory 211844 kb
Host smart-c85373ec-3c43-458f-8950-e6f1baf8b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141665680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3141665680
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2914816994
Short name T780
Test name
Test status
Simulation time 1649454832 ps
CPU time 9.84 seconds
Started Feb 07 02:21:10 PM PST 24
Finished Feb 07 02:21:23 PM PST 24
Peak memory 296956 kb
Host smart-74108f7b-a4a9-4adc-8d35-37852da50981
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914816994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2914816994
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2649862167
Short name T909
Test name
Test status
Simulation time 5184387181 ps
CPU time 195.79 seconds
Started Feb 07 02:21:10 PM PST 24
Finished Feb 07 02:24:29 PM PST 24
Peak memory 810432 kb
Host smart-a495d1ca-f1cc-4423-b381-dc867a5e5359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649862167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2649862167
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.4082527955
Short name T465
Test name
Test status
Simulation time 38233388197 ps
CPU time 199.47 seconds
Started Feb 07 02:21:10 PM PST 24
Finished Feb 07 02:24:33 PM PST 24
Peak memory 1160808 kb
Host smart-33178790-9a12-4352-b3ae-ed7bf47f058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082527955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.4082527955
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.987599153
Short name T1459
Test name
Test status
Simulation time 622802307 ps
CPU time 1.25 seconds
Started Feb 07 02:21:10 PM PST 24
Finished Feb 07 02:21:14 PM PST 24
Peak memory 203644 kb
Host smart-6eee534b-8607-4186-a480-70f2a929d2f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987599153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.987599153
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.687444597
Short name T1065
Test name
Test status
Simulation time 500553277 ps
CPU time 6.49 seconds
Started Feb 07 02:21:11 PM PST 24
Finished Feb 07 02:21:23 PM PST 24
Peak memory 203616 kb
Host smart-3e8d9561-1a12-44cc-8f05-6ce802188a93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687444597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
687444597
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1477618671
Short name T1440
Test name
Test status
Simulation time 5368506319 ps
CPU time 258.1 seconds
Started Feb 07 02:21:10 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 1347492 kb
Host smart-304cd3e5-2ce9-45da-9569-f37ba28f6598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477618671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1477618671
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.372694093
Short name T808
Test name
Test status
Simulation time 3067481397 ps
CPU time 141.72 seconds
Started Feb 07 02:21:15 PM PST 24
Finished Feb 07 02:23:41 PM PST 24
Peak memory 229532 kb
Host smart-a6cdddf1-f15d-4da6-ba89-d09fcc82546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372694093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.372694093
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3079812068
Short name T473
Test name
Test status
Simulation time 75232744 ps
CPU time 0.61 seconds
Started Feb 07 02:20:58 PM PST 24
Finished Feb 07 02:20:59 PM PST 24
Peak memory 202604 kb
Host smart-abc35c18-429b-4a38-9f38-be76547964d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079812068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3079812068
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.873238007
Short name T933
Test name
Test status
Simulation time 49916612746 ps
CPU time 416.69 seconds
Started Feb 07 02:21:15 PM PST 24
Finished Feb 07 02:28:15 PM PST 24
Peak memory 203700 kb
Host smart-45479223-3c19-48e5-bd0a-23fa9c81379a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873238007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.873238007
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.783948114
Short name T757
Test name
Test status
Simulation time 17224296121 ps
CPU time 173.07 seconds
Started Feb 07 02:20:58 PM PST 24
Finished Feb 07 02:23:52 PM PST 24
Peak memory 363444 kb
Host smart-ea400cd0-5b52-4c09-a000-276d31adf0b9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783948114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample.
783948114
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3441953730
Short name T317
Test name
Test status
Simulation time 11479061613 ps
CPU time 92.76 seconds
Started Feb 07 02:20:56 PM PST 24
Finished Feb 07 02:22:30 PM PST 24
Peak memory 309452 kb
Host smart-db4d9b7b-990e-4b2b-b703-95e9d33ee436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441953730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3441953730
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.664357975
Short name T47
Test name
Test status
Simulation time 6488286542 ps
CPU time 563.2 seconds
Started Feb 07 02:21:18 PM PST 24
Finished Feb 07 02:30:43 PM PST 24
Peak memory 1531176 kb
Host smart-53c150f9-2831-4a9a-87ed-67f74f24077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664357975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.664357975
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.280173560
Short name T849
Test name
Test status
Simulation time 4472026612 ps
CPU time 21.33 seconds
Started Feb 07 02:21:12 PM PST 24
Finished Feb 07 02:21:39 PM PST 24
Peak memory 218728 kb
Host smart-0c46e211-91f8-4a25-9a0b-3aaf247d9550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280173560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.280173560
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.966195057
Short name T36
Test name
Test status
Simulation time 932482437 ps
CPU time 2.34 seconds
Started Feb 07 02:21:24 PM PST 24
Finished Feb 07 02:21:27 PM PST 24
Peak memory 203652 kb
Host smart-590df1c9-0bc0-43e2-94b6-d5049ce8d6c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966195057 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.966195057
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3879670480
Short name T1210
Test name
Test status
Simulation time 10124884148 ps
CPU time 73.92 seconds
Started Feb 07 02:21:25 PM PST 24
Finished Feb 07 02:22:40 PM PST 24
Peak memory 606372 kb
Host smart-ab2c1cbd-c1c8-4b00-946a-03d3dba63d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879670480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3879670480
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3902217817
Short name T987
Test name
Test status
Simulation time 10065393983 ps
CPU time 84.07 seconds
Started Feb 07 02:21:14 PM PST 24
Finished Feb 07 02:22:43 PM PST 24
Peak memory 682300 kb
Host smart-c8fd2494-4214-4a62-952b-efcfdf10c1b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902217817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3902217817
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3095925470
Short name T97
Test name
Test status
Simulation time 892467491 ps
CPU time 2.46 seconds
Started Feb 07 02:21:18 PM PST 24
Finished Feb 07 02:21:22 PM PST 24
Peak memory 203592 kb
Host smart-c1b7ac49-da1e-4ce2-93e0-424fbe46f378
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095925470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3095925470
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.995539305
Short name T1136
Test name
Test status
Simulation time 1337220833 ps
CPU time 5.67 seconds
Started Feb 07 02:21:12 PM PST 24
Finished Feb 07 02:21:23 PM PST 24
Peak memory 205052 kb
Host smart-a97fbe55-0ed4-4e37-849d-5e8c578abf02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995539305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.995539305
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.598457309
Short name T935
Test name
Test status
Simulation time 16341424865 ps
CPU time 20.33 seconds
Started Feb 07 02:21:17 PM PST 24
Finished Feb 07 02:21:39 PM PST 24
Peak memory 461980 kb
Host smart-ebf027c6-744d-4c2d-90fd-dd6badb4a79d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598457309 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.598457309
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.3465601061
Short name T306
Test name
Test status
Simulation time 789563493 ps
CPU time 4.81 seconds
Started Feb 07 02:21:12 PM PST 24
Finished Feb 07 02:21:23 PM PST 24
Peak memory 210064 kb
Host smart-6d49428f-8660-4a57-b5c4-e04707d13ba6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465601061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.3465601061
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.672065574
Short name T683
Test name
Test status
Simulation time 1270506229 ps
CPU time 16.97 seconds
Started Feb 07 02:21:13 PM PST 24
Finished Feb 07 02:21:35 PM PST 24
Peak memory 203612 kb
Host smart-53b67e3f-e1f6-4ad4-94f7-03f887386e79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672065574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.672065574
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.1750764636
Short name T700
Test name
Test status
Simulation time 15788157147 ps
CPU time 200.71 seconds
Started Feb 07 02:21:19 PM PST 24
Finished Feb 07 02:24:42 PM PST 24
Peak memory 220064 kb
Host smart-28655848-8292-47e1-aae2-829334344075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750764636 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.1750764636
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3605846565
Short name T1252
Test name
Test status
Simulation time 4553985186 ps
CPU time 39.92 seconds
Started Feb 07 02:21:18 PM PST 24
Finished Feb 07 02:22:00 PM PST 24
Peak memory 227104 kb
Host smart-898a622b-a1fd-4a69-a7c6-fc76b6fcbe93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605846565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3605846565
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3035306848
Short name T1137
Test name
Test status
Simulation time 29569694428 ps
CPU time 633.71 seconds
Started Feb 07 02:21:14 PM PST 24
Finished Feb 07 02:31:53 PM PST 24
Peak memory 3252420 kb
Host smart-7b310e16-e264-4cc0-ab2c-295e32be1713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035306848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3035306848
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2230289426
Short name T772
Test name
Test status
Simulation time 6799742330 ps
CPU time 7.05 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 02:21:31 PM PST 24
Peak memory 208952 kb
Host smart-df4aa311-1f18-4168-994b-a365d17bf637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230289426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2230289426
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_ovf.999772911
Short name T314
Test name
Test status
Simulation time 7049528274 ps
CPU time 42.26 seconds
Started Feb 07 02:21:12 PM PST 24
Finished Feb 07 02:22:00 PM PST 24
Peak memory 211972 kb
Host smart-f5aa7604-ef67-4a73-8eb7-c57dcd709598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999772911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_tx_ovf.999772911
Directory /workspace/16.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.904922021
Short name T712
Test name
Test status
Simulation time 1823340678 ps
CPU time 8.49 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 02:21:32 PM PST 24
Peak memory 206868 kb
Host smart-3361d138-b7f2-4782-830c-fbf7eaf24f61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904922021 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_unexp_stop.904922021
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3813941054
Short name T297
Test name
Test status
Simulation time 57546912 ps
CPU time 0.61 seconds
Started Feb 07 02:21:33 PM PST 24
Finished Feb 07 02:21:34 PM PST 24
Peak memory 202380 kb
Host smart-c69c66cb-018a-4036-ba0b-c4ba51bdcedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813941054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3813941054
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.236204693
Short name T1399
Test name
Test status
Simulation time 122808291 ps
CPU time 1.5 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 02:21:24 PM PST 24
Peak memory 211836 kb
Host smart-9ea780b2-83a1-4399-a8f0-be06040bbcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236204693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.236204693
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1495342945
Short name T357
Test name
Test status
Simulation time 763910239 ps
CPU time 21.81 seconds
Started Feb 07 02:21:24 PM PST 24
Finished Feb 07 02:21:47 PM PST 24
Peak memory 287864 kb
Host smart-42730700-1ea8-4aee-bea4-b680d6224d96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495342945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1495342945
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1580954186
Short name T676
Test name
Test status
Simulation time 12529486982 ps
CPU time 115.48 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 02:23:19 PM PST 24
Peak memory 924312 kb
Host smart-43446a3c-22c7-4283-bb5b-30ffcfe16ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580954186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1580954186
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2389387302
Short name T633
Test name
Test status
Simulation time 8866124917 ps
CPU time 177.88 seconds
Started Feb 07 02:21:24 PM PST 24
Finished Feb 07 02:24:22 PM PST 24
Peak memory 1042256 kb
Host smart-e38a4451-021b-4d28-951a-c72bf7b9f934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389387302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2389387302
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2565297612
Short name T1106
Test name
Test status
Simulation time 109311033 ps
CPU time 0.77 seconds
Started Feb 07 02:21:21 PM PST 24
Finished Feb 07 02:21:23 PM PST 24
Peak memory 203404 kb
Host smart-e031cbc3-55b3-4562-854e-ecc311994cc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565297612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2565297612
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3305217956
Short name T1027
Test name
Test status
Simulation time 340778367 ps
CPU time 4.27 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 02:21:28 PM PST 24
Peak memory 233616 kb
Host smart-6e460ad4-2797-4d61-870a-83944e1b16fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305217956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3305217956
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2657599727
Short name T682
Test name
Test status
Simulation time 21783241752 ps
CPU time 274.64 seconds
Started Feb 07 02:21:16 PM PST 24
Finished Feb 07 02:25:53 PM PST 24
Peak memory 1568204 kb
Host smart-ac88a70e-3e9e-40c4-986e-152fb19b7333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657599727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2657599727
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3226672383
Short name T411
Test name
Test status
Simulation time 3758500392 ps
CPU time 119.1 seconds
Started Feb 07 02:21:26 PM PST 24
Finished Feb 07 02:23:26 PM PST 24
Peak memory 268720 kb
Host smart-ab228ac1-4c37-4fe8-a999-fe1651d91cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226672383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3226672383
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.702612075
Short name T864
Test name
Test status
Simulation time 43008693 ps
CPU time 0.65 seconds
Started Feb 07 02:21:23 PM PST 24
Finished Feb 07 02:21:25 PM PST 24
Peak memory 203256 kb
Host smart-4422dfec-c013-4e68-ac1b-9665c06f8a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702612075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.702612075
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3954257290
Short name T1515
Test name
Test status
Simulation time 552269523 ps
CPU time 25.26 seconds
Started Feb 07 02:21:20 PM PST 24
Finished Feb 07 02:21:48 PM PST 24
Peak memory 220056 kb
Host smart-4fd1da5a-be64-483e-8e1f-e8b78721909e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954257290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3954257290
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.1130786609
Short name T391
Test name
Test status
Simulation time 6668977435 ps
CPU time 64.94 seconds
Started Feb 07 02:21:25 PM PST 24
Finished Feb 07 02:22:31 PM PST 24
Peak memory 294580 kb
Host smart-8a4c5e28-4c9d-476e-a3b5-bb9a6511adec
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130786609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample
.1130786609
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1098793868
Short name T627
Test name
Test status
Simulation time 1222111669 ps
CPU time 37.68 seconds
Started Feb 07 02:21:21 PM PST 24
Finished Feb 07 02:22:00 PM PST 24
Peak memory 307860 kb
Host smart-a5c07615-e2f9-4e1e-9e29-25e26e9650f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098793868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1098793868
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1505837295
Short name T372
Test name
Test status
Simulation time 54054637464 ps
CPU time 3555.03 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 03:20:38 PM PST 24
Peak memory 3744784 kb
Host smart-4e7cb517-bbbc-4468-904b-e874121e1c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505837295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1505837295
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1666273829
Short name T936
Test name
Test status
Simulation time 6116718974 ps
CPU time 11.49 seconds
Started Feb 07 02:21:24 PM PST 24
Finished Feb 07 02:21:36 PM PST 24
Peak memory 220072 kb
Host smart-1393ac04-a9a2-42bb-854b-580088850a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666273829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1666273829
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.107728935
Short name T964
Test name
Test status
Simulation time 8729917187 ps
CPU time 4.45 seconds
Started Feb 07 02:21:25 PM PST 24
Finished Feb 07 02:21:30 PM PST 24
Peak memory 203768 kb
Host smart-1f1d0b0e-0d43-42fc-be82-c5190aae273c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107728935 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.107728935
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.732500148
Short name T882
Test name
Test status
Simulation time 10212352781 ps
CPU time 50.35 seconds
Started Feb 07 02:21:29 PM PST 24
Finished Feb 07 02:22:21 PM PST 24
Peak memory 485448 kb
Host smart-0bf8a45c-dd83-463f-a76a-87a04b76cfff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732500148 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.732500148
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3270577080
Short name T98
Test name
Test status
Simulation time 10087030481 ps
CPU time 24.97 seconds
Started Feb 07 02:21:24 PM PST 24
Finished Feb 07 02:21:50 PM PST 24
Peak memory 385040 kb
Host smart-9856942a-f7da-4895-adb3-7c1320503214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270577080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3270577080
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.41292842
Short name T921
Test name
Test status
Simulation time 641194316 ps
CPU time 2.7 seconds
Started Feb 07 02:21:32 PM PST 24
Finished Feb 07 02:21:35 PM PST 24
Peak memory 203628 kb
Host smart-f9671c42-79df-4598-bc5d-89844bd26eec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41292842 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.i2c_target_hrst.41292842
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.531501890
Short name T284
Test name
Test status
Simulation time 6336002377 ps
CPU time 4.37 seconds
Started Feb 07 02:21:22 PM PST 24
Finished Feb 07 02:21:28 PM PST 24
Peak memory 203816 kb
Host smart-f11fb032-cccd-4564-bc16-c208e65a95f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531501890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.531501890
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3116712265
Short name T715
Test name
Test status
Simulation time 14107942781 ps
CPU time 54.06 seconds
Started Feb 07 02:21:23 PM PST 24
Finished Feb 07 02:22:18 PM PST 24
Peak memory 915112 kb
Host smart-013f092a-5fd3-4a0d-bf76-61ac65d2c9b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116712265 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3116712265
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3993844247
Short name T505
Test name
Test status
Simulation time 2690834126 ps
CPU time 4.04 seconds
Started Feb 07 02:21:28 PM PST 24
Finished Feb 07 02:21:33 PM PST 24
Peak memory 207048 kb
Host smart-7d61ba51-af49-4954-a341-61e356cb6e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993844247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3993844247
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3145856574
Short name T1453
Test name
Test status
Simulation time 15515465976 ps
CPU time 22.15 seconds
Started Feb 07 02:21:18 PM PST 24
Finished Feb 07 02:21:42 PM PST 24
Peak memory 203728 kb
Host smart-e3cead93-0444-43e1-8d8e-03ba08face81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145856574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3145856574
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.4098843522
Short name T1247
Test name
Test status
Simulation time 39242750292 ps
CPU time 68.12 seconds
Started Feb 07 02:21:30 PM PST 24
Finished Feb 07 02:22:39 PM PST 24
Peak memory 377824 kb
Host smart-c67093b0-e57c-47ec-a72a-b6d37bb518a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098843522 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.4098843522
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2564936486
Short name T271
Test name
Test status
Simulation time 1320096257 ps
CPU time 21.95 seconds
Started Feb 07 02:21:21 PM PST 24
Finished Feb 07 02:21:44 PM PST 24
Peak memory 208988 kb
Host smart-dd118614-09c8-4e2e-a2c7-4db84dccce34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564936486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2564936486
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3764020072
Short name T1126
Test name
Test status
Simulation time 35958290641 ps
CPU time 468.21 seconds
Started Feb 07 02:21:20 PM PST 24
Finished Feb 07 02:29:10 PM PST 24
Peak memory 4025824 kb
Host smart-b5570175-5fba-496d-b75b-1376b77d7255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764020072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3764020072
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1567116064
Short name T1530
Test name
Test status
Simulation time 19542962431 ps
CPU time 143.78 seconds
Started Feb 07 02:21:21 PM PST 24
Finished Feb 07 02:23:46 PM PST 24
Peak memory 1242472 kb
Host smart-58de2797-f914-4bba-87df-ce4ffa9ecc76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567116064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1567116064
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2373399293
Short name T237
Test name
Test status
Simulation time 1909991999 ps
CPU time 7.81 seconds
Started Feb 07 02:21:28 PM PST 24
Finished Feb 07 02:21:36 PM PST 24
Peak memory 209044 kb
Host smart-f8bd5d9e-7298-4e14-bad1-7d1294633b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373399293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2373399293
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_ovf.3413190531
Short name T607
Test name
Test status
Simulation time 11447516463 ps
CPU time 61.51 seconds
Started Feb 07 02:21:30 PM PST 24
Finished Feb 07 02:22:32 PM PST 24
Peak memory 317280 kb
Host smart-cb72c3c8-bd03-4a95-b104-e1c86065d2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413190531 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_tx_ovf.3413190531
Directory /workspace/17.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.2539591608
Short name T1326
Test name
Test status
Simulation time 973580004 ps
CPU time 5.41 seconds
Started Feb 07 02:21:32 PM PST 24
Finished Feb 07 02:21:38 PM PST 24
Peak memory 203628 kb
Host smart-a4ee3492-04fa-4337-8f0a-ceda905afd1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539591608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.2539591608
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3450478668
Short name T1099
Test name
Test status
Simulation time 25036912 ps
CPU time 0.59 seconds
Started Feb 07 02:21:43 PM PST 24
Finished Feb 07 02:21:47 PM PST 24
Peak memory 202164 kb
Host smart-81bcb534-6b17-47d9-8dbc-e7b28fa35f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450478668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3450478668
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3789449757
Short name T890
Test name
Test status
Simulation time 45637582 ps
CPU time 1.32 seconds
Started Feb 07 02:21:33 PM PST 24
Finished Feb 07 02:21:36 PM PST 24
Peak memory 211820 kb
Host smart-a8b81a94-9da4-47b6-bc8c-c1ab320174ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789449757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3789449757
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2341232484
Short name T879
Test name
Test status
Simulation time 1079997886 ps
CPU time 12.73 seconds
Started Feb 07 02:21:35 PM PST 24
Finished Feb 07 02:21:50 PM PST 24
Peak memory 253320 kb
Host smart-56b08c7c-4c51-4054-8485-ea8ec36f4c80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341232484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2341232484
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3509681817
Short name T616
Test name
Test status
Simulation time 8325955431 ps
CPU time 136.86 seconds
Started Feb 07 02:21:33 PM PST 24
Finished Feb 07 02:23:52 PM PST 24
Peak memory 660636 kb
Host smart-8bd8171e-4812-4491-9c32-45f4503700db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509681817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3509681817
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1436452483
Short name T489
Test name
Test status
Simulation time 22242148667 ps
CPU time 319.28 seconds
Started Feb 07 02:21:34 PM PST 24
Finished Feb 07 02:26:55 PM PST 24
Peak memory 1535456 kb
Host smart-812ae2ce-dc79-4361-b5db-f96ba7b9f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436452483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1436452483
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3950542184
Short name T905
Test name
Test status
Simulation time 1355102402 ps
CPU time 0.87 seconds
Started Feb 07 02:21:34 PM PST 24
Finished Feb 07 02:21:37 PM PST 24
Peak memory 203428 kb
Host smart-f25b8fce-5395-45a1-9717-72d9c0fea473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950542184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3950542184
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2832645737
Short name T948
Test name
Test status
Simulation time 168537422 ps
CPU time 4.95 seconds
Started Feb 07 02:21:34 PM PST 24
Finished Feb 07 02:21:41 PM PST 24
Peak memory 234236 kb
Host smart-58c5f516-9ed5-4ffa-b223-ac4c67862209
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832645737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2832645737
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1936087305
Short name T1483
Test name
Test status
Simulation time 33446975292 ps
CPU time 670.34 seconds
Started Feb 07 02:21:37 PM PST 24
Finished Feb 07 02:32:52 PM PST 24
Peak memory 1652668 kb
Host smart-06de2e53-7428-4683-8c60-e3608a6578fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936087305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1936087305
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3027903098
Short name T725
Test name
Test status
Simulation time 5154693581 ps
CPU time 97.27 seconds
Started Feb 07 02:21:44 PM PST 24
Finished Feb 07 02:23:24 PM PST 24
Peak memory 341384 kb
Host smart-15a12c70-e7ab-4235-adb1-97123afe7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027903098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3027903098
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2096085140
Short name T1327
Test name
Test status
Simulation time 17628908 ps
CPU time 0.64 seconds
Started Feb 07 02:21:35 PM PST 24
Finished Feb 07 02:21:37 PM PST 24
Peak memory 202580 kb
Host smart-6b9b0c7c-5f01-4456-bf3d-b7aa1c400987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096085140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2096085140
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.228140331
Short name T548
Test name
Test status
Simulation time 13586184899 ps
CPU time 46.93 seconds
Started Feb 07 02:21:34 PM PST 24
Finished Feb 07 02:22:23 PM PST 24
Peak memory 211940 kb
Host smart-5f2b9347-6a48-4c0c-9ed0-02f819869240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228140331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.228140331
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.2664425995
Short name T991
Test name
Test status
Simulation time 4177891658 ps
CPU time 171.87 seconds
Started Feb 07 02:21:36 PM PST 24
Finished Feb 07 02:24:33 PM PST 24
Peak memory 306760 kb
Host smart-d280dd72-8361-40de-a3cf-0bbf3e656993
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664425995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample
.2664425995
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.4062417040
Short name T625
Test name
Test status
Simulation time 2716852728 ps
CPU time 166.19 seconds
Started Feb 07 02:21:33 PM PST 24
Finished Feb 07 02:24:20 PM PST 24
Peak memory 265440 kb
Host smart-0bf67b7b-0af4-4dd4-81d8-0f51b2395c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062417040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.4062417040
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3459553159
Short name T1282
Test name
Test status
Simulation time 9084078274 ps
CPU time 911 seconds
Started Feb 07 02:21:32 PM PST 24
Finished Feb 07 02:36:44 PM PST 24
Peak memory 1039468 kb
Host smart-7b767acc-4af8-4e41-8917-ff747a328152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459553159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3459553159
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3693434158
Short name T1274
Test name
Test status
Simulation time 1508641146 ps
CPU time 33.5 seconds
Started Feb 07 02:21:32 PM PST 24
Finished Feb 07 02:22:07 PM PST 24
Peak memory 211720 kb
Host smart-b8253c4d-61af-4558-ab07-e73383dbb641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693434158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3693434158
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2951178921
Short name T461
Test name
Test status
Simulation time 943402119 ps
CPU time 3.55 seconds
Started Feb 07 02:21:39 PM PST 24
Finished Feb 07 02:21:46 PM PST 24
Peak memory 203456 kb
Host smart-0e2c59bd-91b4-4008-beda-252f83cffa87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951178921 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2951178921
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2872741720
Short name T62
Test name
Test status
Simulation time 10429894291 ps
CPU time 11.74 seconds
Started Feb 07 02:21:38 PM PST 24
Finished Feb 07 02:21:55 PM PST 24
Peak memory 268484 kb
Host smart-1aefdcc5-6f47-4ce2-aa66-de62beb6d7b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872741720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2872741720
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3747263895
Short name T854
Test name
Test status
Simulation time 10311065743 ps
CPU time 14.77 seconds
Started Feb 07 02:21:36 PM PST 24
Finished Feb 07 02:21:55 PM PST 24
Peak memory 332024 kb
Host smart-45ce9b04-8ab8-483e-9251-e068f5648266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747263895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3747263895
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3805572114
Short name T652
Test name
Test status
Simulation time 759038946 ps
CPU time 2.92 seconds
Started Feb 07 02:21:36 PM PST 24
Finished Feb 07 02:21:43 PM PST 24
Peak memory 203600 kb
Host smart-d826bb7b-a986-4616-b2ab-e2b981a3cc90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805572114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3805572114
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1131795034
Short name T1162
Test name
Test status
Simulation time 1012492173 ps
CPU time 4.68 seconds
Started Feb 07 02:21:37 PM PST 24
Finished Feb 07 02:21:46 PM PST 24
Peak memory 208404 kb
Host smart-5e1e01bc-c7b5-42ff-9551-c16c0d2ea215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131795034 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1131795034
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2167325274
Short name T531
Test name
Test status
Simulation time 14037895481 ps
CPU time 145.34 seconds
Started Feb 07 02:21:38 PM PST 24
Finished Feb 07 02:24:08 PM PST 24
Peak memory 1715340 kb
Host smart-84f1def5-c76c-4369-8067-69e3dbe4d127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167325274 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2167325274
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.4066307800
Short name T1385
Test name
Test status
Simulation time 13252837580 ps
CPU time 4.29 seconds
Started Feb 07 02:21:36 PM PST 24
Finished Feb 07 02:21:46 PM PST 24
Peak memory 208232 kb
Host smart-9781b148-9014-49e1-8364-ad5515a7ecf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066307800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.4066307800
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1200997760
Short name T222
Test name
Test status
Simulation time 10988449151 ps
CPU time 24 seconds
Started Feb 07 02:21:32 PM PST 24
Finished Feb 07 02:21:57 PM PST 24
Peak memory 203728 kb
Host smart-9e7b70a5-dafa-4662-98d1-fde991e47c84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200997760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1200997760
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2062390229
Short name T267
Test name
Test status
Simulation time 3420403527 ps
CPU time 29.77 seconds
Started Feb 07 02:21:38 PM PST 24
Finished Feb 07 02:22:13 PM PST 24
Peak memory 219676 kb
Host smart-1204ad07-0cf9-4dd2-bf29-6ffc18bc2880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062390229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2062390229
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.180627880
Short name T1128
Test name
Test status
Simulation time 11154856459 ps
CPU time 16.44 seconds
Started Feb 07 02:21:34 PM PST 24
Finished Feb 07 02:21:53 PM PST 24
Peak memory 547760 kb
Host smart-3a5101e9-cf80-4b96-b411-635ba18f0f42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180627880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.180627880
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3747448596
Short name T1148
Test name
Test status
Simulation time 36874367476 ps
CPU time 860.44 seconds
Started Feb 07 02:21:37 PM PST 24
Finished Feb 07 02:36:03 PM PST 24
Peak memory 3423676 kb
Host smart-993fde3f-d122-48d8-a1a9-250827a1fba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747448596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3747448596
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1798419199
Short name T722
Test name
Test status
Simulation time 2279108963 ps
CPU time 7.8 seconds
Started Feb 07 02:21:36 PM PST 24
Finished Feb 07 02:21:48 PM PST 24
Peak memory 203740 kb
Host smart-339beede-cf66-4d6b-bed1-f940e5b13f8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798419199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1798419199
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_ovf.743703939
Short name T479
Test name
Test status
Simulation time 9787782484 ps
CPU time 98.06 seconds
Started Feb 07 02:21:35 PM PST 24
Finished Feb 07 02:23:15 PM PST 24
Peak memory 348140 kb
Host smart-64c0aa7d-c6d4-47f3-aec5-9d723e1a78ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743703939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_tx_ovf.743703939
Directory /workspace/18.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.4266265020
Short name T39
Test name
Test status
Simulation time 4117281549 ps
CPU time 5.56 seconds
Started Feb 07 02:21:32 PM PST 24
Finished Feb 07 02:21:39 PM PST 24
Peak memory 206796 kb
Host smart-63b73b5a-ef6c-412b-9a9d-e6f164d597a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266265020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.4266265020
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1261848110
Short name T624
Test name
Test status
Simulation time 17471559 ps
CPU time 0.7 seconds
Started Feb 07 02:22:01 PM PST 24
Finished Feb 07 02:22:03 PM PST 24
Peak memory 202352 kb
Host smart-2a7a1bc7-ac39-4638-bc5b-46533295122c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261848110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1261848110
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2322918503
Short name T1487
Test name
Test status
Simulation time 398306682 ps
CPU time 1.36 seconds
Started Feb 07 02:21:44 PM PST 24
Finished Feb 07 02:21:48 PM PST 24
Peak memory 215300 kb
Host smart-57bc8539-1716-48bc-a936-ae2fb658bbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322918503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2322918503
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.146445893
Short name T480
Test name
Test status
Simulation time 387645653 ps
CPU time 17.8 seconds
Started Feb 07 02:21:47 PM PST 24
Finished Feb 07 02:22:06 PM PST 24
Peak memory 234860 kb
Host smart-202dc5ea-eb9c-4706-90a7-a336743de237
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146445893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.146445893
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1431697022
Short name T1331
Test name
Test status
Simulation time 8650500565 ps
CPU time 138.95 seconds
Started Feb 07 02:21:54 PM PST 24
Finished Feb 07 02:24:14 PM PST 24
Peak memory 1002780 kb
Host smart-91a657b1-aff8-4c36-a93b-d701153514d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431697022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1431697022
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3066425709
Short name T661
Test name
Test status
Simulation time 4483413685 ps
CPU time 261.61 seconds
Started Feb 07 02:21:43 PM PST 24
Finished Feb 07 02:26:08 PM PST 24
Peak memory 1289988 kb
Host smart-0ba90e64-8a94-4055-a28a-8e8ea16664eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066425709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3066425709
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3544133126
Short name T202
Test name
Test status
Simulation time 153411280 ps
CPU time 0.86 seconds
Started Feb 07 02:21:44 PM PST 24
Finished Feb 07 02:21:48 PM PST 24
Peak memory 203428 kb
Host smart-26acf203-aac8-4cf7-8e1b-8d84635cf4bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544133126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3544133126
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2651938363
Short name T734
Test name
Test status
Simulation time 203643039 ps
CPU time 10.51 seconds
Started Feb 07 02:21:44 PM PST 24
Finished Feb 07 02:21:57 PM PST 24
Peak memory 203520 kb
Host smart-37ccdbc7-476c-4789-8ebc-80e220f6b1fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651938363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2651938363
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.171251821
Short name T576
Test name
Test status
Simulation time 6161048203 ps
CPU time 396.21 seconds
Started Feb 07 02:21:47 PM PST 24
Finished Feb 07 02:28:24 PM PST 24
Peak memory 1772360 kb
Host smart-724b0ed5-9c60-401b-89c1-69cf115bd49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171251821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.171251821
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.124632997
Short name T926
Test name
Test status
Simulation time 6540128528 ps
CPU time 165.43 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:24:50 PM PST 24
Peak memory 245544 kb
Host smart-108959eb-43b1-41b7-aff4-72da7193298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124632997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.124632997
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3710301467
Short name T1285
Test name
Test status
Simulation time 60392055 ps
CPU time 0.62 seconds
Started Feb 07 02:21:51 PM PST 24
Finished Feb 07 02:21:53 PM PST 24
Peak memory 202516 kb
Host smart-cb960382-abca-40dc-802a-66aee174eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710301467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3710301467
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.35204569
Short name T685
Test name
Test status
Simulation time 10672682141 ps
CPU time 225.92 seconds
Started Feb 07 02:21:44 PM PST 24
Finished Feb 07 02:25:33 PM PST 24
Peak memory 291144 kb
Host smart-e2610e2d-8ae2-4b0e-9906-7a0bc30f6556
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35204569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample.35204569
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3171533282
Short name T241
Test name
Test status
Simulation time 5372557716 ps
CPU time 33.83 seconds
Started Feb 07 02:21:44 PM PST 24
Finished Feb 07 02:22:20 PM PST 24
Peak memory 294248 kb
Host smart-6c5f5126-7b99-4b7f-a8a4-87dbd2408a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171533282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3171533282
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3941473578
Short name T668
Test name
Test status
Simulation time 45390100796 ps
CPU time 1596.73 seconds
Started Feb 07 02:21:45 PM PST 24
Finished Feb 07 02:48:24 PM PST 24
Peak memory 876032 kb
Host smart-96f70a86-1c26-4359-a384-86f472b24587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941473578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3941473578
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2533508334
Short name T1309
Test name
Test status
Simulation time 1417814059 ps
CPU time 33.22 seconds
Started Feb 07 02:21:43 PM PST 24
Finished Feb 07 02:22:20 PM PST 24
Peak memory 211860 kb
Host smart-b7ffcf85-fa57-4c14-9c6e-e531ff30d9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533508334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2533508334
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.871006772
Short name T1066
Test name
Test status
Simulation time 953817222 ps
CPU time 4.06 seconds
Started Feb 07 02:21:56 PM PST 24
Finished Feb 07 02:22:01 PM PST 24
Peak memory 203564 kb
Host smart-21351a5a-90bc-4e27-a9e0-c5305ae0b281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871006772 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.871006772
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3363725010
Short name T902
Test name
Test status
Simulation time 10086286128 ps
CPU time 68.52 seconds
Started Feb 07 02:21:55 PM PST 24
Finished Feb 07 02:23:04 PM PST 24
Peak memory 610652 kb
Host smart-9d1b72c1-db46-4eb9-bc19-9bbd78b1b32b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363725010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3363725010
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2957654832
Short name T799
Test name
Test status
Simulation time 10375932568 ps
CPU time 24.02 seconds
Started Feb 07 02:21:56 PM PST 24
Finished Feb 07 02:22:21 PM PST 24
Peak memory 356848 kb
Host smart-95e579fe-16c5-4fd5-916f-bfa978a5487c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957654832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2957654832
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1010886689
Short name T322
Test name
Test status
Simulation time 1752940425 ps
CPU time 2.46 seconds
Started Feb 07 02:21:57 PM PST 24
Finished Feb 07 02:22:00 PM PST 24
Peak memory 203656 kb
Host smart-0abf8a49-eb19-4e3b-abc0-7bfe62949e73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010886689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1010886689
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.485887683
Short name T593
Test name
Test status
Simulation time 3887877005 ps
CPU time 4.23 seconds
Started Feb 07 02:21:55 PM PST 24
Finished Feb 07 02:22:00 PM PST 24
Peak memory 204688 kb
Host smart-2d92f255-1667-4e57-811c-a4cfa4692998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485887683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.485887683
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3573103403
Short name T740
Test name
Test status
Simulation time 14755478374 ps
CPU time 49.37 seconds
Started Feb 07 02:21:48 PM PST 24
Finished Feb 07 02:22:38 PM PST 24
Peak memory 796264 kb
Host smart-20f20b7c-b0fe-4be8-88cf-9bda854eb41a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573103403 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3573103403
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.4192352177
Short name T401
Test name
Test status
Simulation time 3073518206 ps
CPU time 4.62 seconds
Started Feb 07 02:21:47 PM PST 24
Finished Feb 07 02:21:53 PM PST 24
Peak memory 203736 kb
Host smart-0db8ebfe-bad6-4b76-8c01-a972421089d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192352177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.4192352177
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2603485235
Short name T444
Test name
Test status
Simulation time 2628758610 ps
CPU time 14.06 seconds
Started Feb 07 02:21:46 PM PST 24
Finished Feb 07 02:22:01 PM PST 24
Peak memory 203728 kb
Host smart-bf513692-13d5-43d6-8576-bef87547f352
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603485235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2603485235
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3095541185
Short name T662
Test name
Test status
Simulation time 1528817088 ps
CPU time 60.16 seconds
Started Feb 07 02:21:45 PM PST 24
Finished Feb 07 02:22:47 PM PST 24
Peak memory 203624 kb
Host smart-be252f5c-b70a-4108-a25a-c8f22bede82f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095541185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3095541185
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2876564651
Short name T28
Test name
Test status
Simulation time 1454495340 ps
CPU time 6.51 seconds
Started Feb 07 02:21:55 PM PST 24
Finished Feb 07 02:22:02 PM PST 24
Peak memory 203560 kb
Host smart-228e77ae-9fe7-4af5-b309-5e330a32fb72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876564651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2876564651
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_ovf.1322468974
Short name T158
Test name
Test status
Simulation time 2892784987 ps
CPU time 87.24 seconds
Started Feb 07 02:21:55 PM PST 24
Finished Feb 07 02:23:23 PM PST 24
Peak memory 307956 kb
Host smart-8c9e8c6b-483d-436c-9680-3f2cb88de3bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322468974 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_tx_ovf.1322468974
Directory /workspace/19.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.589391672
Short name T1033
Test name
Test status
Simulation time 2603831833 ps
CPU time 5.98 seconds
Started Feb 07 02:21:55 PM PST 24
Finished Feb 07 02:22:02 PM PST 24
Peak memory 203672 kb
Host smart-8ffa15b0-700a-4739-8a29-f21a33dc7e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589391672 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_unexp_stop.589391672
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.634843805
Short name T101
Test name
Test status
Simulation time 16098488 ps
CPU time 0.59 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:18:45 PM PST 24
Peak memory 203160 kb
Host smart-e4d9bf76-d8e5-4a8c-bc67-bb93f2016fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634843805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.634843805
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1465044837
Short name T397
Test name
Test status
Simulation time 110811239 ps
CPU time 1.91 seconds
Started Feb 07 02:18:41 PM PST 24
Finished Feb 07 02:18:43 PM PST 24
Peak memory 211808 kb
Host smart-11913e1c-5222-4358-b6b8-6a1534282075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465044837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1465044837
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1996514829
Short name T603
Test name
Test status
Simulation time 603141998 ps
CPU time 5.63 seconds
Started Feb 07 02:18:46 PM PST 24
Finished Feb 07 02:18:57 PM PST 24
Peak memory 266896 kb
Host smart-09528b57-5799-409e-8c72-00f8261116be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996514829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1996514829
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1761394229
Short name T985
Test name
Test status
Simulation time 5458942634 ps
CPU time 215.92 seconds
Started Feb 07 02:18:43 PM PST 24
Finished Feb 07 02:22:19 PM PST 24
Peak memory 868412 kb
Host smart-8eea66ec-e4ab-4583-8143-75460549dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761394229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1761394229
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1724319155
Short name T344
Test name
Test status
Simulation time 33826982722 ps
CPU time 525.34 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:27:20 PM PST 24
Peak memory 1266912 kb
Host smart-b9be6656-a41a-401c-8442-07ccf2f7bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724319155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1724319155
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2901471151
Short name T1420
Test name
Test status
Simulation time 262043688 ps
CPU time 1.13 seconds
Started Feb 07 02:18:38 PM PST 24
Finished Feb 07 02:18:40 PM PST 24
Peak memory 203596 kb
Host smart-b998b359-2ebe-475d-9fe4-8f398c4cc885
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901471151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2901471151
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.810997511
Short name T835
Test name
Test status
Simulation time 546450285 ps
CPU time 4.58 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:18:50 PM PST 24
Peak memory 227572 kb
Host smart-46d99cbe-8c33-4e33-99e3-1158692a226a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810997511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.810997511
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.123700499
Short name T1325
Test name
Test status
Simulation time 11645734809 ps
CPU time 271.89 seconds
Started Feb 07 02:18:29 PM PST 24
Finished Feb 07 02:23:02 PM PST 24
Peak memory 1495540 kb
Host smart-cbe84400-3006-434d-b881-6f4afb572ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123700499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.123700499
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.176105518
Short name T1519
Test name
Test status
Simulation time 7425005426 ps
CPU time 98.62 seconds
Started Feb 07 02:18:41 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 244560 kb
Host smart-703b2971-6350-4173-8945-6538e053e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176105518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.176105518
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.3187247744
Short name T1442
Test name
Test status
Simulation time 17065306 ps
CPU time 0.63 seconds
Started Feb 07 02:18:32 PM PST 24
Finished Feb 07 02:18:34 PM PST 24
Peak memory 202700 kb
Host smart-ef01ee4a-c60b-4f17-a0b3-f82fb86688c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187247744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3187247744
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1647368516
Short name T1480
Test name
Test status
Simulation time 76865037919 ps
CPU time 1058.38 seconds
Started Feb 07 02:18:45 PM PST 24
Finished Feb 07 02:36:25 PM PST 24
Peak memory 316292 kb
Host smart-90ee30d6-6861-4177-815e-4d27e7669b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647368516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1647368516
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_rx_oversample.1246115567
Short name T610
Test name
Test status
Simulation time 5110802068 ps
CPU time 74.64 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:19:45 PM PST 24
Peak memory 248096 kb
Host smart-e669d71e-34d3-4c58-bba0-91bcef2c5faf
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246115567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_rx_oversample.
1246115567
Directory /workspace/2.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3745832019
Short name T1026
Test name
Test status
Simulation time 1610893809 ps
CPU time 92.31 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:20:07 PM PST 24
Peak memory 244356 kb
Host smart-a0f298d9-47ba-43d8-a513-1e8405f124be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745832019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3745832019
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.429538555
Short name T188
Test name
Test status
Simulation time 2913448146 ps
CPU time 22.89 seconds
Started Feb 07 02:18:42 PM PST 24
Finished Feb 07 02:19:05 PM PST 24
Peak memory 228356 kb
Host smart-145860fc-bddf-43a4-a71d-030a7ae683c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429538555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.429538555
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2927323016
Short name T430
Test name
Test status
Simulation time 1077588088 ps
CPU time 47.42 seconds
Started Feb 07 02:18:43 PM PST 24
Finished Feb 07 02:19:31 PM PST 24
Peak memory 219980 kb
Host smart-cdaf60e1-c806-4685-bc94-d74c9e26635d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927323016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2927323016
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2077656320
Short name T93
Test name
Test status
Simulation time 233462992 ps
CPU time 0.92 seconds
Started Feb 07 02:18:43 PM PST 24
Finished Feb 07 02:18:44 PM PST 24
Peak memory 220880 kb
Host smart-2bc0acc2-3c7a-4831-ad99-6cc72e402f22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077656320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2077656320
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.4126374620
Short name T559
Test name
Test status
Simulation time 1132515659 ps
CPU time 4.14 seconds
Started Feb 07 02:18:40 PM PST 24
Finished Feb 07 02:18:45 PM PST 24
Peak memory 203696 kb
Host smart-d5777979-0f4b-4d3c-9703-fadf08fbb62b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126374620 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.4126374620
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1016229203
Short name T1276
Test name
Test status
Simulation time 10219029710 ps
CPU time 18.12 seconds
Started Feb 07 02:18:42 PM PST 24
Finished Feb 07 02:19:01 PM PST 24
Peak memory 358780 kb
Host smart-ebe9ace7-61e5-43ab-9648-bb9a4a867367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016229203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1016229203
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.4052480746
Short name T778
Test name
Test status
Simulation time 10063882453 ps
CPU time 105.02 seconds
Started Feb 07 02:18:46 PM PST 24
Finished Feb 07 02:20:32 PM PST 24
Peak memory 689132 kb
Host smart-240d1593-77a6-4c91-89bb-c6c44e5f20d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052480746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.4052480746
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3279862194
Short name T150
Test name
Test status
Simulation time 931182430 ps
CPU time 2.37 seconds
Started Feb 07 02:18:41 PM PST 24
Finished Feb 07 02:18:44 PM PST 24
Peak memory 203588 kb
Host smart-c44678b9-e843-4d0e-8d4b-2d6c3b43a12d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279862194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3279862194
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2605714634
Short name T1287
Test name
Test status
Simulation time 833359031 ps
CPU time 4.07 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:18:49 PM PST 24
Peak memory 203684 kb
Host smart-4ac1b431-6bd8-46ca-b39b-68995040a9b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605714634 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2605714634
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3256970503
Short name T912
Test name
Test status
Simulation time 12270732290 ps
CPU time 283.4 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:23:29 PM PST 24
Peak memory 2736108 kb
Host smart-2dcf818f-f3b8-4162-9327-5c28faa78a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256970503 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3256970503
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.2791082075
Short name T557
Test name
Test status
Simulation time 5294719626 ps
CPU time 5.22 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:18:51 PM PST 24
Peak memory 212056 kb
Host smart-a6890b13-c22e-4f6d-8229-2cdf55821140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791082075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.2791082075
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.146033360
Short name T976
Test name
Test status
Simulation time 1115637245 ps
CPU time 11.06 seconds
Started Feb 07 02:18:41 PM PST 24
Finished Feb 07 02:18:53 PM PST 24
Peak memory 203504 kb
Host smart-f1bad427-45ee-4eee-9acc-2c44540d16b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146033360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.146033360
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3640301173
Short name T1182
Test name
Test status
Simulation time 8791923082 ps
CPU time 37.65 seconds
Started Feb 07 02:18:39 PM PST 24
Finished Feb 07 02:19:18 PM PST 24
Peak memory 226488 kb
Host smart-ad4913da-de08-45f4-90e7-48a3a40b933d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640301173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3640301173
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2590261812
Short name T240
Test name
Test status
Simulation time 42302815203 ps
CPU time 677.01 seconds
Started Feb 07 02:18:43 PM PST 24
Finished Feb 07 02:30:01 PM PST 24
Peak memory 4873548 kb
Host smart-a067628c-713f-4bbb-bde7-e777bd9f323e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590261812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2590261812
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.893789502
Short name T1103
Test name
Test status
Simulation time 9240443676 ps
CPU time 102.31 seconds
Started Feb 07 02:18:43 PM PST 24
Finished Feb 07 02:20:26 PM PST 24
Peak memory 1031144 kb
Host smart-b33fbfe6-8543-4bfa-a2ee-777ad8cbba52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893789502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.893789502
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1124948656
Short name T917
Test name
Test status
Simulation time 2404479037 ps
CPU time 9.8 seconds
Started Feb 07 02:18:45 PM PST 24
Finished Feb 07 02:18:57 PM PST 24
Peak memory 203808 kb
Host smart-5f8fd125-0672-4aed-b64a-d2a9f7f47651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124948656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1124948656
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_ovf.719096988
Short name T598
Test name
Test status
Simulation time 10240677705 ps
CPU time 41.76 seconds
Started Feb 07 02:18:42 PM PST 24
Finished Feb 07 02:19:24 PM PST 24
Peak memory 219380 kb
Host smart-bcb462a9-3749-4a4f-9774-b52cb69a4f92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719096988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_tx_ovf.719096988
Directory /workspace/2.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.3085140974
Short name T581
Test name
Test status
Simulation time 1083473171 ps
CPU time 6.39 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:18:52 PM PST 24
Peak memory 203656 kb
Host smart-dd6523d7-3115-48d3-bd2a-2989947f9647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085140974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.3085140974
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3129041280
Short name T265
Test name
Test status
Simulation time 16629863 ps
CPU time 0.6 seconds
Started Feb 07 02:22:14 PM PST 24
Finished Feb 07 02:22:16 PM PST 24
Peak memory 203392 kb
Host smart-b6396bac-57b8-4933-a637-bd153fd5fec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129041280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3129041280
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1961024498
Short name T1463
Test name
Test status
Simulation time 118053749 ps
CPU time 1.51 seconds
Started Feb 07 02:22:05 PM PST 24
Finished Feb 07 02:22:08 PM PST 24
Peak memory 219996 kb
Host smart-4f0c6945-c7e0-4a20-bfc9-229e7e81054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961024498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1961024498
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.4063597205
Short name T1278
Test name
Test status
Simulation time 728954646 ps
CPU time 7.7 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:22:12 PM PST 24
Peak memory 273848 kb
Host smart-abef9398-3e22-4438-991a-74b72df42295
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063597205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.4063597205
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1747021725
Short name T408
Test name
Test status
Simulation time 2997677886 ps
CPU time 59.11 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:23:03 PM PST 24
Peak memory 502536 kb
Host smart-cbe71c6a-a4f4-4437-831e-0aa6300e57d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747021725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1747021725
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.425937264
Short name T896
Test name
Test status
Simulation time 11335946113 ps
CPU time 818.25 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:35:43 PM PST 24
Peak memory 1590780 kb
Host smart-aa446f18-271a-4344-ae58-8fd7d00c2007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425937264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.425937264
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1761508618
Short name T530
Test name
Test status
Simulation time 358278209 ps
CPU time 0.95 seconds
Started Feb 07 02:22:05 PM PST 24
Finished Feb 07 02:22:07 PM PST 24
Peak memory 203620 kb
Host smart-cc11a9bd-786b-40e6-843b-cfac650cbf9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761508618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1761508618
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2079611954
Short name T305
Test name
Test status
Simulation time 293069054 ps
CPU time 3.4 seconds
Started Feb 07 02:22:01 PM PST 24
Finished Feb 07 02:22:05 PM PST 24
Peak memory 203632 kb
Host smart-8fde6b94-a010-4c1b-82d6-a500ef594c25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079611954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2079611954
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2970252432
Short name T995
Test name
Test status
Simulation time 4226530022 ps
CPU time 211.02 seconds
Started Feb 07 02:21:59 PM PST 24
Finished Feb 07 02:25:30 PM PST 24
Peak memory 1247776 kb
Host smart-acffaf69-58a8-420a-bb29-61d492f7af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970252432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2970252432
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3190334060
Short name T56
Test name
Test status
Simulation time 12346739713 ps
CPU time 56.6 seconds
Started Feb 07 02:22:16 PM PST 24
Finished Feb 07 02:23:13 PM PST 24
Peak memory 277864 kb
Host smart-5a6343ff-5233-4e61-93c0-bb2107bf362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190334060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3190334060
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2668325395
Short name T974
Test name
Test status
Simulation time 71072688 ps
CPU time 0.61 seconds
Started Feb 07 02:22:04 PM PST 24
Finished Feb 07 02:22:06 PM PST 24
Peak memory 202644 kb
Host smart-83023436-86d6-400c-be5f-60a6751955f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668325395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2668325395
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3965268260
Short name T579
Test name
Test status
Simulation time 2669171199 ps
CPU time 143.36 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:24:28 PM PST 24
Peak memory 235552 kb
Host smart-8b39c738-0e62-4322-b657-9df7a1751ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965268260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3965268260
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_rx_oversample.3456911962
Short name T1190
Test name
Test status
Simulation time 1414239551 ps
CPU time 34.19 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:22:39 PM PST 24
Peak memory 276988 kb
Host smart-57679601-6638-4049-b09b-9de401b9b49b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456911962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_rx_oversample
.3456911962
Directory /workspace/20.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.199019681
Short name T1045
Test name
Test status
Simulation time 2747229655 ps
CPU time 123.02 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:24:08 PM PST 24
Peak memory 263832 kb
Host smart-5bee5064-63c2-4891-8678-f0cb6e9f7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199019681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.199019681
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1825101347
Short name T423
Test name
Test status
Simulation time 11414483222 ps
CPU time 14.75 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:22:18 PM PST 24
Peak memory 215568 kb
Host smart-1c558fc2-5111-480e-b01e-76b61933d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825101347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1825101347
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.4238968788
Short name T37
Test name
Test status
Simulation time 1528971756 ps
CPU time 5.17 seconds
Started Feb 07 02:22:05 PM PST 24
Finished Feb 07 02:22:11 PM PST 24
Peak memory 203608 kb
Host smart-eb24e11a-fc6b-4e70-9f56-c78f5b7d1196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238968788 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.4238968788
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2594995940
Short name T1222
Test name
Test status
Simulation time 10037926251 ps
CPU time 67.12 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:23:10 PM PST 24
Peak memory 579640 kb
Host smart-a9bef904-92f0-42f0-8a58-a71341261e55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594995940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2594995940
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3340622197
Short name T377
Test name
Test status
Simulation time 10052886203 ps
CPU time 48.98 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:22:53 PM PST 24
Peak memory 525044 kb
Host smart-7d3dbda9-1f92-44c7-b0e7-92b451fc67e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340622197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3340622197
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.277055666
Short name T830
Test name
Test status
Simulation time 1158297343 ps
CPU time 1.94 seconds
Started Feb 07 02:22:17 PM PST 24
Finished Feb 07 02:22:19 PM PST 24
Peak memory 203608 kb
Host smart-cba429d3-2ef8-4418-ac14-0473abbf8364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277055666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.277055666
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.129830932
Short name T1064
Test name
Test status
Simulation time 1496495875 ps
CPU time 5.75 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:22:10 PM PST 24
Peak memory 204440 kb
Host smart-56927448-956e-4f0a-ab06-3a38f7267299
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129830932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.129830932
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2246062775
Short name T1364
Test name
Test status
Simulation time 22207012935 ps
CPU time 198.69 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:25:22 PM PST 24
Peak memory 1828000 kb
Host smart-93be78b0-2327-460d-8a59-297d7e1b1170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246062775 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2246062775
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.3686614526
Short name T1009
Test name
Test status
Simulation time 732277163 ps
CPU time 4.41 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:22:09 PM PST 24
Peak memory 208388 kb
Host smart-c776da82-b133-4690-aac4-b7ad30e40edc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686614526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.3686614526
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.253895824
Short name T503
Test name
Test status
Simulation time 1561647602 ps
CPU time 39.91 seconds
Started Feb 07 02:22:05 PM PST 24
Finished Feb 07 02:22:46 PM PST 24
Peak memory 203624 kb
Host smart-109c274c-040b-408b-81ec-98e6ff1a8ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253895824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.253895824
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.3048319705
Short name T1261
Test name
Test status
Simulation time 31278689627 ps
CPU time 1252.07 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:42:57 PM PST 24
Peak memory 5800692 kb
Host smart-4b020cc7-a18b-48d8-a82a-e11ad59a07d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048319705 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.3048319705
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2150173352
Short name T522
Test name
Test status
Simulation time 532624819 ps
CPU time 8.69 seconds
Started Feb 07 02:22:02 PM PST 24
Finished Feb 07 02:22:12 PM PST 24
Peak memory 203628 kb
Host smart-2d1cee2a-67f4-4083-85c4-bc345ec0b481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150173352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2150173352
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.317474326
Short name T754
Test name
Test status
Simulation time 54472023106 ps
CPU time 3513.58 seconds
Started Feb 07 02:22:04 PM PST 24
Finished Feb 07 03:20:39 PM PST 24
Peak memory 12269060 kb
Host smart-6033e8d7-ae34-43e5-9b1b-9cb24a0fffbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317474326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.317474326
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.125410904
Short name T881
Test name
Test status
Simulation time 35695765724 ps
CPU time 229.47 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:25:54 PM PST 24
Peak memory 1750392 kb
Host smart-417d367a-1781-4a81-82f6-afc9dde71ae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125410904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.125410904
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.990694720
Short name T1053
Test name
Test status
Simulation time 5585289146 ps
CPU time 6.21 seconds
Started Feb 07 02:22:03 PM PST 24
Finished Feb 07 02:22:11 PM PST 24
Peak memory 207584 kb
Host smart-8b567cf0-913b-4155-8425-fa269002b8cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990694720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.990694720
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_ovf.2137011280
Short name T1074
Test name
Test status
Simulation time 10259022038 ps
CPU time 37.77 seconds
Started Feb 07 02:22:01 PM PST 24
Finished Feb 07 02:22:41 PM PST 24
Peak memory 221300 kb
Host smart-8abd42cf-f174-4ebf-b661-4d876ddfed59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137011280 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_tx_ovf.2137011280
Directory /workspace/20.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.622097209
Short name T932
Test name
Test status
Simulation time 4312504055 ps
CPU time 5.27 seconds
Started Feb 07 02:22:05 PM PST 24
Finished Feb 07 02:22:11 PM PST 24
Peak memory 205764 kb
Host smart-553271d9-4802-4937-8ded-77253759b9c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622097209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_unexp_stop.622097209
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3812896738
Short name T532
Test name
Test status
Simulation time 50895281 ps
CPU time 0.6 seconds
Started Feb 07 02:22:24 PM PST 24
Finished Feb 07 02:22:26 PM PST 24
Peak memory 202344 kb
Host smart-58d90a0d-b258-4909-93d8-824a1aba8e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812896738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3812896738
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1171406615
Short name T647
Test name
Test status
Simulation time 53400153 ps
CPU time 1.66 seconds
Started Feb 07 02:22:26 PM PST 24
Finished Feb 07 02:22:29 PM PST 24
Peak memory 211884 kb
Host smart-b9a59c9a-c58b-4b02-8768-9c45488429d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171406615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1171406615
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2311676050
Short name T545
Test name
Test status
Simulation time 635892770 ps
CPU time 35.96 seconds
Started Feb 07 02:22:13 PM PST 24
Finished Feb 07 02:22:50 PM PST 24
Peak memory 350452 kb
Host smart-d7574954-8a4a-4416-8c4f-49474f145c84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311676050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2311676050
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3043652149
Short name T285
Test name
Test status
Simulation time 7489558673 ps
CPU time 96.71 seconds
Started Feb 07 02:22:14 PM PST 24
Finished Feb 07 02:23:51 PM PST 24
Peak memory 858400 kb
Host smart-8b521415-b098-43c7-ba2c-29a0701a738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043652149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3043652149
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.859454695
Short name T466
Test name
Test status
Simulation time 9259607214 ps
CPU time 255.9 seconds
Started Feb 07 02:22:14 PM PST 24
Finished Feb 07 02:26:31 PM PST 24
Peak memory 1385208 kb
Host smart-91e57c1c-d49e-46bd-93df-f799e4a2cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859454695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.859454695
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.72896984
Short name T1524
Test name
Test status
Simulation time 432164284 ps
CPU time 0.88 seconds
Started Feb 07 02:22:13 PM PST 24
Finished Feb 07 02:22:15 PM PST 24
Peak memory 203344 kb
Host smart-9da79591-9d2c-4858-8f61-75894f11b4c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72896984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt
.72896984
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3828692076
Short name T657
Test name
Test status
Simulation time 552641538 ps
CPU time 4.26 seconds
Started Feb 07 02:22:15 PM PST 24
Finished Feb 07 02:22:20 PM PST 24
Peak memory 203584 kb
Host smart-1cee4c81-6136-4a3d-954d-1835f17aab3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828692076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3828692076
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.891738107
Short name T347
Test name
Test status
Simulation time 5238617549 ps
CPU time 258.37 seconds
Started Feb 07 02:22:13 PM PST 24
Finished Feb 07 02:26:33 PM PST 24
Peak memory 1355500 kb
Host smart-6fbf86f9-2564-425d-9d71-26fd4158bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891738107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.891738107
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3506075341
Short name T385
Test name
Test status
Simulation time 2192970048 ps
CPU time 60.9 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:23:28 PM PST 24
Peak memory 317608 kb
Host smart-7f019182-a004-403a-9e6b-4637d9201ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506075341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3506075341
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2968414953
Short name T965
Test name
Test status
Simulation time 18421054 ps
CPU time 0.64 seconds
Started Feb 07 02:22:12 PM PST 24
Finished Feb 07 02:22:13 PM PST 24
Peak memory 202556 kb
Host smart-8daf62af-7df2-4c86-bc3c-2164e30ce70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968414953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2968414953
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3682369019
Short name T646
Test name
Test status
Simulation time 20210571727 ps
CPU time 79.01 seconds
Started Feb 07 02:22:13 PM PST 24
Finished Feb 07 02:23:32 PM PST 24
Peak memory 211968 kb
Host smart-31c79ee9-5f34-4de7-a543-8dd07551d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682369019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3682369019
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.3665938758
Short name T1441
Test name
Test status
Simulation time 2814946852 ps
CPU time 154.38 seconds
Started Feb 07 02:22:13 PM PST 24
Finished Feb 07 02:24:48 PM PST 24
Peak memory 346892 kb
Host smart-cf4286d0-a351-4afd-915e-40e693aa6e36
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665938758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample
.3665938758
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2960052782
Short name T810
Test name
Test status
Simulation time 1228121337 ps
CPU time 72.65 seconds
Started Feb 07 02:22:14 PM PST 24
Finished Feb 07 02:23:28 PM PST 24
Peak memory 245484 kb
Host smart-b005d257-c3ea-4f99-a8e5-c621ba2a5810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960052782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2960052782
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3390530552
Short name T176
Test name
Test status
Simulation time 30879761900 ps
CPU time 1332.1 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:44:38 PM PST 24
Peak memory 2979816 kb
Host smart-2b0f5cd9-eb7c-4782-be42-89d7b12ad1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390530552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3390530552
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2719688300
Short name T373
Test name
Test status
Simulation time 3598446442 ps
CPU time 43.54 seconds
Started Feb 07 02:22:20 PM PST 24
Finished Feb 07 02:23:04 PM PST 24
Peak memory 220128 kb
Host smart-c5d8deb3-580d-4f42-94c0-9f231ed2d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719688300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2719688300
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1276458280
Short name T94
Test name
Test status
Simulation time 3091636297 ps
CPU time 4.77 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:22:31 PM PST 24
Peak memory 203724 kb
Host smart-7cad63d2-bcda-47f0-9662-72977d7bd0bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276458280 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1276458280
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1626068277
Short name T58
Test name
Test status
Simulation time 10157291832 ps
CPU time 13.7 seconds
Started Feb 07 02:22:26 PM PST 24
Finished Feb 07 02:22:41 PM PST 24
Peak memory 311276 kb
Host smart-060f1ead-afa8-47ed-9995-4c561ec9e128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626068277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1626068277
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2150731025
Short name T892
Test name
Test status
Simulation time 1132677467 ps
CPU time 2.62 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:22:28 PM PST 24
Peak memory 203568 kb
Host smart-5dd3207c-97ff-4e28-8435-d566a5757faf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150731025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2150731025
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.4152932010
Short name T1343
Test name
Test status
Simulation time 2658505232 ps
CPU time 7.43 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:22:33 PM PST 24
Peak memory 203776 kb
Host smart-7ce5e03e-e79e-4b6e-ae6f-061c7dd69e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152932010 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.4152932010
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.4007109080
Short name T1345
Test name
Test status
Simulation time 6034298040 ps
CPU time 31.21 seconds
Started Feb 07 02:22:26 PM PST 24
Finished Feb 07 02:22:58 PM PST 24
Peak memory 778048 kb
Host smart-1d3362ac-c894-4a04-be12-7632ee7bfec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007109080 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.4007109080
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.2171264224
Short name T1147
Test name
Test status
Simulation time 1705958911 ps
CPU time 2.59 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:22:28 PM PST 24
Peak memory 203652 kb
Host smart-0f844cb6-cbe9-4a4b-8694-519edd49e0af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171264224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.2171264224
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.2607916602
Short name T609
Test name
Test status
Simulation time 2478305171 ps
CPU time 15.46 seconds
Started Feb 07 02:22:27 PM PST 24
Finished Feb 07 02:22:43 PM PST 24
Peak memory 203716 kb
Host smart-c82f1302-b96b-4462-aa73-bda391db516c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607916602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.2607916602
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.877772056
Short name T1396
Test name
Test status
Simulation time 68130247837 ps
CPU time 1944.4 seconds
Started Feb 07 02:22:26 PM PST 24
Finished Feb 07 02:54:52 PM PST 24
Peak memory 4344472 kb
Host smart-716a8589-1227-46c2-b680-bf369b670c18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877772056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.877772056
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2651014301
Short name T1228
Test name
Test status
Simulation time 698847135 ps
CPU time 28.25 seconds
Started Feb 07 02:22:28 PM PST 24
Finished Feb 07 02:22:57 PM PST 24
Peak memory 203600 kb
Host smart-965678c3-d802-4876-b935-d195009f4322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651014301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2651014301
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2679550128
Short name T851
Test name
Test status
Simulation time 51615380134 ps
CPU time 2943.8 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 03:11:30 PM PST 24
Peak memory 11040300 kb
Host smart-1ccd51bb-0813-4232-a012-77c098f46648
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679550128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2679550128
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3316766503
Short name T2
Test name
Test status
Simulation time 20903301962 ps
CPU time 175.59 seconds
Started Feb 07 02:22:26 PM PST 24
Finished Feb 07 02:25:23 PM PST 24
Peak memory 782780 kb
Host smart-7e5f6747-9c17-4a76-a0f1-8531bf99f1fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316766503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3316766503
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2339440176
Short name T1379
Test name
Test status
Simulation time 2142066084 ps
CPU time 8.12 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:22:35 PM PST 24
Peak memory 215820 kb
Host smart-ef462260-fd37-4dca-b760-503c5a843c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339440176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2339440176
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_ovf.2579745074
Short name T1403
Test name
Test status
Simulation time 16368171514 ps
CPU time 168.53 seconds
Started Feb 07 02:22:25 PM PST 24
Finished Feb 07 02:25:15 PM PST 24
Peak memory 403568 kb
Host smart-0adffa34-5af3-48f2-8ee4-d0aa0f22bc5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579745074 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_tx_ovf.2579745074
Directory /workspace/21.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.2467042089
Short name T558
Test name
Test status
Simulation time 6975827380 ps
CPU time 6.78 seconds
Started Feb 07 02:22:27 PM PST 24
Finished Feb 07 02:22:34 PM PST 24
Peak memory 213824 kb
Host smart-bd34fd60-09d8-42e0-bc75-bf015eb95f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467042089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.2467042089
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1094946370
Short name T494
Test name
Test status
Simulation time 15608022 ps
CPU time 0.6 seconds
Started Feb 07 02:22:52 PM PST 24
Finished Feb 07 02:22:53 PM PST 24
Peak memory 202376 kb
Host smart-e9171c11-ad58-47c5-9e2f-b91ccd52a784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094946370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1094946370
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2644640931
Short name T236
Test name
Test status
Simulation time 115064842 ps
CPU time 1.06 seconds
Started Feb 07 02:22:47 PM PST 24
Finished Feb 07 02:22:48 PM PST 24
Peak memory 211852 kb
Host smart-33561e9b-ae00-4160-a473-2a6fee105ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644640931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2644640931
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3995110745
Short name T821
Test name
Test status
Simulation time 1149778873 ps
CPU time 7.56 seconds
Started Feb 07 02:22:44 PM PST 24
Finished Feb 07 02:22:53 PM PST 24
Peak memory 286116 kb
Host smart-a3364394-5db1-48e9-b4b7-ee230a81a7a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995110745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3995110745
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.841073678
Short name T973
Test name
Test status
Simulation time 51938058819 ps
CPU time 211.01 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:26:26 PM PST 24
Peak memory 850996 kb
Host smart-21b4a373-8291-4600-9074-67b729d6f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841073678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.841073678
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2199877762
Short name T1250
Test name
Test status
Simulation time 4109517875 ps
CPU time 220.81 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 02:26:35 PM PST 24
Peak memory 1174024 kb
Host smart-95cb8860-0a4f-4f38-b147-0ad2fe6b8f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199877762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2199877762
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2974264833
Short name T379
Test name
Test status
Simulation time 1315987476 ps
CPU time 0.8 seconds
Started Feb 07 02:22:47 PM PST 24
Finished Feb 07 02:22:49 PM PST 24
Peak memory 202588 kb
Host smart-9a41f6fc-cdb8-4c56-afd7-75691c66dd6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974264833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2974264833
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2260349256
Short name T320
Test name
Test status
Simulation time 1320534910 ps
CPU time 7.4 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:23:04 PM PST 24
Peak memory 253276 kb
Host smart-b66ff029-9251-4e8b-8e83-035e5cd54ef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260349256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2260349256
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2433806494
Short name T65
Test name
Test status
Simulation time 6859602838 ps
CPU time 148.91 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:25:24 PM PST 24
Peak memory 1043696 kb
Host smart-e0f36862-89c0-456e-81fa-a13126cdf4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433806494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2433806494
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3337503695
Short name T716
Test name
Test status
Simulation time 8175219590 ps
CPU time 103.67 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:24:39 PM PST 24
Peak memory 236308 kb
Host smart-f6cb5b1e-e2eb-4bec-a7d6-2a5ad1829d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337503695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3337503695
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1879768583
Short name T910
Test name
Test status
Simulation time 50861590 ps
CPU time 0.62 seconds
Started Feb 07 02:22:24 PM PST 24
Finished Feb 07 02:22:26 PM PST 24
Peak memory 202576 kb
Host smart-6206a1ed-0495-457e-a2a7-f4a000d341d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879768583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1879768583
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3242468894
Short name T269
Test name
Test status
Simulation time 12306433094 ps
CPU time 708.55 seconds
Started Feb 07 02:22:51 PM PST 24
Finished Feb 07 02:34:40 PM PST 24
Peak memory 362712 kb
Host smart-c126488f-e82f-4df9-bdbf-c76fa13927d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242468894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3242468894
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.803282971
Short name T1468
Test name
Test status
Simulation time 6237199799 ps
CPU time 106.75 seconds
Started Feb 07 02:22:44 PM PST 24
Finished Feb 07 02:24:32 PM PST 24
Peak memory 252660 kb
Host smart-69d85891-b44b-4d42-a01d-fb43a6bf5fc5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803282971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample.
803282971
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1044636823
Short name T758
Test name
Test status
Simulation time 1509125060 ps
CPU time 36.9 seconds
Started Feb 07 02:22:26 PM PST 24
Finished Feb 07 02:23:04 PM PST 24
Peak memory 246744 kb
Host smart-f3fa7a4d-f1f6-48a5-89d4-4b8d0e3e44c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044636823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1044636823
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3728941028
Short name T283
Test name
Test status
Simulation time 728703916 ps
CPU time 30.86 seconds
Started Feb 07 02:22:52 PM PST 24
Finished Feb 07 02:23:24 PM PST 24
Peak memory 211768 kb
Host smart-f3ded606-42bc-4566-ba82-9fe764ccb438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728941028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3728941028
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1982402892
Short name T428
Test name
Test status
Simulation time 5248647031 ps
CPU time 5 seconds
Started Feb 07 02:22:45 PM PST 24
Finished Feb 07 02:22:50 PM PST 24
Peak memory 203700 kb
Host smart-2b59ea41-9b66-470e-a5d2-d149ed77ad3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982402892 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1982402892
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.781288461
Short name T848
Test name
Test status
Simulation time 10147358382 ps
CPU time 10.84 seconds
Started Feb 07 02:22:45 PM PST 24
Finished Feb 07 02:22:56 PM PST 24
Peak memory 252708 kb
Host smart-3606a151-08c7-464f-aa67-713b821f134e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781288461 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.781288461
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3042168027
Short name T208
Test name
Test status
Simulation time 12142070925 ps
CPU time 4.62 seconds
Started Feb 07 02:22:46 PM PST 24
Finished Feb 07 02:22:52 PM PST 24
Peak memory 234328 kb
Host smart-3a6b6407-0cb4-4522-b1a5-64ca835dfc29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042168027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3042168027
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.47567451
Short name T1227
Test name
Test status
Simulation time 875007089 ps
CPU time 2.45 seconds
Started Feb 07 02:22:45 PM PST 24
Finished Feb 07 02:22:48 PM PST 24
Peak memory 203652 kb
Host smart-39b01b5b-1202-43e9-8020-163e396de8c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47567451 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.i2c_target_hrst.47567451
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.845182133
Short name T885
Test name
Test status
Simulation time 1650900844 ps
CPU time 6.45 seconds
Started Feb 07 02:22:47 PM PST 24
Finished Feb 07 02:22:54 PM PST 24
Peak memory 208416 kb
Host smart-b0e45dc8-7aad-45ef-80ef-c0974129c28b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845182133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.845182133
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2690501269
Short name T441
Test name
Test status
Simulation time 4190511293 ps
CPU time 32.59 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:23:29 PM PST 24
Peak memory 809076 kb
Host smart-24172f47-43c3-48cc-8517-4371c989b0d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690501269 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2690501269
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.2294095860
Short name T952
Test name
Test status
Simulation time 622927326 ps
CPU time 3.68 seconds
Started Feb 07 02:22:44 PM PST 24
Finished Feb 07 02:22:48 PM PST 24
Peak memory 203840 kb
Host smart-d173610b-d452-4ad7-8769-1ca8ec4dc520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294095860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.2294095860
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2999588969
Short name T1116
Test name
Test status
Simulation time 1616990733 ps
CPU time 42.9 seconds
Started Feb 07 02:22:46 PM PST 24
Finished Feb 07 02:23:30 PM PST 24
Peak memory 203624 kb
Host smart-7ab5ff37-fa7a-4bc6-89c6-d2351f2e9339
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999588969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2999588969
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.1210555776
Short name T690
Test name
Test status
Simulation time 50569290608 ps
CPU time 253.39 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 02:27:07 PM PST 24
Peak memory 1449572 kb
Host smart-54dd94bc-9d8a-483b-91f5-1f81f070aa53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210555776 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.1210555776
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1850512431
Short name T927
Test name
Test status
Simulation time 6662056727 ps
CPU time 65.09 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:24:01 PM PST 24
Peak memory 203736 kb
Host smart-c9172e0b-4e52-4ab4-a3d9-b2896537bd6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850512431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1850512431
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2724511110
Short name T1030
Test name
Test status
Simulation time 30255263611 ps
CPU time 1066.27 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:40:42 PM PST 24
Peak memory 6711828 kb
Host smart-24df1012-3dfb-4c58-883e-9e21e3388894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724511110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2724511110
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1395602089
Short name T797
Test name
Test status
Simulation time 22166511539 ps
CPU time 975.01 seconds
Started Feb 07 02:22:52 PM PST 24
Finished Feb 07 02:39:08 PM PST 24
Peak memory 2137268 kb
Host smart-ca2a6d19-5daf-405f-8696-f57f6d47cbc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395602089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1395602089
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.6024196
Short name T877
Test name
Test status
Simulation time 3146318047 ps
CPU time 6.4 seconds
Started Feb 07 02:22:45 PM PST 24
Finished Feb 07 02:22:52 PM PST 24
Peak memory 203776 kb
Host smart-2b88ba5f-ae0f-4967-9a92-ee87e53d1e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6024196 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_timeout.6024196
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_ovf.1698244459
Short name T212
Test name
Test status
Simulation time 2721154008 ps
CPU time 105.52 seconds
Started Feb 07 02:22:43 PM PST 24
Finished Feb 07 02:24:30 PM PST 24
Peak memory 361536 kb
Host smart-5507f87d-f706-44c8-a179-92ba3329b63b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698244459 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_tx_ovf.1698244459
Directory /workspace/22.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.3019069896
Short name T390
Test name
Test status
Simulation time 5562114276 ps
CPU time 6.3 seconds
Started Feb 07 02:22:42 PM PST 24
Finished Feb 07 02:22:49 PM PST 24
Peak memory 203716 kb
Host smart-57d4aadd-95ed-4c07-b9cb-71bcc8a68fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019069896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.3019069896
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2716973281
Short name T508
Test name
Test status
Simulation time 38904488 ps
CPU time 0.6 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:23:07 PM PST 24
Peak memory 202388 kb
Host smart-6319fc52-dc1e-4e4a-8775-6883c35af0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716973281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2716973281
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2931236102
Short name T526
Test name
Test status
Simulation time 51127676 ps
CPU time 1.47 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:22:58 PM PST 24
Peak memory 211812 kb
Host smart-592e07f4-19bb-458d-abb4-d1c4a98296a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931236102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2931236102
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1806944616
Short name T836
Test name
Test status
Simulation time 672174116 ps
CPU time 12.65 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:23:08 PM PST 24
Peak memory 352536 kb
Host smart-1e738160-f771-4974-82a9-5c9946f2f03a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806944616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1806944616
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3297779924
Short name T1363
Test name
Test status
Simulation time 2500980183 ps
CPU time 201.03 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:26:18 PM PST 24
Peak memory 824440 kb
Host smart-a76973fa-989a-4c8e-ab3f-1b7c70516500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297779924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3297779924
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1561435308
Short name T1206
Test name
Test status
Simulation time 28321783622 ps
CPU time 556.62 seconds
Started Feb 07 02:22:54 PM PST 24
Finished Feb 07 02:32:12 PM PST 24
Peak memory 1959392 kb
Host smart-2e5b7c4c-8872-4f57-a36d-8330c6fb1dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561435308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1561435308
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1728451207
Short name T865
Test name
Test status
Simulation time 448738813 ps
CPU time 1.04 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 02:22:55 PM PST 24
Peak memory 203680 kb
Host smart-9cfde18f-b2ae-47ca-8d3b-3160d0c25c53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728451207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1728451207
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.969928147
Short name T1051
Test name
Test status
Simulation time 846584979 ps
CPU time 5.23 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:10 PM PST 24
Peak memory 203652 kb
Host smart-31dfd1d7-593b-445c-a853-4bd8763c7d4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969928147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
969928147
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2682606498
Short name T1008
Test name
Test status
Simulation time 6378168481 ps
CPU time 186.31 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:26:03 PM PST 24
Peak memory 1160244 kb
Host smart-490c6787-0494-46b2-86ff-a9ea014c1e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682606498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2682606498
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1322731923
Short name T1426
Test name
Test status
Simulation time 15763266197 ps
CPU time 132.07 seconds
Started Feb 07 02:23:07 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 252660 kb
Host smart-1772fd67-4895-489a-9644-9f48e3901f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322731923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1322731923
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2788273844
Short name T629
Test name
Test status
Simulation time 58476793 ps
CPU time 0.62 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:22:57 PM PST 24
Peak memory 202592 kb
Host smart-faf4a367-3dc9-439e-ab72-a2f1ae9eb50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788273844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2788273844
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.556574885
Short name T1365
Test name
Test status
Simulation time 49097052414 ps
CPU time 3207.24 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 03:16:21 PM PST 24
Peak memory 489980 kb
Host smart-53e924d4-f20e-40ea-bd15-419bfa93c931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556574885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.556574885
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.1752478635
Short name T1382
Test name
Test status
Simulation time 3331319813 ps
CPU time 170.17 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:25:46 PM PST 24
Peak memory 405020 kb
Host smart-18d2f279-3e00-452d-9d63-c66cdd41345f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752478635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample
.1752478635
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.4007029423
Short name T1253
Test name
Test status
Simulation time 4829225315 ps
CPU time 42.51 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 02:23:37 PM PST 24
Peak memory 277012 kb
Host smart-bda6a0a5-911d-4777-af22-59600c4532c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007029423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.4007029423
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2269746219
Short name T681
Test name
Test status
Simulation time 670741742 ps
CPU time 12.34 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:23:08 PM PST 24
Peak memory 212972 kb
Host smart-456fa051-51fc-425e-a76b-cae041d0c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269746219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2269746219
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3253536996
Short name T1133
Test name
Test status
Simulation time 15172686878 ps
CPU time 5.24 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:11 PM PST 24
Peak memory 204020 kb
Host smart-9fa13ae2-21be-48f9-a4b2-726eebaf87e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253536996 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3253536996
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.381386282
Short name T1367
Test name
Test status
Simulation time 10047141731 ps
CPU time 57.93 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 02:23:52 PM PST 24
Peak memory 502252 kb
Host smart-16f3195b-59ca-4ca3-9ca2-9f67029d466d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381386282 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.381386282
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3995904724
Short name T437
Test name
Test status
Simulation time 10435624988 ps
CPU time 13.82 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:23:10 PM PST 24
Peak memory 313396 kb
Host smart-9cbf82ae-ff57-44d4-8102-bcd001ba57b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995904724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3995904724
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3937472428
Short name T665
Test name
Test status
Simulation time 788248204 ps
CPU time 2.05 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:08 PM PST 24
Peak memory 203496 kb
Host smart-4388c57d-0d8e-4ccf-bb80-994275efacab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937472428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3937472428
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2366548953
Short name T289
Test name
Test status
Simulation time 3104834780 ps
CPU time 6.49 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:23:04 PM PST 24
Peak memory 210564 kb
Host smart-08937dba-da52-422c-aa88-bfe27df5e633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366548953 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2366548953
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3105588677
Short name T1138
Test name
Test status
Simulation time 12396667194 ps
CPU time 271 seconds
Started Feb 07 02:22:53 PM PST 24
Finished Feb 07 02:27:25 PM PST 24
Peak memory 2745824 kb
Host smart-ca0a5be5-b3c2-4e8f-b5ac-683b4a7d6501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105588677 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3105588677
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.2349216837
Short name T533
Test name
Test status
Simulation time 778001646 ps
CPU time 4.52 seconds
Started Feb 07 02:23:04 PM PST 24
Finished Feb 07 02:23:09 PM PST 24
Peak memory 205400 kb
Host smart-78186718-ea45-42f0-a7d6-2a4d5cda1b59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349216837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.2349216837
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3382255717
Short name T1218
Test name
Test status
Simulation time 865747470 ps
CPU time 23.5 seconds
Started Feb 07 02:22:52 PM PST 24
Finished Feb 07 02:23:17 PM PST 24
Peak memory 203628 kb
Host smart-8410206a-a299-425a-8959-a72966e39a2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382255717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3382255717
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.2442108928
Short name T477
Test name
Test status
Simulation time 31485935283 ps
CPU time 752.21 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:35:29 PM PST 24
Peak memory 856220 kb
Host smart-ec50fbb7-1343-4d63-9b4e-1f3144aa5c96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442108928 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.2442108928
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.252184135
Short name T470
Test name
Test status
Simulation time 3910726192 ps
CPU time 27.1 seconds
Started Feb 07 02:22:55 PM PST 24
Finished Feb 07 02:23:23 PM PST 24
Peak memory 203724 kb
Host smart-a98a7a2c-3193-414e-bc61-44d77cf7cd7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252184135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_rd.252184135
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2975551585
Short name T1156
Test name
Test status
Simulation time 57200016816 ps
CPU time 1330.67 seconds
Started Feb 07 02:22:56 PM PST 24
Finished Feb 07 02:45:07 PM PST 24
Peak memory 6879492 kb
Host smart-9abbbb82-0160-40df-83a0-64ec5311f8dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975551585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2975551585
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2987222648
Short name T248
Test name
Test status
Simulation time 24544539539 ps
CPU time 1081.46 seconds
Started Feb 07 02:23:21 PM PST 24
Finished Feb 07 02:41:24 PM PST 24
Peak memory 2354976 kb
Host smart-b9d8aa25-4701-4906-bcba-90c038e47014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987222648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2987222648
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2205579130
Short name T746
Test name
Test status
Simulation time 4440745854 ps
CPU time 7.46 seconds
Started Feb 07 02:22:58 PM PST 24
Finished Feb 07 02:23:06 PM PST 24
Peak memory 210876 kb
Host smart-4f1c97c1-8d6b-48dc-998d-6241628e6b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205579130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2205579130
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_ovf.2263071959
Short name T1432
Test name
Test status
Simulation time 3784546771 ps
CPU time 30.89 seconds
Started Feb 07 02:22:54 PM PST 24
Finished Feb 07 02:23:26 PM PST 24
Peak memory 219124 kb
Host smart-fc826596-a819-411d-ba8a-248d0831db28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263071959 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_tx_ovf.2263071959
Directory /workspace/23.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.918074809
Short name T1017
Test name
Test status
Simulation time 922317993 ps
CPU time 5.35 seconds
Started Feb 07 02:22:54 PM PST 24
Finished Feb 07 02:23:00 PM PST 24
Peak memory 203648 kb
Host smart-38687c6f-5e1e-4fdb-9e12-8c730e9123d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918074809 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_unexp_stop.918074809
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3368041971
Short name T1395
Test name
Test status
Simulation time 43851924 ps
CPU time 0.61 seconds
Started Feb 07 02:23:21 PM PST 24
Finished Feb 07 02:23:24 PM PST 24
Peak memory 202392 kb
Host smart-6fa0c42e-2d33-458d-9760-404eb3113ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368041971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3368041971
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2963994964
Short name T220
Test name
Test status
Simulation time 51910930 ps
CPU time 1.41 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:07 PM PST 24
Peak memory 211908 kb
Host smart-fbc6aeee-7170-4096-bdb8-b4b071132da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963994964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2963994964
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3701757492
Short name T724
Test name
Test status
Simulation time 518277924 ps
CPU time 9.14 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:15 PM PST 24
Peak memory 283952 kb
Host smart-274c9e1e-3244-4b41-900c-7ccdc52337de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701757492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3701757492
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.3070524620
Short name T745
Test name
Test status
Simulation time 2586311654 ps
CPU time 104.52 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:24:52 PM PST 24
Peak memory 848028 kb
Host smart-aedd6fdc-e650-4249-b28c-d5fd26a36b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070524620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.3070524620
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2050306082
Short name T1130
Test name
Test status
Simulation time 10706072249 ps
CPU time 644.57 seconds
Started Feb 07 02:22:57 PM PST 24
Finished Feb 07 02:33:42 PM PST 24
Peak memory 1499988 kb
Host smart-45aedbee-2758-4857-9691-bff58afdf841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050306082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2050306082
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1594868531
Short name T1000
Test name
Test status
Simulation time 194237887 ps
CPU time 1.15 seconds
Started Feb 07 02:23:01 PM PST 24
Finished Feb 07 02:23:03 PM PST 24
Peak memory 203644 kb
Host smart-12f2aa83-4170-478b-ad43-b82c749c13da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594868531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1594868531
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.853322389
Short name T1025
Test name
Test status
Simulation time 151590245 ps
CPU time 4.06 seconds
Started Feb 07 02:23:02 PM PST 24
Finished Feb 07 02:23:06 PM PST 24
Peak memory 229220 kb
Host smart-f2055b1c-75a0-41b0-8634-826f87f45589
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853322389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
853322389
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.181956212
Short name T863
Test name
Test status
Simulation time 42155123333 ps
CPU time 434.22 seconds
Started Feb 07 02:23:03 PM PST 24
Finished Feb 07 02:30:18 PM PST 24
Peak memory 1886656 kb
Host smart-cd96afe3-b2fc-4a28-a17d-a1d41fc75040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181956212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.181956212
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.392582266
Short name T1455
Test name
Test status
Simulation time 2304851354 ps
CPU time 154.56 seconds
Started Feb 07 02:23:10 PM PST 24
Finished Feb 07 02:25:46 PM PST 24
Peak memory 324312 kb
Host smart-93b94fd6-3c02-4cba-8b12-5f7cc19c369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392582266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.392582266
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1694627811
Short name T895
Test name
Test status
Simulation time 31576444 ps
CPU time 0.63 seconds
Started Feb 07 02:23:01 PM PST 24
Finished Feb 07 02:23:03 PM PST 24
Peak memory 202616 kb
Host smart-fe6f4cfc-a836-4c23-8ea7-68136da44765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694627811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1694627811
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3047167509
Short name T449
Test name
Test status
Simulation time 19064787581 ps
CPU time 159.66 seconds
Started Feb 07 02:23:04 PM PST 24
Finished Feb 07 02:25:44 PM PST 24
Peak memory 316220 kb
Host smart-66438fef-15ee-45de-a0c7-00bb8b24cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047167509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3047167509
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.2154723879
Short name T185
Test name
Test status
Simulation time 8120972014 ps
CPU time 95.58 seconds
Started Feb 07 02:22:57 PM PST 24
Finished Feb 07 02:24:34 PM PST 24
Peak memory 252072 kb
Host smart-87ccd401-1531-4dbf-aada-dcf0a7511b3f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154723879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample
.2154723879
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3081806882
Short name T1315
Test name
Test status
Simulation time 1599834745 ps
CPU time 77.98 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:24:25 PM PST 24
Peak memory 227740 kb
Host smart-278364e1-eed7-4e5a-a963-25e296fb3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081806882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3081806882
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.4083974368
Short name T1237
Test name
Test status
Simulation time 41093106390 ps
CPU time 1084.39 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:41:12 PM PST 24
Peak memory 1535496 kb
Host smart-be428286-0883-494c-a941-9f0577598a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083974368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4083974368
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2162569650
Short name T329
Test name
Test status
Simulation time 535116389 ps
CPU time 22.06 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:28 PM PST 24
Peak memory 211508 kb
Host smart-ef064f88-0c19-4c57-9562-9042539ea965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162569650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2162569650
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2789165557
Short name T1056
Test name
Test status
Simulation time 5181583970 ps
CPU time 4.91 seconds
Started Feb 07 02:23:08 PM PST 24
Finished Feb 07 02:23:13 PM PST 24
Peak memory 203648 kb
Host smart-d9282a30-404b-418c-9723-b462d57cc1b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789165557 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2789165557
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1813476457
Short name T1164
Test name
Test status
Simulation time 10620592034 ps
CPU time 7.64 seconds
Started Feb 07 02:23:05 PM PST 24
Finished Feb 07 02:23:14 PM PST 24
Peak memory 243404 kb
Host smart-8dbaf95a-dd7e-4d77-a9ac-b0fcb9bb6156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813476457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1813476457
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1988051424
Short name T574
Test name
Test status
Simulation time 10075718971 ps
CPU time 59.43 seconds
Started Feb 07 02:23:10 PM PST 24
Finished Feb 07 02:24:11 PM PST 24
Peak memory 529420 kb
Host smart-b4a2ed36-06d9-4fcf-b4f5-0ea29901d3b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988051424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1988051424
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.405342566
Short name T960
Test name
Test status
Simulation time 5260698745 ps
CPU time 1.95 seconds
Started Feb 07 02:23:10 PM PST 24
Finished Feb 07 02:23:13 PM PST 24
Peak memory 203720 kb
Host smart-5f080cd5-6fb7-4ba7-9534-713b0d99d264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405342566 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.405342566
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3831568232
Short name T488
Test name
Test status
Simulation time 3913073560 ps
CPU time 8.17 seconds
Started Feb 07 02:23:10 PM PST 24
Finished Feb 07 02:23:19 PM PST 24
Peak memory 210184 kb
Host smart-73915c13-1bde-42bd-b042-af0311fc5692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831568232 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3831568232
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1169651806
Short name T1436
Test name
Test status
Simulation time 23739458165 ps
CPU time 898.17 seconds
Started Feb 07 02:23:12 PM PST 24
Finished Feb 07 02:38:11 PM PST 24
Peak memory 5197364 kb
Host smart-cf60efe2-269d-4983-985a-2d659b7bd2f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169651806 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1169651806
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.2195222616
Short name T1059
Test name
Test status
Simulation time 654867692 ps
CPU time 3.84 seconds
Started Feb 07 02:23:07 PM PST 24
Finished Feb 07 02:23:12 PM PST 24
Peak memory 203616 kb
Host smart-dd613070-dc7a-4f02-a131-7f1ce18f65d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195222616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.2195222616
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1583796843
Short name T1488
Test name
Test status
Simulation time 3385600229 ps
CPU time 11.03 seconds
Started Feb 07 02:22:58 PM PST 24
Finished Feb 07 02:23:09 PM PST 24
Peak memory 203740 kb
Host smart-a3da643c-4880-4833-b185-03b90e06b8d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583796843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1583796843
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.2910164855
Short name T815
Test name
Test status
Simulation time 17554569197 ps
CPU time 30.96 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:23:38 PM PST 24
Peak memory 220124 kb
Host smart-64d5bcd0-8d4f-4937-9590-b396aa5d5c06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910164855 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.2910164855
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.693150931
Short name T432
Test name
Test status
Simulation time 2512328650 ps
CPU time 34.46 seconds
Started Feb 07 02:23:12 PM PST 24
Finished Feb 07 02:23:47 PM PST 24
Peak memory 233500 kb
Host smart-384795fb-6eec-44d0-8e46-8149ddf9a30b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693150931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.693150931
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1651448724
Short name T867
Test name
Test status
Simulation time 14611142021 ps
CPU time 197.02 seconds
Started Feb 07 02:23:10 PM PST 24
Finished Feb 07 02:26:28 PM PST 24
Peak memory 2608260 kb
Host smart-e57e5ab8-d196-47df-bd93-eccafde7d481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651448724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1651448724
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2220664025
Short name T874
Test name
Test status
Simulation time 5794665804 ps
CPU time 388.32 seconds
Started Feb 07 02:23:06 PM PST 24
Finished Feb 07 02:29:35 PM PST 24
Peak memory 1372356 kb
Host smart-d4df5a15-1d41-4e07-a1d8-393b5437ae92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220664025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2220664025
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.438124738
Short name T956
Test name
Test status
Simulation time 1805621250 ps
CPU time 7.42 seconds
Started Feb 07 02:23:07 PM PST 24
Finished Feb 07 02:23:15 PM PST 24
Peak memory 203684 kb
Host smart-86f42163-fe04-492d-bf39-b9e45b766110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438124738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.438124738
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_ovf.887641300
Short name T775
Test name
Test status
Simulation time 10203934955 ps
CPU time 108.93 seconds
Started Feb 07 02:23:08 PM PST 24
Finished Feb 07 02:24:57 PM PST 24
Peak memory 349924 kb
Host smart-d881da20-8711-426f-8682-d379d9cd7918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887641300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_tx_ovf.887641300
Directory /workspace/24.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1591012091
Short name T349
Test name
Test status
Simulation time 20323070 ps
CPU time 0.61 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:23:41 PM PST 24
Peak memory 203280 kb
Host smart-fb6c99e6-8120-4618-aed9-d670417458c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591012091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1591012091
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1740016600
Short name T1072
Test name
Test status
Simulation time 229098028 ps
CPU time 1.39 seconds
Started Feb 07 02:23:17 PM PST 24
Finished Feb 07 02:23:21 PM PST 24
Peak memory 211828 kb
Host smart-fbd96fc2-0041-48d5-8164-6e7b573b3f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740016600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1740016600
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2887892666
Short name T1393
Test name
Test status
Simulation time 265940302 ps
CPU time 5.53 seconds
Started Feb 07 02:23:21 PM PST 24
Finished Feb 07 02:23:27 PM PST 24
Peak memory 258384 kb
Host smart-faf8e5d7-b646-4f8b-9819-41c6a287b539
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887892666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2887892666
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3706754585
Short name T1079
Test name
Test status
Simulation time 12899151335 ps
CPU time 295.29 seconds
Started Feb 07 02:23:16 PM PST 24
Finished Feb 07 02:28:15 PM PST 24
Peak memory 1005828 kb
Host smart-924727f9-73a5-45dd-9dbf-feed56ee7d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706754585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3706754585
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1898521973
Short name T1371
Test name
Test status
Simulation time 8104795697 ps
CPU time 178.99 seconds
Started Feb 07 02:23:17 PM PST 24
Finished Feb 07 02:26:18 PM PST 24
Peak memory 1031588 kb
Host smart-855651c9-ff66-4357-8b8d-5a8c52560000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898521973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1898521973
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.4218606345
Short name T967
Test name
Test status
Simulation time 1241225319 ps
CPU time 1.14 seconds
Started Feb 07 02:23:22 PM PST 24
Finished Feb 07 02:23:25 PM PST 24
Peak memory 203604 kb
Host smart-b6d9e270-fc62-4f02-868e-ed37907ba7ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218606345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.4218606345
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2480940709
Short name T286
Test name
Test status
Simulation time 346032901 ps
CPU time 10.96 seconds
Started Feb 07 02:23:21 PM PST 24
Finished Feb 07 02:23:32 PM PST 24
Peak memory 203572 kb
Host smart-d0224114-a5d5-434b-ba7a-a7ea3c2a2a73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480940709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2480940709
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1796675498
Short name T894
Test name
Test status
Simulation time 6483271831 ps
CPU time 334.28 seconds
Started Feb 07 02:23:15 PM PST 24
Finished Feb 07 02:28:53 PM PST 24
Peak memory 1787932 kb
Host smart-c93f6240-0b43-4d40-82d3-db25d7617cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796675498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1796675498
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2408895246
Short name T618
Test name
Test status
Simulation time 1744224870 ps
CPU time 97.4 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:25:17 PM PST 24
Peak memory 236212 kb
Host smart-d6711654-c622-474d-bc98-6f39a88dc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408895246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2408895246
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2228244384
Short name T1114
Test name
Test status
Simulation time 51034785 ps
CPU time 0.62 seconds
Started Feb 07 02:23:19 PM PST 24
Finished Feb 07 02:23:21 PM PST 24
Peak memory 202568 kb
Host smart-7db5a211-f4d5-42ea-ada9-00d9221f27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228244384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2228244384
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.2102746365
Short name T771
Test name
Test status
Simulation time 6492752686 ps
CPU time 126.01 seconds
Started Feb 07 02:23:21 PM PST 24
Finished Feb 07 02:25:27 PM PST 24
Peak memory 346264 kb
Host smart-5941e076-6978-4903-b50a-24a58c2b0043
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102746365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample
.2102746365
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.142365736
Short name T1319
Test name
Test status
Simulation time 6229555478 ps
CPU time 62.94 seconds
Started Feb 07 02:23:21 PM PST 24
Finished Feb 07 02:24:25 PM PST 24
Peak memory 300572 kb
Host smart-2bbfe746-a85a-43fe-81e8-88a9e54a23a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142365736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.142365736
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2303991458
Short name T1028
Test name
Test status
Simulation time 9268565860 ps
CPU time 10.95 seconds
Started Feb 07 02:23:16 PM PST 24
Finished Feb 07 02:23:30 PM PST 24
Peak memory 211884 kb
Host smart-4c46158c-ba41-4a1e-a01c-5c5cac23691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303991458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2303991458
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1225261613
Short name T855
Test name
Test status
Simulation time 1476719216 ps
CPU time 5.5 seconds
Started Feb 07 02:23:28 PM PST 24
Finished Feb 07 02:23:39 PM PST 24
Peak memory 203628 kb
Host smart-19909187-617a-40e5-9df3-6fa7b588672b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225261613 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1225261613
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4165934692
Short name T514
Test name
Test status
Simulation time 10064250603 ps
CPU time 61.33 seconds
Started Feb 07 02:23:27 PM PST 24
Finished Feb 07 02:24:32 PM PST 24
Peak memory 502780 kb
Host smart-54344907-0797-428c-92b2-62ccd916d27f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165934692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.4165934692
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1703481506
Short name T217
Test name
Test status
Simulation time 10081264626 ps
CPU time 15.31 seconds
Started Feb 07 02:23:27 PM PST 24
Finished Feb 07 02:23:47 PM PST 24
Peak memory 298244 kb
Host smart-9f8e5f3e-d1be-4b59-ae1b-055d847ea622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703481506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1703481506
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.774602927
Short name T1005
Test name
Test status
Simulation time 1822216479 ps
CPU time 2.19 seconds
Started Feb 07 02:23:29 PM PST 24
Finished Feb 07 02:23:36 PM PST 24
Peak memory 203664 kb
Host smart-616d25a7-bbf7-4f6e-bf67-79af5c18912b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774602927 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.774602927
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.433412114
Short name T731
Test name
Test status
Simulation time 2937910590 ps
CPU time 3.93 seconds
Started Feb 07 02:23:28 PM PST 24
Finished Feb 07 02:23:37 PM PST 24
Peak memory 203652 kb
Host smart-7685632c-4e8f-46bb-b856-15e8e0c8dbe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433412114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.433412114
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2460774506
Short name T781
Test name
Test status
Simulation time 5826507679 ps
CPU time 61.87 seconds
Started Feb 07 02:23:30 PM PST 24
Finished Feb 07 02:24:35 PM PST 24
Peak memory 1164576 kb
Host smart-c2ce726f-47bc-4939-bd79-26cae0e01810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460774506 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2460774506
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.3633264661
Short name T957
Test name
Test status
Simulation time 831532438 ps
CPU time 4.43 seconds
Started Feb 07 02:23:30 PM PST 24
Finished Feb 07 02:23:38 PM PST 24
Peak memory 203608 kb
Host smart-961c6804-06d1-4ab3-ad4e-d3a338105497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633264661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.3633264661
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1467993848
Short name T925
Test name
Test status
Simulation time 3912567210 ps
CPU time 14.17 seconds
Started Feb 07 02:23:16 PM PST 24
Finished Feb 07 02:23:34 PM PST 24
Peak memory 203696 kb
Host smart-27df9c2c-1c64-4bb5-ab8e-c65e5127ef10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467993848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1467993848
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.3675012729
Short name T1316
Test name
Test status
Simulation time 7237086892 ps
CPU time 28.78 seconds
Started Feb 07 02:23:33 PM PST 24
Finished Feb 07 02:24:03 PM PST 24
Peak memory 231208 kb
Host smart-d1668314-8b8c-4689-b5ec-b3c77bc9eceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675012729 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.3675012729
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.221997801
Short name T922
Test name
Test status
Simulation time 1774729667 ps
CPU time 30.01 seconds
Started Feb 07 02:23:17 PM PST 24
Finished Feb 07 02:23:49 PM PST 24
Peak memory 212904 kb
Host smart-375e3c18-77cf-4bcd-993e-c0a13d44b71a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221997801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.221997801
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.211734825
Short name T436
Test name
Test status
Simulation time 17706043028 ps
CPU time 13.17 seconds
Started Feb 07 02:23:15 PM PST 24
Finished Feb 07 02:23:33 PM PST 24
Peak memory 429500 kb
Host smart-4be2714e-d4a3-47a4-8ef5-3193f9700193
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211734825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.211734825
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.789330050
Short name T496
Test name
Test status
Simulation time 7629954701 ps
CPU time 47.84 seconds
Started Feb 07 02:23:15 PM PST 24
Finished Feb 07 02:24:07 PM PST 24
Peak memory 706772 kb
Host smart-52183d29-66d1-4fd2-b6d3-1f30d89010b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789330050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.789330050
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2333578598
Short name T1034
Test name
Test status
Simulation time 1648505935 ps
CPU time 6.71 seconds
Started Feb 07 02:23:28 PM PST 24
Finished Feb 07 02:23:39 PM PST 24
Peak memory 203692 kb
Host smart-480c087e-d3cd-418c-a4c3-84015d627e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333578598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2333578598
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_ovf.386055897
Short name T1358
Test name
Test status
Simulation time 18111948427 ps
CPU time 55.79 seconds
Started Feb 07 02:23:29 PM PST 24
Finished Feb 07 02:24:29 PM PST 24
Peak memory 228184 kb
Host smart-fec7cd6e-0158-4666-841f-3954a2f2f150
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386055897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_tx_ovf.386055897
Directory /workspace/25.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.1048821836
Short name T244
Test name
Test status
Simulation time 789410477 ps
CPU time 4.52 seconds
Started Feb 07 02:23:29 PM PST 24
Finished Feb 07 02:23:38 PM PST 24
Peak memory 205304 kb
Host smart-281fab1c-ca3a-4876-b861-73ec9ee0a41c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048821836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.1048821836
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3431628265
Short name T1516
Test name
Test status
Simulation time 24497934 ps
CPU time 0.62 seconds
Started Feb 07 02:23:48 PM PST 24
Finished Feb 07 02:23:51 PM PST 24
Peak memory 202112 kb
Host smart-4b7c9dab-bdad-47e0-9822-ce21bfd27abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431628265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3431628265
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.992582582
Short name T163
Test name
Test status
Simulation time 51002641 ps
CPU time 1.54 seconds
Started Feb 07 02:23:40 PM PST 24
Finished Feb 07 02:23:43 PM PST 24
Peak memory 220032 kb
Host smart-69b27f75-4c64-4e35-8f3f-f6909577d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992582582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.992582582
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3214855617
Short name T1511
Test name
Test status
Simulation time 982540436 ps
CPU time 10.69 seconds
Started Feb 07 02:23:38 PM PST 24
Finished Feb 07 02:23:49 PM PST 24
Peak memory 300792 kb
Host smart-0dba0006-6faf-4531-b0bd-35be76660bc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214855617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3214855617
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2826269891
Short name T425
Test name
Test status
Simulation time 8492606489 ps
CPU time 82.53 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:25:03 PM PST 24
Peak memory 733340 kb
Host smart-da601ee3-7c9e-4c71-af30-87368fb35726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826269891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2826269891
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1003297964
Short name T1335
Test name
Test status
Simulation time 19365316928 ps
CPU time 280.71 seconds
Started Feb 07 02:23:46 PM PST 24
Finished Feb 07 02:28:31 PM PST 24
Peak memory 1322072 kb
Host smart-1aadb18a-cb1d-4443-b7f9-44b2548b0a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003297964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1003297964
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3847226641
Short name T913
Test name
Test status
Simulation time 328588450 ps
CPU time 1.07 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:23:41 PM PST 24
Peak memory 203692 kb
Host smart-c2836fdd-6ec1-40e5-a5b4-0de30e1dbd68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847226641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3847226641
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1585775970
Short name T407
Test name
Test status
Simulation time 2651057528 ps
CPU time 12.52 seconds
Started Feb 07 02:23:42 PM PST 24
Finished Feb 07 02:23:56 PM PST 24
Peak memory 203780 kb
Host smart-57be9bba-0afe-4b3f-88c5-ad698152d9bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585775970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1585775970
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1545963147
Short name T1369
Test name
Test status
Simulation time 11944153938 ps
CPU time 614.37 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:33:54 PM PST 24
Peak memory 1566236 kb
Host smart-9a4b4c8b-2fc1-4be3-a0a5-b52a1341dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545963147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1545963147
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3545198616
Short name T911
Test name
Test status
Simulation time 3160653150 ps
CPU time 33.17 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:24:24 PM PST 24
Peak memory 232736 kb
Host smart-a0e7446c-173d-4ce0-ad8a-c53db5bbda3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545198616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3545198616
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1470660254
Short name T649
Test name
Test status
Simulation time 31707005 ps
CPU time 0.62 seconds
Started Feb 07 02:23:38 PM PST 24
Finished Feb 07 02:23:40 PM PST 24
Peak memory 202584 kb
Host smart-d2d1e2bb-c4c1-4094-a982-805f4a29a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470660254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1470660254
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3331174388
Short name T1338
Test name
Test status
Simulation time 7175962120 ps
CPU time 27.26 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:24:07 PM PST 24
Peak memory 220148 kb
Host smart-477cd5ff-d816-4d4e-b59b-55e166015d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331174388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3331174388
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.1856517906
Short name T1494
Test name
Test status
Simulation time 3405549638 ps
CPU time 116.26 seconds
Started Feb 07 02:23:44 PM PST 24
Finished Feb 07 02:25:45 PM PST 24
Peak memory 321196 kb
Host smart-ebccf7a3-e1eb-42b7-a67d-46e18619b003
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856517906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample
.1856517906
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.2750663805
Short name T275
Test name
Test status
Simulation time 9055272189 ps
CPU time 52.73 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:24:43 PM PST 24
Peak memory 291284 kb
Host smart-99b148fa-710d-4826-ad5d-853752475521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750663805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2750663805
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2587367943
Short name T929
Test name
Test status
Simulation time 706530387 ps
CPU time 9.86 seconds
Started Feb 07 02:23:41 PM PST 24
Finished Feb 07 02:23:52 PM PST 24
Peak memory 211776 kb
Host smart-6e6f43bc-1639-4876-a5b8-b7e6859a0698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587367943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2587367943
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.694890407
Short name T279
Test name
Test status
Simulation time 4140971407 ps
CPU time 3.73 seconds
Started Feb 07 02:23:50 PM PST 24
Finished Feb 07 02:23:58 PM PST 24
Peak memory 203784 kb
Host smart-e56c649f-d1b4-4f4f-8b8c-afbfa03dce99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694890407 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.694890407
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1901889487
Short name T708
Test name
Test status
Simulation time 10186401488 ps
CPU time 53.18 seconds
Started Feb 07 02:23:48 PM PST 24
Finished Feb 07 02:24:44 PM PST 24
Peak memory 479796 kb
Host smart-b362433e-c910-4715-b65f-be012e44e729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901889487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1901889487
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2996614975
Short name T243
Test name
Test status
Simulation time 10123733873 ps
CPU time 61.14 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:24:52 PM PST 24
Peak memory 551372 kb
Host smart-59aa4f9f-d639-4921-94c1-5df21e69fdc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996614975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2996614975
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3071688555
Short name T1006
Test name
Test status
Simulation time 438358550 ps
CPU time 2.29 seconds
Started Feb 07 02:23:45 PM PST 24
Finished Feb 07 02:23:53 PM PST 24
Peak memory 203576 kb
Host smart-e3dbb9f6-8e08-4580-8073-7b003e46f052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071688555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3071688555
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1262511413
Short name T768
Test name
Test status
Simulation time 2308374786 ps
CPU time 4.78 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:23:55 PM PST 24
Peak memory 203692 kb
Host smart-62fe4742-8ec0-4498-b99a-e06c833c6ccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262511413 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1262511413
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1158488497
Short name T343
Test name
Test status
Simulation time 15341003042 ps
CPU time 76.69 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:25:07 PM PST 24
Peak memory 1036104 kb
Host smart-a30eae3e-15a1-49d1-b38a-9cf0daeb1c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158488497 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1158488497
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.550288444
Short name T1546
Test name
Test status
Simulation time 695680743 ps
CPU time 4.01 seconds
Started Feb 07 02:23:49 PM PST 24
Finished Feb 07 02:23:55 PM PST 24
Peak memory 203332 kb
Host smart-53d0d6e9-dba0-4599-84f5-5f23e5b5dc63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550288444 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_perf.550288444
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1315106185
Short name T1168
Test name
Test status
Simulation time 1233543251 ps
CPU time 15.19 seconds
Started Feb 07 02:23:39 PM PST 24
Finished Feb 07 02:23:55 PM PST 24
Peak memory 203600 kb
Host smart-4e1485dc-5b17-47fc-9452-b532418a627e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315106185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1315106185
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.583850732
Short name T1236
Test name
Test status
Simulation time 1903156072 ps
CPU time 24.54 seconds
Started Feb 07 02:23:41 PM PST 24
Finished Feb 07 02:24:07 PM PST 24
Peak memory 220996 kb
Host smart-4071ee73-e973-4abc-a41b-8d5e2b4c8f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583850732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_rd.583850732
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3492630671
Short name T1086
Test name
Test status
Simulation time 20422645155 ps
CPU time 423.57 seconds
Started Feb 07 02:23:46 PM PST 24
Finished Feb 07 02:30:54 PM PST 24
Peak memory 3934020 kb
Host smart-e88813ca-bfa0-4b5a-a644-d2f26c8c27e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492630671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3492630671
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2108579506
Short name T523
Test name
Test status
Simulation time 1211982977 ps
CPU time 5.49 seconds
Started Feb 07 02:23:44 PM PST 24
Finished Feb 07 02:23:56 PM PST 24
Peak memory 203676 kb
Host smart-ee888c02-68c6-42aa-bb7b-e834cd8a5005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108579506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2108579506
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_ovf.1590503089
Short name T1125
Test name
Test status
Simulation time 2885852858 ps
CPU time 50.36 seconds
Started Feb 07 02:23:45 PM PST 24
Finished Feb 07 02:24:41 PM PST 24
Peak memory 226292 kb
Host smart-7e016f59-9fe5-4e9e-9e19-c35b99db9bee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590503089 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_tx_ovf.1590503089
Directory /workspace/26.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.1727336397
Short name T767
Test name
Test status
Simulation time 4846440297 ps
CPU time 6.9 seconds
Started Feb 07 02:23:49 PM PST 24
Finished Feb 07 02:23:58 PM PST 24
Peak memory 203416 kb
Host smart-16a82f70-dc74-4714-9fcc-9f83404d0704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727336397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.1727336397
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3721536782
Short name T641
Test name
Test status
Simulation time 15080185 ps
CPU time 0.61 seconds
Started Feb 07 02:24:06 PM PST 24
Finished Feb 07 02:24:07 PM PST 24
Peak memory 202360 kb
Host smart-d695ff4f-b110-4206-8d92-9352ae53c95c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721536782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3721536782
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3332975362
Short name T227
Test name
Test status
Simulation time 485260974 ps
CPU time 1.85 seconds
Started Feb 07 02:23:56 PM PST 24
Finished Feb 07 02:23:59 PM PST 24
Peak memory 211888 kb
Host smart-1dd62664-3091-4c96-af5b-7c6f6130e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332975362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3332975362
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2228061516
Short name T1187
Test name
Test status
Simulation time 1080453730 ps
CPU time 8.74 seconds
Started Feb 07 02:23:53 PM PST 24
Finished Feb 07 02:24:04 PM PST 24
Peak memory 287732 kb
Host smart-33189dac-099c-480d-9ba4-0d63fc869ad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228061516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2228061516
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2354875202
Short name T528
Test name
Test status
Simulation time 16865637446 ps
CPU time 125.54 seconds
Started Feb 07 02:23:55 PM PST 24
Finished Feb 07 02:26:02 PM PST 24
Peak memory 962888 kb
Host smart-1a9bd36a-86da-4f95-9a28-0927be641a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354875202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2354875202
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1803260231
Short name T1429
Test name
Test status
Simulation time 3430075865 ps
CPU time 313.99 seconds
Started Feb 07 02:23:45 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 1023660 kb
Host smart-c1b35576-a625-4e96-93fa-aaf049b8c0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803260231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1803260231
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3186496096
Short name T546
Test name
Test status
Simulation time 483145764 ps
CPU time 1 seconds
Started Feb 07 02:23:48 PM PST 24
Finished Feb 07 02:23:52 PM PST 24
Peak memory 203588 kb
Host smart-7b69bc6c-2724-4e29-b764-36dec753412f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186496096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3186496096
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1121310668
Short name T1080
Test name
Test status
Simulation time 138850345 ps
CPU time 4.41 seconds
Started Feb 07 02:23:54 PM PST 24
Finished Feb 07 02:24:00 PM PST 24
Peak memory 226336 kb
Host smart-f3c0a0c3-7da9-4a7c-a52e-91c8d3bf671d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121310668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1121310668
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1306830648
Short name T845
Test name
Test status
Simulation time 31091270684 ps
CPU time 363.02 seconds
Started Feb 07 02:23:45 PM PST 24
Finished Feb 07 02:29:54 PM PST 24
Peak memory 1710904 kb
Host smart-4f2724d7-c521-44f7-8508-b00471726808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306830648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1306830648
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.969650713
Short name T57
Test name
Test status
Simulation time 38668965632 ps
CPU time 126.32 seconds
Started Feb 07 02:24:19 PM PST 24
Finished Feb 07 02:26:26 PM PST 24
Peak memory 244564 kb
Host smart-f2a9a8eb-5d73-4b0a-a0d5-153b6fa1987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969650713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.969650713
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3898197346
Short name T1048
Test name
Test status
Simulation time 23315161 ps
CPU time 0.64 seconds
Started Feb 07 02:23:45 PM PST 24
Finished Feb 07 02:23:51 PM PST 24
Peak memory 202628 kb
Host smart-ffebbbb3-9151-4e70-a688-2c11733c05f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898197346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3898197346
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.744704464
Short name T141
Test name
Test status
Simulation time 3320809741 ps
CPU time 77.83 seconds
Started Feb 07 02:23:57 PM PST 24
Finished Feb 07 02:25:16 PM PST 24
Peak memory 364176 kb
Host smart-00aad811-98f8-4d6d-b3bc-8235932c875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744704464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.744704464
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.1297769998
Short name T1300
Test name
Test status
Simulation time 1720929862 ps
CPU time 55.41 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:24:46 PM PST 24
Peak memory 298920 kb
Host smart-a7ede4da-0cb9-44a9-a4df-4b641356ecd3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297769998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample
.1297769998
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1804615110
Short name T260
Test name
Test status
Simulation time 2517222977 ps
CPU time 135.48 seconds
Started Feb 07 02:23:47 PM PST 24
Finished Feb 07 02:26:06 PM PST 24
Peak memory 253524 kb
Host smart-d2852e95-e12a-495b-b8d7-59dac88091f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804615110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1804615110
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3728925816
Short name T741
Test name
Test status
Simulation time 14822831560 ps
CPU time 2079.18 seconds
Started Feb 07 02:23:58 PM PST 24
Finished Feb 07 02:58:38 PM PST 24
Peak memory 2658792 kb
Host smart-0d89e35d-17a6-4083-8c56-88164b7368e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728925816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3728925816
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2566360312
Short name T769
Test name
Test status
Simulation time 2657208217 ps
CPU time 21.13 seconds
Started Feb 07 02:23:54 PM PST 24
Finished Feb 07 02:24:17 PM PST 24
Peak memory 211980 kb
Host smart-0bf3b8d2-00ad-4a8b-b114-b5d8e7bae9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566360312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2566360312
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.9483382
Short name T752
Test name
Test status
Simulation time 2322397603 ps
CPU time 3.01 seconds
Started Feb 07 02:24:13 PM PST 24
Finished Feb 07 02:24:17 PM PST 24
Peak memory 203728 kb
Host smart-9ea784d4-1fef-4b10-86a7-2dc4e54df2f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9483382 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_bad_addr.9483382
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3807855960
Short name T1525
Test name
Test status
Simulation time 10161748662 ps
CPU time 23.51 seconds
Started Feb 07 02:23:53 PM PST 24
Finished Feb 07 02:24:19 PM PST 24
Peak memory 329392 kb
Host smart-7dec9aeb-4ffa-44a5-8a30-fe523c020c9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807855960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3807855960
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1245141773
Short name T406
Test name
Test status
Simulation time 10099177330 ps
CPU time 65.58 seconds
Started Feb 07 02:23:57 PM PST 24
Finished Feb 07 02:25:04 PM PST 24
Peak memory 596908 kb
Host smart-2ed441e4-fc6f-42aa-9a70-ea32629ed63b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245141773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1245141773
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.630438905
Short name T1541
Test name
Test status
Simulation time 1026444013 ps
CPU time 2.56 seconds
Started Feb 07 02:24:10 PM PST 24
Finished Feb 07 02:24:13 PM PST 24
Peak memory 203636 kb
Host smart-748f82db-a9d7-4839-b0ec-81271b177da3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630438905 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.630438905
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3387805987
Short name T419
Test name
Test status
Simulation time 5235040837 ps
CPU time 5.11 seconds
Started Feb 07 02:23:54 PM PST 24
Finished Feb 07 02:24:00 PM PST 24
Peak memory 203748 kb
Host smart-9bf611b4-ad35-4ae1-bf47-deb43c9708ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387805987 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3387805987
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1817156446
Short name T1038
Test name
Test status
Simulation time 16540440289 ps
CPU time 160.96 seconds
Started Feb 07 02:23:53 PM PST 24
Finished Feb 07 02:26:36 PM PST 24
Peak memory 1866740 kb
Host smart-ab982abb-6a67-4cd2-9f7f-49b448dcabc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817156446 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1817156446
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.2433031175
Short name T1096
Test name
Test status
Simulation time 847779191 ps
CPU time 4.92 seconds
Started Feb 07 02:24:14 PM PST 24
Finished Feb 07 02:24:19 PM PST 24
Peak memory 207904 kb
Host smart-a3a8a5ec-4de6-455c-ae35-0f0b71325f8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433031175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.2433031175
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.4254315921
Short name T356
Test name
Test status
Simulation time 974332312 ps
CPU time 9.52 seconds
Started Feb 07 02:23:58 PM PST 24
Finished Feb 07 02:24:08 PM PST 24
Peak memory 203604 kb
Host smart-80303035-c053-48a8-b899-3283f32e82d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254315921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.4254315921
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.978467331
Short name T1151
Test name
Test status
Simulation time 50293630403 ps
CPU time 1651.99 seconds
Started Feb 07 02:24:13 PM PST 24
Finished Feb 07 02:51:46 PM PST 24
Peak memory 1277264 kb
Host smart-16825d43-a81b-40dd-943f-6465883d5101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978467331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_stress_all.978467331
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.4163733430
Short name T537
Test name
Test status
Simulation time 1908841665 ps
CPU time 7.3 seconds
Started Feb 07 02:23:54 PM PST 24
Finished Feb 07 02:24:03 PM PST 24
Peak memory 203628 kb
Host smart-2e9c1703-c2fc-472a-9f9d-f05991ce5c8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163733430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.4163733430
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1786211843
Short name T703
Test name
Test status
Simulation time 14877091672 ps
CPU time 31.34 seconds
Started Feb 07 02:23:55 PM PST 24
Finished Feb 07 02:24:28 PM PST 24
Peak memory 772216 kb
Host smart-f02cab6c-04f5-42af-a3dc-79e465639f1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786211843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1786211843
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.1057728296
Short name T844
Test name
Test status
Simulation time 18659606693 ps
CPU time 349.45 seconds
Started Feb 07 02:23:52 PM PST 24
Finished Feb 07 02:29:44 PM PST 24
Peak memory 2222012 kb
Host smart-1fa8485f-271c-4951-af86-461f7fd97cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057728296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.1057728296
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.4280673276
Short name T375
Test name
Test status
Simulation time 7844072275 ps
CPU time 8.27 seconds
Started Feb 07 02:23:55 PM PST 24
Finished Feb 07 02:24:05 PM PST 24
Peak memory 209464 kb
Host smart-2749b189-b94c-43d1-812f-51cd5290b888
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280673276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.4280673276
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_ovf.426472614
Short name T1400
Test name
Test status
Simulation time 37868613145 ps
CPU time 29.98 seconds
Started Feb 07 02:23:57 PM PST 24
Finished Feb 07 02:24:29 PM PST 24
Peak memory 218440 kb
Host smart-c22339c6-f728-48d8-b92e-4ddbe0233dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426472614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_tx_ovf.426472614
Directory /workspace/27.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.1511552066
Short name T1169
Test name
Test status
Simulation time 1006640202 ps
CPU time 5.01 seconds
Started Feb 07 02:23:54 PM PST 24
Finished Feb 07 02:24:01 PM PST 24
Peak memory 203640 kb
Host smart-f75ec1e4-76e1-45bc-aa8a-5ca0ff6071f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511552066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.1511552066
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2130403942
Short name T1430
Test name
Test status
Simulation time 18702264 ps
CPU time 0.61 seconds
Started Feb 07 02:24:21 PM PST 24
Finished Feb 07 02:24:22 PM PST 24
Peak memory 202408 kb
Host smart-ce1ab556-a8ca-4f1d-8ded-d03b43fff6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130403942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2130403942
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1929007075
Short name T1302
Test name
Test status
Simulation time 172254145 ps
CPU time 1.51 seconds
Started Feb 07 02:24:11 PM PST 24
Finished Feb 07 02:24:14 PM PST 24
Peak memory 211804 kb
Host smart-0c1e48fe-1fad-4e2f-9dab-dc7afafcfa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929007075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1929007075
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3995149295
Short name T705
Test name
Test status
Simulation time 867690034 ps
CPU time 7.34 seconds
Started Feb 07 02:24:06 PM PST 24
Finished Feb 07 02:24:14 PM PST 24
Peak memory 270920 kb
Host smart-3ddbd335-eb57-431f-a088-6aa59a119485
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995149295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3995149295
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.487126210
Short name T994
Test name
Test status
Simulation time 3546879080 ps
CPU time 211.65 seconds
Started Feb 07 02:24:09 PM PST 24
Finished Feb 07 02:27:42 PM PST 24
Peak memory 670536 kb
Host smart-ade7a021-f4dd-431e-85a6-4984aa6e5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487126210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.487126210
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.4221810876
Short name T340
Test name
Test status
Simulation time 5079416951 ps
CPU time 695.37 seconds
Started Feb 07 02:24:11 PM PST 24
Finished Feb 07 02:35:47 PM PST 24
Peak memory 1498540 kb
Host smart-cbc0896f-f798-433e-b25d-3dffef8aece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221810876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4221810876
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1240178405
Short name T651
Test name
Test status
Simulation time 507140244 ps
CPU time 0.91 seconds
Started Feb 07 02:24:06 PM PST 24
Finished Feb 07 02:24:08 PM PST 24
Peak memory 203420 kb
Host smart-fb5820ea-57eb-4b40-a8f2-4f0904728164
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240178405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1240178405
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4038947622
Short name T147
Test name
Test status
Simulation time 220914427 ps
CPU time 6.56 seconds
Started Feb 07 02:24:09 PM PST 24
Finished Feb 07 02:24:17 PM PST 24
Peak memory 247160 kb
Host smart-63a561f6-4c1f-4978-9eeb-e83ca58eb23d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038947622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4038947622
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.90336036
Short name T1023
Test name
Test status
Simulation time 3410243974 ps
CPU time 270.04 seconds
Started Feb 07 02:24:11 PM PST 24
Finished Feb 07 02:28:42 PM PST 24
Peak memory 955368 kb
Host smart-cd1aadb3-b847-4013-b457-d81de8b7a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90336036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.90336036
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2882963606
Short name T333
Test name
Test status
Simulation time 5188704399 ps
CPU time 180.03 seconds
Started Feb 07 02:24:22 PM PST 24
Finished Feb 07 02:27:22 PM PST 24
Peak memory 296300 kb
Host smart-56808b9f-7dca-4efe-85e2-2aa8b586f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882963606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2882963606
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2841714107
Short name T940
Test name
Test status
Simulation time 53111482 ps
CPU time 0.64 seconds
Started Feb 07 02:24:11 PM PST 24
Finished Feb 07 02:24:12 PM PST 24
Peak memory 202568 kb
Host smart-314926ce-fe9d-43b9-9afe-6d254a164f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841714107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2841714107
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1378520626
Short name T1272
Test name
Test status
Simulation time 5242030722 ps
CPU time 175 seconds
Started Feb 07 02:24:12 PM PST 24
Finished Feb 07 02:27:08 PM PST 24
Peak memory 406732 kb
Host smart-89c0e420-4baf-4d73-b9c1-359ea0a05b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378520626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1378520626
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.1190976823
Short name T350
Test name
Test status
Simulation time 5878320661 ps
CPU time 123.87 seconds
Started Feb 07 02:24:09 PM PST 24
Finished Feb 07 02:26:13 PM PST 24
Peak memory 312600 kb
Host smart-48454c39-7aa5-4c6d-9b74-9a8a73bcdc35
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190976823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample
.1190976823
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.692261888
Short name T720
Test name
Test status
Simulation time 5567872473 ps
CPU time 35.6 seconds
Started Feb 07 02:24:06 PM PST 24
Finished Feb 07 02:24:43 PM PST 24
Peak memory 252560 kb
Host smart-0257f0be-2a63-4455-8145-e64108c31b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692261888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.692261888
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2749236936
Short name T1174
Test name
Test status
Simulation time 3070175295 ps
CPU time 10.71 seconds
Started Feb 07 02:24:09 PM PST 24
Finished Feb 07 02:24:21 PM PST 24
Peak memory 212952 kb
Host smart-2e0f4734-353e-49aa-944e-23066591d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749236936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2749236936
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.305668630
Short name T709
Test name
Test status
Simulation time 1103258671 ps
CPU time 4.27 seconds
Started Feb 07 02:24:20 PM PST 24
Finished Feb 07 02:24:25 PM PST 24
Peak memory 203632 kb
Host smart-49c70207-06da-477a-8a2a-df35f6f410ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305668630 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.305668630
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3955488661
Short name T247
Test name
Test status
Simulation time 10796216251 ps
CPU time 7.76 seconds
Started Feb 07 02:24:20 PM PST 24
Finished Feb 07 02:24:28 PM PST 24
Peak memory 256576 kb
Host smart-cfc1d20d-8fcc-44d8-92fe-d97dfeb20243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955488661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3955488661
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1962111669
Short name T750
Test name
Test status
Simulation time 10704066878 ps
CPU time 5.88 seconds
Started Feb 07 02:24:20 PM PST 24
Finished Feb 07 02:24:27 PM PST 24
Peak memory 256568 kb
Host smart-6c7e43d4-8a67-4082-abae-b8c8fb7ecaac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962111669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1962111669
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3676201075
Short name T262
Test name
Test status
Simulation time 1723773876 ps
CPU time 2.22 seconds
Started Feb 07 02:24:21 PM PST 24
Finished Feb 07 02:24:24 PM PST 24
Peak memory 203572 kb
Host smart-a36bcad0-2259-40ed-a606-06041cf11a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676201075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3676201075
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.962957012
Short name T412
Test name
Test status
Simulation time 1576442869 ps
CPU time 6.07 seconds
Started Feb 07 02:24:22 PM PST 24
Finished Feb 07 02:24:29 PM PST 24
Peak memory 203684 kb
Host smart-6ad66d46-cc0d-46bd-9161-98808b0ff570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962957012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.962957012
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.176454676
Short name T232
Test name
Test status
Simulation time 4088114990 ps
CPU time 27.07 seconds
Started Feb 07 02:24:23 PM PST 24
Finished Feb 07 02:24:51 PM PST 24
Peak memory 767196 kb
Host smart-be4282d8-d949-4c44-9e0d-a4cfb82ba175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176454676 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.176454676
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.3831582452
Short name T807
Test name
Test status
Simulation time 1839480077 ps
CPU time 2.76 seconds
Started Feb 07 02:24:23 PM PST 24
Finished Feb 07 02:24:26 PM PST 24
Peak memory 203936 kb
Host smart-d1f8e96e-bf0d-4140-aa30-235743b0aadb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831582452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.3831582452
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3202206189
Short name T502
Test name
Test status
Simulation time 1721727006 ps
CPU time 17.33 seconds
Started Feb 07 02:24:20 PM PST 24
Finished Feb 07 02:24:38 PM PST 24
Peak memory 203620 kb
Host smart-6314b183-457f-4e98-a414-e4a880dc214a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202206189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3202206189
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.543184304
Short name T1121
Test name
Test status
Simulation time 22534437417 ps
CPU time 168.09 seconds
Started Feb 07 02:24:16 PM PST 24
Finished Feb 07 02:27:04 PM PST 24
Peak memory 236964 kb
Host smart-9e1937fc-d68a-4a64-91f7-16ce2584576b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543184304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_stress_all.543184304
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3142284952
Short name T843
Test name
Test status
Simulation time 1767323096 ps
CPU time 26.02 seconds
Started Feb 07 02:24:15 PM PST 24
Finished Feb 07 02:24:42 PM PST 24
Peak memory 225640 kb
Host smart-bf82f182-a374-4048-a454-2ec46a40ea4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142284952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3142284952
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3304844300
Short name T583
Test name
Test status
Simulation time 21802849164 ps
CPU time 54.51 seconds
Started Feb 07 02:24:20 PM PST 24
Finished Feb 07 02:25:16 PM PST 24
Peak memory 1154784 kb
Host smart-c93760d4-b9f6-4e08-bc34-c12037ff12f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304844300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3304844300
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1970299998
Short name T266
Test name
Test status
Simulation time 6941786615 ps
CPU time 31.82 seconds
Started Feb 07 02:24:21 PM PST 24
Finished Feb 07 02:24:54 PM PST 24
Peak memory 497404 kb
Host smart-cb3fa37d-4540-47c0-8aeb-17ec27b3048f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970299998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1970299998
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.775093704
Short name T513
Test name
Test status
Simulation time 2042423402 ps
CPU time 6.78 seconds
Started Feb 07 02:24:23 PM PST 24
Finished Feb 07 02:24:30 PM PST 24
Peak memory 206912 kb
Host smart-6b6933b0-97b9-47a4-97d1-a90f89702c43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775093704 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.775093704
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.1980732367
Short name T199
Test name
Test status
Simulation time 6853257075 ps
CPU time 5.53 seconds
Started Feb 07 02:24:20 PM PST 24
Finished Feb 07 02:24:26 PM PST 24
Peak memory 203716 kb
Host smart-e497b71f-c440-42e3-8a84-04b2f60671c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980732367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.1980732367
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.615937295
Short name T384
Test name
Test status
Simulation time 33055160 ps
CPU time 0.65 seconds
Started Feb 07 02:24:39 PM PST 24
Finished Feb 07 02:24:40 PM PST 24
Peak memory 202112 kb
Host smart-1b579249-a1a5-40bb-ac70-c69ea6996e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615937295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.615937295
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2802111149
Short name T491
Test name
Test status
Simulation time 29806954 ps
CPU time 1.39 seconds
Started Feb 07 02:24:28 PM PST 24
Finished Feb 07 02:24:30 PM PST 24
Peak memory 211780 kb
Host smart-b77fbf06-02ae-4799-a130-962896c34ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802111149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2802111149
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1170021895
Short name T313
Test name
Test status
Simulation time 541264287 ps
CPU time 3.3 seconds
Started Feb 07 02:24:28 PM PST 24
Finished Feb 07 02:24:32 PM PST 24
Peak memory 228284 kb
Host smart-f317ffac-bd12-4bbb-8857-586d7403a8c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170021895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1170021895
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.809134678
Short name T1427
Test name
Test status
Simulation time 2984404739 ps
CPU time 86.1 seconds
Started Feb 07 02:24:28 PM PST 24
Finished Feb 07 02:25:55 PM PST 24
Peak memory 641728 kb
Host smart-90a16741-0148-4df9-8244-d3fb6d10f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809134678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.809134678
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1520789882
Short name T182
Test name
Test status
Simulation time 5418256076 ps
CPU time 687.89 seconds
Started Feb 07 02:24:26 PM PST 24
Finished Feb 07 02:35:55 PM PST 24
Peak memory 1519172 kb
Host smart-9cca5971-8dc9-42bf-b914-b3ef6c8e5aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520789882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1520789882
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1543657341
Short name T706
Test name
Test status
Simulation time 768836291 ps
CPU time 0.91 seconds
Started Feb 07 02:24:25 PM PST 24
Finished Feb 07 02:24:26 PM PST 24
Peak memory 203308 kb
Host smart-b155e399-a11f-433f-a86b-0af569a3f495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543657341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1543657341
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.4216583858
Short name T1542
Test name
Test status
Simulation time 594817080 ps
CPU time 7.89 seconds
Started Feb 07 02:24:24 PM PST 24
Finished Feb 07 02:24:32 PM PST 24
Peak memory 203676 kb
Host smart-64eacc6c-4b13-400f-a9ff-027082906385
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216583858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.4216583858
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3425622755
Short name T702
Test name
Test status
Simulation time 20725062990 ps
CPU time 574.54 seconds
Started Feb 07 02:24:25 PM PST 24
Finished Feb 07 02:34:00 PM PST 24
Peak memory 1542988 kb
Host smart-dd098c6b-6148-4760-854f-7bca4c5fa79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425622755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3425622755
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.403290191
Short name T827
Test name
Test status
Simulation time 2409396512 ps
CPU time 122.21 seconds
Started Feb 07 02:24:38 PM PST 24
Finished Feb 07 02:26:41 PM PST 24
Peak memory 244544 kb
Host smart-8e003cb5-4351-4691-b00c-ecbebaf03070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403290191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.403290191
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_perf.4161962145
Short name T1333
Test name
Test status
Simulation time 760665641 ps
CPU time 32.72 seconds
Started Feb 07 02:24:24 PM PST 24
Finished Feb 07 02:24:58 PM PST 24
Peak memory 220028 kb
Host smart-cde3a728-b96f-4552-9c25-739c8421263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161962145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.4161962145
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.4245157595
Short name T426
Test name
Test status
Simulation time 15284958286 ps
CPU time 157.53 seconds
Started Feb 07 02:24:24 PM PST 24
Finished Feb 07 02:27:02 PM PST 24
Peak memory 397400 kb
Host smart-8c48dc0e-28c4-467b-95d8-6b3892f0d049
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245157595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample
.4245157595
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2890233844
Short name T656
Test name
Test status
Simulation time 5851460261 ps
CPU time 64.55 seconds
Started Feb 07 02:24:25 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 293392 kb
Host smart-9f229d3a-a10f-4e1e-b3ea-ded780559048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890233844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2890233844
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3510568248
Short name T1118
Test name
Test status
Simulation time 16899329329 ps
CPU time 2349.35 seconds
Started Feb 07 02:24:25 PM PST 24
Finished Feb 07 03:03:36 PM PST 24
Peak memory 3221436 kb
Host smart-3ffc7f69-21f3-4009-8af1-479ccdfc55a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510568248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3510568248
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.281250897
Short name T415
Test name
Test status
Simulation time 543043582 ps
CPU time 7.39 seconds
Started Feb 07 02:24:31 PM PST 24
Finished Feb 07 02:24:39 PM PST 24
Peak memory 211780 kb
Host smart-61318699-517b-499a-9d24-6fd42f79508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281250897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.281250897
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.557903470
Short name T1434
Test name
Test status
Simulation time 688503632 ps
CPU time 2.77 seconds
Started Feb 07 02:24:35 PM PST 24
Finished Feb 07 02:24:38 PM PST 24
Peak memory 203664 kb
Host smart-4fb4709d-1245-4ef7-8912-690de061ded9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557903470 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.557903470
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1905837574
Short name T1158
Test name
Test status
Simulation time 11988908273 ps
CPU time 3.43 seconds
Started Feb 07 02:24:36 PM PST 24
Finished Feb 07 02:24:40 PM PST 24
Peak memory 225428 kb
Host smart-1ad3c326-435d-4990-8bd4-16b57dcdda49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905837574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1905837574
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.889538169
Short name T1011
Test name
Test status
Simulation time 10258930616 ps
CPU time 12.85 seconds
Started Feb 07 02:24:36 PM PST 24
Finished Feb 07 02:24:50 PM PST 24
Peak memory 306532 kb
Host smart-d6be0900-3f3c-44cf-86d7-de37b17b36fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889538169 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.889538169
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2679006553
Short name T860
Test name
Test status
Simulation time 1637577553 ps
CPU time 2.2 seconds
Started Feb 07 02:24:35 PM PST 24
Finished Feb 07 02:24:37 PM PST 24
Peak memory 203580 kb
Host smart-99642774-b841-4c90-808a-9416310f297f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679006553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2679006553
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.963338265
Short name T1234
Test name
Test status
Simulation time 4467132656 ps
CPU time 4.57 seconds
Started Feb 07 02:24:40 PM PST 24
Finished Feb 07 02:24:46 PM PST 24
Peak memory 203760 kb
Host smart-d4eab953-f636-4db8-8c29-b625ab0ec3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963338265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.963338265
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1682477638
Short name T376
Test name
Test status
Simulation time 4246480287 ps
CPU time 31.83 seconds
Started Feb 07 02:24:40 PM PST 24
Finished Feb 07 02:25:13 PM PST 24
Peak memory 833768 kb
Host smart-92a5f1f9-3b68-49f3-ae5d-2079a7cae29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682477638 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1682477638
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.3696151969
Short name T721
Test name
Test status
Simulation time 2670364496 ps
CPU time 4.17 seconds
Started Feb 07 02:24:35 PM PST 24
Finished Feb 07 02:24:40 PM PST 24
Peak memory 203708 kb
Host smart-bfb5422b-efa6-4636-998d-fd5cb3e9ce2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696151969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.3696151969
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2378406148
Short name T1018
Test name
Test status
Simulation time 3295551177 ps
CPU time 43.68 seconds
Started Feb 07 02:24:28 PM PST 24
Finished Feb 07 02:25:12 PM PST 24
Peak memory 203680 kb
Host smart-766aa51a-6e36-4d1e-8dc3-88c21ded05fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378406148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2378406148
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.316648148
Short name T1413
Test name
Test status
Simulation time 8655850002 ps
CPU time 117.6 seconds
Started Feb 07 02:24:40 PM PST 24
Finished Feb 07 02:26:38 PM PST 24
Peak memory 418516 kb
Host smart-e133b29e-d731-4e52-9dbd-4df16c3f72a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316648148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_stress_all.316648148
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3540102613
Short name T1304
Test name
Test status
Simulation time 359090850 ps
CPU time 14.5 seconds
Started Feb 07 02:24:27 PM PST 24
Finished Feb 07 02:24:42 PM PST 24
Peak memory 203676 kb
Host smart-4f0c050a-011f-4fc9-a3f5-4fdbcc9a1876
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540102613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3540102613
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3586797137
Short name T615
Test name
Test status
Simulation time 52222200575 ps
CPU time 3390.91 seconds
Started Feb 07 02:24:27 PM PST 24
Finished Feb 07 03:20:59 PM PST 24
Peak memory 12199216 kb
Host smart-adb5132e-44b6-4b61-b4e1-789ad42b1268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586797137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3586797137
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1948661860
Short name T550
Test name
Test status
Simulation time 35442845563 ps
CPU time 265.05 seconds
Started Feb 07 02:24:23 PM PST 24
Finished Feb 07 02:28:48 PM PST 24
Peak memory 1859720 kb
Host smart-75cfce3e-fb4a-49e0-bfcf-21d77b477c73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948661860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1948661860
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3418131938
Short name T1153
Test name
Test status
Simulation time 5803123048 ps
CPU time 5.67 seconds
Started Feb 07 02:24:36 PM PST 24
Finished Feb 07 02:24:42 PM PST 24
Peak memory 208904 kb
Host smart-5d5405c5-4dbc-4308-8468-814b9561d76d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418131938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3418131938
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_ovf.713269151
Short name T989
Test name
Test status
Simulation time 3149770739 ps
CPU time 55.17 seconds
Started Feb 07 02:24:35 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 227612 kb
Host smart-6035203a-01db-4f51-9939-35bbece452de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713269151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_tx_ovf.713269151
Directory /workspace/29.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.599415637
Short name T395
Test name
Test status
Simulation time 7587642570 ps
CPU time 7.05 seconds
Started Feb 07 02:24:37 PM PST 24
Finished Feb 07 02:24:45 PM PST 24
Peak memory 203740 kb
Host smart-c13498bb-6ca4-433a-8e1a-f88bebe4c803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599415637 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_unexp_stop.599415637
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.567729756
Short name T572
Test name
Test status
Simulation time 41885249 ps
CPU time 0.63 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 202396 kb
Host smart-172a3920-ec84-47f4-b894-a132f992cd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567729756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.567729756
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3878650538
Short name T1303
Test name
Test status
Simulation time 102589492 ps
CPU time 1.57 seconds
Started Feb 07 02:18:46 PM PST 24
Finished Feb 07 02:18:49 PM PST 24
Peak memory 220056 kb
Host smart-636643cc-99c6-4a3c-936c-b570e854ca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878650538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3878650538
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2106946724
Short name T328
Test name
Test status
Simulation time 272587362 ps
CPU time 6.93 seconds
Started Feb 07 02:18:46 PM PST 24
Finished Feb 07 02:18:58 PM PST 24
Peak memory 220916 kb
Host smart-cfe56e9c-64ca-48f2-b565-124ae8984fc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106946724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2106946724
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.110776759
Short name T1172
Test name
Test status
Simulation time 13897905831 ps
CPU time 123.1 seconds
Started Feb 07 02:18:45 PM PST 24
Finished Feb 07 02:20:51 PM PST 24
Peak memory 976156 kb
Host smart-12ccfaac-3a38-44f6-ab25-e1814365d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110776759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.110776759
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.384319247
Short name T371
Test name
Test status
Simulation time 14455706204 ps
CPU time 183.68 seconds
Started Feb 07 02:18:45 PM PST 24
Finished Feb 07 02:21:51 PM PST 24
Peak memory 1072904 kb
Host smart-baffd38b-f3dd-4066-8d4d-d3e9741a5cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384319247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.384319247
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2427115548
Short name T361
Test name
Test status
Simulation time 75145289 ps
CPU time 0.81 seconds
Started Feb 07 02:18:50 PM PST 24
Finished Feb 07 02:18:57 PM PST 24
Peak memory 202552 kb
Host smart-9032ab53-69c7-41b5-a69f-8027405b600b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427115548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2427115548
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.875524100
Short name T612
Test name
Test status
Simulation time 2875351594 ps
CPU time 15.26 seconds
Started Feb 07 02:18:42 PM PST 24
Finished Feb 07 02:18:58 PM PST 24
Peak memory 203684 kb
Host smart-cad152c0-5e04-4ffc-a1f5-b06824cf514b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875524100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.875524100
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.870529023
Short name T988
Test name
Test status
Simulation time 22960133250 ps
CPU time 313.86 seconds
Started Feb 07 02:18:48 PM PST 24
Finished Feb 07 02:24:10 PM PST 24
Peak memory 1063872 kb
Host smart-7c177d28-764a-46f1-8d68-d8caa64bea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870529023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.870529023
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.787360331
Short name T856
Test name
Test status
Simulation time 1871555822 ps
CPU time 111.59 seconds
Started Feb 07 02:19:06 PM PST 24
Finished Feb 07 02:20:58 PM PST 24
Peak memory 262016 kb
Host smart-5c16ca64-e423-4807-88c5-38c0e35b4f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787360331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.787360331
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.824532334
Short name T1093
Test name
Test status
Simulation time 58857009 ps
CPU time 0.64 seconds
Started Feb 07 02:18:46 PM PST 24
Finished Feb 07 02:18:48 PM PST 24
Peak memory 202488 kb
Host smart-c97fa576-415b-4761-84c0-7929045ba7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824532334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.824532334
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3742420275
Short name T396
Test name
Test status
Simulation time 52072711166 ps
CPU time 603.57 seconds
Started Feb 07 02:18:46 PM PST 24
Finished Feb 07 02:28:51 PM PST 24
Peak memory 298756 kb
Host smart-a93ac7d6-32e4-4238-a368-4a49f1c82e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742420275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3742420275
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.1503416554
Short name T446
Test name
Test status
Simulation time 2172954682 ps
CPU time 102.04 seconds
Started Feb 07 02:18:45 PM PST 24
Finished Feb 07 02:20:29 PM PST 24
Peak memory 317056 kb
Host smart-e2a49689-1c84-44ad-99b3-80ed7e8705c3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503416554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.
1503416554
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.500773561
Short name T1020
Test name
Test status
Simulation time 2455390101 ps
CPU time 63.1 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:19:48 PM PST 24
Peak memory 296736 kb
Host smart-c5eca7dc-7d00-476a-96bc-589872b0891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500773561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.500773561
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1149334608
Short name T1437
Test name
Test status
Simulation time 1171732448 ps
CPU time 21.51 seconds
Started Feb 07 02:18:44 PM PST 24
Finished Feb 07 02:19:06 PM PST 24
Peak memory 219876 kb
Host smart-3abd0597-9580-418d-9836-ab2acb75a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149334608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1149334608
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3056367636
Short name T72
Test name
Test status
Simulation time 134383519 ps
CPU time 0.82 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 220160 kb
Host smart-8a6ac40c-ced2-4826-8a73-b5844cb6bd25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056367636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3056367636
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.4276795711
Short name T381
Test name
Test status
Simulation time 3259283929 ps
CPU time 4.71 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:19:10 PM PST 24
Peak memory 203712 kb
Host smart-59b963f8-47ea-4c5f-9eb0-32dfea4e5f1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276795711 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.4276795711
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.448806309
Short name T658
Test name
Test status
Simulation time 10101186747 ps
CPU time 33.32 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:19:36 PM PST 24
Peak memory 387708 kb
Host smart-4495f856-3f7d-4880-aa9d-8fba80e3e1c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448806309 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.448806309
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1436473246
Short name T943
Test name
Test status
Simulation time 10423115718 ps
CPU time 9.6 seconds
Started Feb 07 02:19:04 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 262372 kb
Host smart-e10a7f8d-1a5b-4415-b9ca-84b969816508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436473246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1436473246
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.152401946
Short name T510
Test name
Test status
Simulation time 538887149 ps
CPU time 2.78 seconds
Started Feb 07 02:19:08 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 203584 kb
Host smart-adfc667d-e154-4e6b-8e42-dbc74beb1e07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152401946 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.152401946
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3800246962
Short name T1277
Test name
Test status
Simulation time 5056441885 ps
CPU time 5.42 seconds
Started Feb 07 02:19:08 PM PST 24
Finished Feb 07 02:19:17 PM PST 24
Peak memory 203680 kb
Host smart-d80c9d95-ed03-442f-8b7e-b6c69d8219c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800246962 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3800246962
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.469020685
Short name T278
Test name
Test status
Simulation time 8600393469 ps
CPU time 52.86 seconds
Started Feb 07 02:19:04 PM PST 24
Finished Feb 07 02:19:58 PM PST 24
Peak memory 969264 kb
Host smart-a2e176eb-c067-4f86-97af-7b826b6c195b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469020685 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.469020685
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.3438021176
Short name T374
Test name
Test status
Simulation time 598763119 ps
CPU time 3.71 seconds
Started Feb 07 02:19:08 PM PST 24
Finished Feb 07 02:19:13 PM PST 24
Peak memory 203576 kb
Host smart-92820101-a381-4ae3-b5d5-12e568d46e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438021176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.3438021176
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2158763217
Short name T947
Test name
Test status
Simulation time 3245552436 ps
CPU time 10.33 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 203728 kb
Host smart-75f87111-1c0c-40f0-a64d-b4927333a9d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158763217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2158763217
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2058244710
Short name T1084
Test name
Test status
Simulation time 64522393943 ps
CPU time 2497.46 seconds
Started Feb 07 02:19:08 PM PST 24
Finished Feb 07 03:00:47 PM PST 24
Peak memory 4830720 kb
Host smart-f904e5c4-ab66-40cc-b1e0-e92ce5dd87fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058244710 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.2058244710
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2189659288
Short name T1070
Test name
Test status
Simulation time 2835302903 ps
CPU time 23.73 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:19:27 PM PST 24
Peak memory 221596 kb
Host smart-e953aa4b-71ce-418f-af10-b965c0c79f64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189659288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2189659288
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3482117411
Short name T897
Test name
Test status
Simulation time 25179319735 ps
CPU time 77.21 seconds
Started Feb 07 02:19:01 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 1410400 kb
Host smart-fae61269-dcc2-4f4d-96c0-37c5a9698628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482117411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3482117411
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1505985529
Short name T55
Test name
Test status
Simulation time 37786905326 ps
CPU time 861.64 seconds
Started Feb 07 02:19:04 PM PST 24
Finished Feb 07 02:33:27 PM PST 24
Peak memory 2187884 kb
Host smart-5761770d-27fa-4dea-b314-a2b3b5976e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505985529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1505985529
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3121072062
Short name T492
Test name
Test status
Simulation time 15249414772 ps
CPU time 7.65 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:19:13 PM PST 24
Peak memory 210096 kb
Host smart-f1a996f3-dea0-4e46-9088-6df9ea3061e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121072062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3121072062
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_ovf.715000896
Short name T1415
Test name
Test status
Simulation time 11364246502 ps
CPU time 32.13 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:19:46 PM PST 24
Peak memory 214164 kb
Host smart-e49dd42e-5050-4fca-8de4-eb2a882bf535
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715000896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_tx_ovf.715000896
Directory /workspace/3.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.1536315216
Short name T160
Test name
Test status
Simulation time 1379326661 ps
CPU time 8.7 seconds
Started Feb 07 02:19:02 PM PST 24
Finished Feb 07 02:19:12 PM PST 24
Peak memory 203636 kb
Host smart-a919dd95-d798-4f1c-934a-991e7d41d035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536315216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.1536315216
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.361730944
Short name T89
Test name
Test status
Simulation time 18072189 ps
CPU time 0.64 seconds
Started Feb 07 02:25:06 PM PST 24
Finished Feb 07 02:25:07 PM PST 24
Peak memory 202388 kb
Host smart-8104e2e8-0362-4045-be65-6659c711a868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361730944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.361730944
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3836517000
Short name T392
Test name
Test status
Simulation time 87988576 ps
CPU time 1.6 seconds
Started Feb 07 02:25:04 PM PST 24
Finished Feb 07 02:25:06 PM PST 24
Peak memory 211860 kb
Host smart-fed4b97c-78b6-4cfc-ad1e-3f1c0f90812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836517000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3836517000
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3636404123
Short name T467
Test name
Test status
Simulation time 377274398 ps
CPU time 7.17 seconds
Started Feb 07 02:24:55 PM PST 24
Finished Feb 07 02:25:03 PM PST 24
Peak memory 281952 kb
Host smart-cb4abffc-fd49-476a-b385-68ff121ab5e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636404123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3636404123
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2175749133
Short name T696
Test name
Test status
Simulation time 4094351312 ps
CPU time 131.33 seconds
Started Feb 07 02:24:51 PM PST 24
Finished Feb 07 02:27:03 PM PST 24
Peak memory 596552 kb
Host smart-16bb248c-f948-4ba0-ace9-f715ecd45254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175749133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2175749133
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2410611910
Short name T226
Test name
Test status
Simulation time 97469685004 ps
CPU time 390.5 seconds
Started Feb 07 02:24:38 PM PST 24
Finished Feb 07 02:31:09 PM PST 24
Peak memory 1658412 kb
Host smart-37fe2538-a794-4f87-92d3-2aa9b3f2e204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410611910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2410611910
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3502297327
Short name T1342
Test name
Test status
Simulation time 130275754 ps
CPU time 0.95 seconds
Started Feb 07 02:24:36 PM PST 24
Finished Feb 07 02:24:38 PM PST 24
Peak memory 203388 kb
Host smart-7f42894f-f106-4893-97c9-728ffb2ba2d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502297327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3502297327
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2282417520
Short name T421
Test name
Test status
Simulation time 175344998 ps
CPU time 10.4 seconds
Started Feb 07 02:24:55 PM PST 24
Finished Feb 07 02:25:06 PM PST 24
Peak memory 233920 kb
Host smart-e4c40d38-6e2b-4d6a-be5f-9eb3fde6ec3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282417520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2282417520
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2463234501
Short name T915
Test name
Test status
Simulation time 26832971073 ps
CPU time 251.92 seconds
Started Feb 07 02:24:37 PM PST 24
Finished Feb 07 02:28:50 PM PST 24
Peak memory 1344716 kb
Host smart-9a3ee01b-1b77-43d9-8251-d45ed03f50e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463234501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2463234501
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.925015886
Short name T1078
Test name
Test status
Simulation time 12241598775 ps
CPU time 118.69 seconds
Started Feb 07 02:25:01 PM PST 24
Finished Feb 07 02:27:01 PM PST 24
Peak memory 247108 kb
Host smart-a01bbf28-eb27-45ad-9de8-092438a7ec5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925015886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.925015886
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.2846391859
Short name T1083
Test name
Test status
Simulation time 17227644 ps
CPU time 0.65 seconds
Started Feb 07 02:24:37 PM PST 24
Finished Feb 07 02:24:38 PM PST 24
Peak memory 202636 kb
Host smart-498cd0e4-1047-468f-9d24-98e8a15383db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846391859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2846391859
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1134107808
Short name T1180
Test name
Test status
Simulation time 29147236303 ps
CPU time 67.22 seconds
Started Feb 07 02:24:53 PM PST 24
Finished Feb 07 02:26:01 PM PST 24
Peak memory 266308 kb
Host smart-e397b74e-d7a6-4422-b50a-030e99eec33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134107808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1134107808
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.4013738063
Short name T230
Test name
Test status
Simulation time 2391727587 ps
CPU time 193.45 seconds
Started Feb 07 02:24:36 PM PST 24
Finished Feb 07 02:27:51 PM PST 24
Peak memory 294176 kb
Host smart-64c30cb8-5bd8-4dc9-bcba-9bcfc9687cda
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013738063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample
.4013738063
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2215942938
Short name T246
Test name
Test status
Simulation time 2146484726 ps
CPU time 122.37 seconds
Started Feb 07 02:24:35 PM PST 24
Finished Feb 07 02:26:37 PM PST 24
Peak memory 246456 kb
Host smart-5019d00b-0b5e-43e7-a1d3-cd6bd8758173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215942938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2215942938
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3494886389
Short name T551
Test name
Test status
Simulation time 31964877590 ps
CPU time 2346.25 seconds
Started Feb 07 02:25:03 PM PST 24
Finished Feb 07 03:04:11 PM PST 24
Peak memory 3225964 kb
Host smart-31cd6bc9-dd8c-4f60-8d00-e83e8cb2b076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494886389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3494886389
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.4055722487
Short name T605
Test name
Test status
Simulation time 3569842324 ps
CPU time 38.91 seconds
Started Feb 07 02:24:51 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 211888 kb
Host smart-b7bbcf30-6c44-4070-9e07-e8f177092c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055722487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.4055722487
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1985251836
Short name T1069
Test name
Test status
Simulation time 1710001691 ps
CPU time 5.94 seconds
Started Feb 07 02:25:03 PM PST 24
Finished Feb 07 02:25:11 PM PST 24
Peak memory 203588 kb
Host smart-45f1a0fb-908d-449f-b115-f4774845405b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985251836 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1985251836
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.488508795
Short name T196
Test name
Test status
Simulation time 10149925441 ps
CPU time 25.36 seconds
Started Feb 07 02:24:52 PM PST 24
Finished Feb 07 02:25:18 PM PST 24
Peak memory 342120 kb
Host smart-fd7b7033-5694-4e4e-84e7-770e3e72d4a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488508795 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.488508795
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.91119865
Short name T883
Test name
Test status
Simulation time 10040569195 ps
CPU time 79.36 seconds
Started Feb 07 02:24:54 PM PST 24
Finished Feb 07 02:26:14 PM PST 24
Peak memory 654644 kb
Host smart-6ba759ca-1ae6-4e21-a990-1cfb8d521ae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91119865 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_fifo_reset_tx.91119865
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3664977309
Short name T869
Test name
Test status
Simulation time 547838145 ps
CPU time 2.53 seconds
Started Feb 07 02:25:02 PM PST 24
Finished Feb 07 02:25:05 PM PST 24
Peak memory 203612 kb
Host smart-9e0d2793-cfce-4914-94c0-6f770d447acb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664977309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3664977309
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.3471705530
Short name T1050
Test name
Test status
Simulation time 993309069 ps
CPU time 4.51 seconds
Started Feb 07 02:24:55 PM PST 24
Finished Feb 07 02:25:00 PM PST 24
Peak memory 205188 kb
Host smart-8d68c447-8c31-47c8-9e42-c3eab2193399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471705530 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.3471705530
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3284326009
Short name T809
Test name
Test status
Simulation time 15766680796 ps
CPU time 430.05 seconds
Started Feb 07 02:24:52 PM PST 24
Finished Feb 07 02:32:02 PM PST 24
Peak memory 3727508 kb
Host smart-f0ab4e37-31b2-4824-b20c-2cbe839f2d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284326009 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3284326009
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.3366574243
Short name T578
Test name
Test status
Simulation time 696983469 ps
CPU time 4.16 seconds
Started Feb 07 02:25:05 PM PST 24
Finished Feb 07 02:25:10 PM PST 24
Peak memory 203588 kb
Host smart-ddbf13e4-0a8f-491b-998a-b2926250ab9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366574243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.3366574243
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1662420043
Short name T252
Test name
Test status
Simulation time 1445979894 ps
CPU time 14.87 seconds
Started Feb 07 02:25:05 PM PST 24
Finished Feb 07 02:25:21 PM PST 24
Peak memory 203592 kb
Host smart-cd0b8f90-21ef-457a-b998-d8823f1cb5aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662420043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1662420043
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.867277303
Short name T999
Test name
Test status
Simulation time 85446159967 ps
CPU time 1675.9 seconds
Started Feb 07 02:25:03 PM PST 24
Finished Feb 07 02:53:01 PM PST 24
Peak memory 2922968 kb
Host smart-27c5fff2-64b9-4462-9bf2-9ff1ed46f402
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867277303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_stress_all.867277303
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2257003201
Short name T427
Test name
Test status
Simulation time 6276020749 ps
CPU time 24.74 seconds
Started Feb 07 02:24:52 PM PST 24
Finished Feb 07 02:25:17 PM PST 24
Peak memory 225668 kb
Host smart-414bf184-473a-4434-b836-32ee208da5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257003201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2257003201
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3511828749
Short name T1181
Test name
Test status
Simulation time 7262213625 ps
CPU time 31.51 seconds
Started Feb 07 02:25:06 PM PST 24
Finished Feb 07 02:25:39 PM PST 24
Peak memory 824204 kb
Host smart-7e3d1604-eb0a-4074-af47-115a1d3c057f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511828749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3511828749
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.812527626
Short name T1507
Test name
Test status
Simulation time 30654450650 ps
CPU time 49.2 seconds
Started Feb 07 02:24:53 PM PST 24
Finished Feb 07 02:25:43 PM PST 24
Peak memory 631428 kb
Host smart-b11b6880-190b-46b5-8173-2b73f6009565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812527626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.812527626
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1274991381
Short name T442
Test name
Test status
Simulation time 1310124105 ps
CPU time 5.96 seconds
Started Feb 07 02:24:52 PM PST 24
Finished Feb 07 02:24:59 PM PST 24
Peak memory 203600 kb
Host smart-4c2d5766-d383-4cbd-ad36-13f447874d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274991381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1274991381
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_ovf.3524841879
Short name T886
Test name
Test status
Simulation time 6503053462 ps
CPU time 49.15 seconds
Started Feb 07 02:24:51 PM PST 24
Finished Feb 07 02:25:41 PM PST 24
Peak memory 222956 kb
Host smart-46e61fbb-cc5d-4efa-954e-caa9c7754992
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524841879 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_tx_ovf.3524841879
Directory /workspace/30.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.1159419742
Short name T218
Test name
Test status
Simulation time 5351551125 ps
CPU time 5 seconds
Started Feb 07 02:24:50 PM PST 24
Finished Feb 07 02:24:56 PM PST 24
Peak memory 203740 kb
Host smart-dd13e606-3c12-4dbc-9808-7e5a0c6af5e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159419742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.1159419742
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2989605967
Short name T1411
Test name
Test status
Simulation time 68531108 ps
CPU time 0.63 seconds
Started Feb 07 02:25:18 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 202352 kb
Host smart-1cc43cd8-aa84-4935-9085-0bc781e5a678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989605967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2989605967
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3560429068
Short name T594
Test name
Test status
Simulation time 142108701 ps
CPU time 1.69 seconds
Started Feb 07 02:25:12 PM PST 24
Finished Feb 07 02:25:14 PM PST 24
Peak memory 211884 kb
Host smart-117e6e67-59e1-4cd2-801a-b311cfc1b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560429068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3560429068
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3739101430
Short name T1540
Test name
Test status
Simulation time 2076151488 ps
CPU time 8.94 seconds
Started Feb 07 02:25:01 PM PST 24
Finished Feb 07 02:25:11 PM PST 24
Peak memory 306944 kb
Host smart-babf68e4-fd66-4180-9291-72acfeb8d984
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739101430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3739101430
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.373062406
Short name T448
Test name
Test status
Simulation time 7679024053 ps
CPU time 133.21 seconds
Started Feb 07 02:25:07 PM PST 24
Finished Feb 07 02:27:21 PM PST 24
Peak memory 662808 kb
Host smart-693dd11b-f8ff-4997-a055-f9e8d49dffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373062406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.373062406
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.987880870
Short name T181
Test name
Test status
Simulation time 10311808950 ps
CPU time 631.1 seconds
Started Feb 07 02:25:05 PM PST 24
Finished Feb 07 02:35:37 PM PST 24
Peak memory 1518056 kb
Host smart-35ee0a17-ce8d-4ce7-ae10-16f2576b7656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987880870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.987880870
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.739871672
Short name T458
Test name
Test status
Simulation time 301253886 ps
CPU time 3.29 seconds
Started Feb 07 02:25:05 PM PST 24
Finished Feb 07 02:25:10 PM PST 24
Peak memory 203692 kb
Host smart-ae9a8364-3178-4294-9576-d8b778ea0473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739871672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
739871672
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1776766472
Short name T1097
Test name
Test status
Simulation time 6391152385 ps
CPU time 344.57 seconds
Started Feb 07 02:25:01 PM PST 24
Finished Feb 07 02:30:46 PM PST 24
Peak memory 1735228 kb
Host smart-d0e55c79-a548-4586-9da8-ef6c0d7499b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776766472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1776766472
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_override.778947189
Short name T1003
Test name
Test status
Simulation time 24306613 ps
CPU time 0.65 seconds
Started Feb 07 02:25:08 PM PST 24
Finished Feb 07 02:25:10 PM PST 24
Peak memory 203304 kb
Host smart-0457b14d-d448-402f-9c69-0ab03f2060eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778947189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.778947189
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3041850959
Short name T139
Test name
Test status
Simulation time 3161057152 ps
CPU time 20.09 seconds
Started Feb 07 02:25:04 PM PST 24
Finished Feb 07 02:25:25 PM PST 24
Peak memory 220008 kb
Host smart-7d6f361b-8e30-43d4-9f59-9dd0cccb2fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041850959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3041850959
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.952643498
Short name T1042
Test name
Test status
Simulation time 35372179986 ps
CPU time 96.11 seconds
Started Feb 07 02:25:03 PM PST 24
Finished Feb 07 02:26:41 PM PST 24
Peak memory 252384 kb
Host smart-7a56526d-7b35-4bf7-81c8-cd88bfc1e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952643498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.952643498
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2006590826
Short name T839
Test name
Test status
Simulation time 619228576 ps
CPU time 9.16 seconds
Started Feb 07 02:25:09 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 212768 kb
Host smart-15fdeb2f-4d65-4e97-a2f8-18642eb23135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006590826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2006590826
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2028229096
Short name T468
Test name
Test status
Simulation time 630281292 ps
CPU time 2.54 seconds
Started Feb 07 02:25:15 PM PST 24
Finished Feb 07 02:25:19 PM PST 24
Peak memory 203624 kb
Host smart-4238746b-39fd-46f6-bc14-6012d19e7675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028229096 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2028229096
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.4178028290
Short name T463
Test name
Test status
Simulation time 10080728788 ps
CPU time 59.26 seconds
Started Feb 07 02:25:09 PM PST 24
Finished Feb 07 02:26:10 PM PST 24
Peak memory 585692 kb
Host smart-21d94982-64b6-481a-80e9-066e8e6d8a9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178028290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.4178028290
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2516906484
Short name T1283
Test name
Test status
Simulation time 988928240 ps
CPU time 2.38 seconds
Started Feb 07 02:25:17 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 203548 kb
Host smart-ecf0ad1a-699c-4bdc-83e4-250f470da9a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516906484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2516906484
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.882289032
Short name T1349
Test name
Test status
Simulation time 1391220688 ps
CPU time 3.46 seconds
Started Feb 07 02:25:10 PM PST 24
Finished Feb 07 02:25:15 PM PST 24
Peak memory 203632 kb
Host smart-cf3a3394-16ae-4668-8920-1ecc4813b18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882289032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.882289032
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1986359848
Short name T519
Test name
Test status
Simulation time 15090167284 ps
CPU time 59.15 seconds
Started Feb 07 02:25:10 PM PST 24
Finished Feb 07 02:26:10 PM PST 24
Peak memory 898772 kb
Host smart-23e5871e-65c0-4a16-9098-611dcb217090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986359848 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1986359848
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.1027036215
Short name T311
Test name
Test status
Simulation time 711302802 ps
CPU time 4.25 seconds
Started Feb 07 02:25:13 PM PST 24
Finished Feb 07 02:25:18 PM PST 24
Peak memory 203580 kb
Host smart-b8167a0a-827d-42ec-95fb-554224688ae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027036215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.1027036215
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1213329102
Short name T761
Test name
Test status
Simulation time 1044660317 ps
CPU time 5.52 seconds
Started Feb 07 02:25:14 PM PST 24
Finished Feb 07 02:25:21 PM PST 24
Peak memory 203620 kb
Host smart-d69c19fc-62b5-4c22-82f4-e6bbe6aee14c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213329102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1213329102
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.2382737443
Short name T592
Test name
Test status
Simulation time 82965119754 ps
CPU time 563.93 seconds
Started Feb 07 02:25:10 PM PST 24
Finished Feb 07 02:34:35 PM PST 24
Peak memory 2920704 kb
Host smart-82afdde4-69a0-44fe-9bda-6092ca3466bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382737443 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.2382737443
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1255872283
Short name T1317
Test name
Test status
Simulation time 2148448066 ps
CPU time 88.6 seconds
Started Feb 07 02:25:09 PM PST 24
Finished Feb 07 02:26:40 PM PST 24
Peak memory 205068 kb
Host smart-a970732c-6969-4a3d-9462-a5481dedee33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255872283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1255872283
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.968256637
Short name T1075
Test name
Test status
Simulation time 25479358037 ps
CPU time 251.75 seconds
Started Feb 07 02:25:13 PM PST 24
Finished Feb 07 02:29:25 PM PST 24
Peak memory 2724368 kb
Host smart-5b94a469-417d-48a9-b300-0651e27b7a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968256637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_wr.968256637
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2940620717
Short name T1485
Test name
Test status
Simulation time 37553963525 ps
CPU time 1542.73 seconds
Started Feb 07 02:25:06 PM PST 24
Finished Feb 07 02:50:50 PM PST 24
Peak memory 4575932 kb
Host smart-692fef8f-394a-4960-b267-939b84666e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940620717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2940620717
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.22399537
Short name T209
Test name
Test status
Simulation time 5594899832 ps
CPU time 6.27 seconds
Started Feb 07 02:25:05 PM PST 24
Finished Feb 07 02:25:13 PM PST 24
Peak memory 203708 kb
Host smart-73c41e7c-9964-4832-9e10-161fc26b87b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22399537 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_timeout.22399537
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_ovf.881372102
Short name T597
Test name
Test status
Simulation time 14619571446 ps
CPU time 43.54 seconds
Started Feb 07 02:25:08 PM PST 24
Finished Feb 07 02:25:53 PM PST 24
Peak memory 222292 kb
Host smart-8574bebb-3a52-478c-afec-ce1e37b1ff23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881372102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_tx_ovf.881372102
Directory /workspace/31.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.892369160
Short name T1522
Test name
Test status
Simulation time 20484791582 ps
CPU time 6.84 seconds
Started Feb 07 02:25:09 PM PST 24
Finished Feb 07 02:25:17 PM PST 24
Peak memory 212648 kb
Host smart-37cb2c32-f8c2-40b4-b22a-1d885f456106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892369160 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_unexp_stop.892369160
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3500475473
Short name T1175
Test name
Test status
Simulation time 17113665 ps
CPU time 0.61 seconds
Started Feb 07 02:25:24 PM PST 24
Finished Feb 07 02:25:28 PM PST 24
Peak memory 202324 kb
Host smart-349590c7-c71a-4628-b6f4-48bec27cfb9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500475473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3500475473
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.73576676
Short name T1117
Test name
Test status
Simulation time 97233141 ps
CPU time 1.41 seconds
Started Feb 07 02:25:21 PM PST 24
Finished Feb 07 02:25:27 PM PST 24
Peak memory 219936 kb
Host smart-e8be9256-4b58-4e0a-9918-eafbae57943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73576676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.73576676
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.195966709
Short name T747
Test name
Test status
Simulation time 2972993488 ps
CPU time 6.99 seconds
Started Feb 07 02:25:16 PM PST 24
Finished Feb 07 02:25:24 PM PST 24
Peak memory 284776 kb
Host smart-e7916d00-795a-40ad-b41c-d5464a9a86ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195966709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.195966709
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.168328782
Short name T644
Test name
Test status
Simulation time 7545625075 ps
CPU time 143.4 seconds
Started Feb 07 02:25:14 PM PST 24
Finished Feb 07 02:27:38 PM PST 24
Peak memory 710120 kb
Host smart-b2278856-be6f-4f2a-a97e-2e1d2079cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168328782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.168328782
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2305710549
Short name T977
Test name
Test status
Simulation time 18685232746 ps
CPU time 283.15 seconds
Started Feb 07 02:25:20 PM PST 24
Finished Feb 07 02:30:04 PM PST 24
Peak memory 1335384 kb
Host smart-a1cd62ba-916d-40cc-8425-c15b2d8d6d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305710549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2305710549
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1494980711
Short name T710
Test name
Test status
Simulation time 695750849 ps
CPU time 0.79 seconds
Started Feb 07 02:25:18 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 203356 kb
Host smart-7327c263-f696-463c-9e4a-5d7b2a96cfe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494980711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1494980711
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.141857371
Short name T1473
Test name
Test status
Simulation time 2089122636 ps
CPU time 6.6 seconds
Started Feb 07 02:25:14 PM PST 24
Finished Feb 07 02:25:22 PM PST 24
Peak memory 255440 kb
Host smart-319e9b1a-d0ce-4662-84b8-30757c151b4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141857371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
141857371
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2569176443
Short name T674
Test name
Test status
Simulation time 15020864205 ps
CPU time 305.06 seconds
Started Feb 07 02:25:14 PM PST 24
Finished Feb 07 02:30:20 PM PST 24
Peak memory 1660164 kb
Host smart-ca7ad4ee-61d1-4421-970a-346a14e42e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569176443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2569176443
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3869318643
Short name T41
Test name
Test status
Simulation time 2244770208 ps
CPU time 59.51 seconds
Started Feb 07 02:25:22 PM PST 24
Finished Feb 07 02:26:27 PM PST 24
Peak memory 279828 kb
Host smart-ec9712ad-9a56-4653-a954-799b57a8c3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869318643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3869318643
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.1760784241
Short name T469
Test name
Test status
Simulation time 28549573 ps
CPU time 0.65 seconds
Started Feb 07 02:25:19 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 202652 kb
Host smart-ebb078f1-4ba9-432e-91cf-1500306077b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760784241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1760784241
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1771631999
Short name T1423
Test name
Test status
Simulation time 3667674015 ps
CPU time 170.2 seconds
Started Feb 07 02:25:15 PM PST 24
Finished Feb 07 02:28:06 PM PST 24
Peak memory 228324 kb
Host smart-5c0319c0-78ca-4e22-933c-447a44cfdce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771631999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1771631999
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.3485616671
Short name T281
Test name
Test status
Simulation time 1973613173 ps
CPU time 154.81 seconds
Started Feb 07 02:25:17 PM PST 24
Finished Feb 07 02:27:53 PM PST 24
Peak memory 279312 kb
Host smart-cf07e6d5-5eeb-4698-be12-17a1f218e499
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485616671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample
.3485616671
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.715508125
Short name T1495
Test name
Test status
Simulation time 1639120878 ps
CPU time 24.25 seconds
Started Feb 07 02:25:14 PM PST 24
Finished Feb 07 02:25:39 PM PST 24
Peak memory 227512 kb
Host smart-abc80baa-02ee-49a9-aae4-770c8b6bda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715508125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.715508125
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.4234228355
Short name T759
Test name
Test status
Simulation time 1005528050 ps
CPU time 16.09 seconds
Started Feb 07 02:25:16 PM PST 24
Finished Feb 07 02:25:33 PM PST 24
Peak memory 212844 kb
Host smart-b1740cee-5cf0-4254-ac5b-5f8d7c49c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234228355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.4234228355
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.138466453
Short name T1269
Test name
Test status
Simulation time 6136227227 ps
CPU time 4.53 seconds
Started Feb 07 02:25:28 PM PST 24
Finished Feb 07 02:25:35 PM PST 24
Peak memory 203752 kb
Host smart-b844bea4-463b-4928-91dc-f0e1e7dbbe55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138466453 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.138466453
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3288135242
Short name T1061
Test name
Test status
Simulation time 10186922564 ps
CPU time 62.77 seconds
Started Feb 07 02:25:21 PM PST 24
Finished Feb 07 02:26:28 PM PST 24
Peak memory 508476 kb
Host smart-06ef2a34-34db-44ff-9bb2-72829e8c6a81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288135242 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3288135242
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.4023216631
Short name T979
Test name
Test status
Simulation time 10179668727 ps
CPU time 12.92 seconds
Started Feb 07 02:25:16 PM PST 24
Finished Feb 07 02:25:29 PM PST 24
Peak memory 272868 kb
Host smart-f218a89b-9ce2-4ff3-a3b0-bbde92b998b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023216631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.4023216631
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.4192150124
Short name T1141
Test name
Test status
Simulation time 550623766 ps
CPU time 2.69 seconds
Started Feb 07 02:25:23 PM PST 24
Finished Feb 07 02:25:30 PM PST 24
Peak memory 203664 kb
Host smart-a1b6b3cb-18f3-4d1c-8b85-6292a793b01a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192150124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.4192150124
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1067537848
Short name T707
Test name
Test status
Simulation time 5070700864 ps
CPU time 5.28 seconds
Started Feb 07 02:25:19 PM PST 24
Finished Feb 07 02:25:26 PM PST 24
Peak memory 203708 kb
Host smart-d21fe811-f365-4d93-9cc2-3b548f64c473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067537848 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1067537848
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.590598630
Short name T485
Test name
Test status
Simulation time 4274885452 ps
CPU time 1.62 seconds
Started Feb 07 02:25:15 PM PST 24
Finished Feb 07 02:25:18 PM PST 24
Peak memory 203756 kb
Host smart-68d4b244-ba8b-4db9-a12c-a4fed3f4ed8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590598630 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.590598630
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.2335595706
Short name T1110
Test name
Test status
Simulation time 4172542969 ps
CPU time 3.33 seconds
Started Feb 07 02:25:19 PM PST 24
Finished Feb 07 02:25:24 PM PST 24
Peak memory 203736 kb
Host smart-f4dd9304-3c06-419c-8bea-79a4f4c5851d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335595706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.2335595706
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.152969547
Short name T1336
Test name
Test status
Simulation time 1277010069 ps
CPU time 16.04 seconds
Started Feb 07 02:25:15 PM PST 24
Finished Feb 07 02:25:32 PM PST 24
Peak memory 203576 kb
Host smart-d8673507-8075-42d1-8641-b63e1568375c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152969547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.152969547
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.3326017493
Short name T521
Test name
Test status
Simulation time 18942312892 ps
CPU time 799.63 seconds
Started Feb 07 02:25:22 PM PST 24
Finished Feb 07 02:38:47 PM PST 24
Peak memory 1564920 kb
Host smart-19a7c24d-1a11-4f43-93ea-400ed4a8fb3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326017493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.3326017493
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1181736363
Short name T338
Test name
Test status
Simulation time 16372549563 ps
CPU time 35.12 seconds
Started Feb 07 02:25:17 PM PST 24
Finished Feb 07 02:25:53 PM PST 24
Peak memory 224728 kb
Host smart-acf8f603-3dcc-4e68-bfe3-ade967b33d03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181736363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1181736363
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.4006525894
Short name T295
Test name
Test status
Simulation time 18975928858 ps
CPU time 116.34 seconds
Started Feb 07 02:25:17 PM PST 24
Finished Feb 07 02:27:14 PM PST 24
Peak memory 1963664 kb
Host smart-13466e7c-e437-4c87-9d22-93c29b522438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006525894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.4006525894
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.415420790
Short name T1380
Test name
Test status
Simulation time 19415952236 ps
CPU time 3171.66 seconds
Started Feb 07 02:25:19 PM PST 24
Finished Feb 07 03:18:12 PM PST 24
Peak memory 4657884 kb
Host smart-ac495ed0-13d3-419e-952e-e925c56b76ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415420790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.415420790
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1846980158
Short name T273
Test name
Test status
Simulation time 5954070822 ps
CPU time 6.94 seconds
Started Feb 07 02:25:15 PM PST 24
Finished Feb 07 02:25:23 PM PST 24
Peak memory 212808 kb
Host smart-9a5b831c-b03f-4e31-9ced-b70863e142fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846980158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1846980158
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_ovf.1051909955
Short name T819
Test name
Test status
Simulation time 5955750963 ps
CPU time 149.36 seconds
Started Feb 07 02:25:17 PM PST 24
Finished Feb 07 02:27:47 PM PST 24
Peak memory 434256 kb
Host smart-849d2268-dae1-40e2-a64b-4ce66ba77202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051909955 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_tx_ovf.1051909955
Directory /workspace/32.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.2051169772
Short name T299
Test name
Test status
Simulation time 1362412139 ps
CPU time 5.91 seconds
Started Feb 07 02:25:21 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 203696 kb
Host smart-b677a9f2-01f8-4fc6-a716-d1dc32d39456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051169772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.2051169772
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2768796430
Short name T353
Test name
Test status
Simulation time 28353502 ps
CPU time 0.61 seconds
Started Feb 07 02:25:29 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 202336 kb
Host smart-439f22a1-2dd0-4cd5-85ad-d28e893d7e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768796430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2768796430
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2041162138
Short name T272
Test name
Test status
Simulation time 52882447 ps
CPU time 1.41 seconds
Started Feb 07 02:25:20 PM PST 24
Finished Feb 07 02:25:26 PM PST 24
Peak memory 211804 kb
Host smart-bd3950f9-624e-416e-a224-db48195e156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041162138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2041162138
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.4197989998
Short name T762
Test name
Test status
Simulation time 1473230629 ps
CPU time 18.06 seconds
Started Feb 07 02:25:24 PM PST 24
Finished Feb 07 02:25:45 PM PST 24
Peak memory 259116 kb
Host smart-1e95072b-6455-4660-8ee3-4f3e24de46b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197989998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.4197989998
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1128670960
Short name T972
Test name
Test status
Simulation time 3389411952 ps
CPU time 111.33 seconds
Started Feb 07 02:25:25 PM PST 24
Finished Feb 07 02:27:19 PM PST 24
Peak memory 741132 kb
Host smart-5ed3a49d-d83a-47aa-89ac-5f072c8b106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128670960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1128670960
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3970432359
Short name T970
Test name
Test status
Simulation time 8412888786 ps
CPU time 261.45 seconds
Started Feb 07 02:25:25 PM PST 24
Finished Feb 07 02:29:49 PM PST 24
Peak memory 1297260 kb
Host smart-c36c1786-f5e5-45e1-8ee5-53488e4bf948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970432359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3970432359
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3869119546
Short name T493
Test name
Test status
Simulation time 411481123 ps
CPU time 1 seconds
Started Feb 07 02:25:21 PM PST 24
Finished Feb 07 02:25:28 PM PST 24
Peak memory 203604 kb
Host smart-3373490c-8202-46f6-89e6-30ea81d01b39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869119546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3869119546
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2809220256
Short name T1029
Test name
Test status
Simulation time 642631010 ps
CPU time 5.13 seconds
Started Feb 07 02:25:20 PM PST 24
Finished Feb 07 02:25:27 PM PST 24
Peak memory 237848 kb
Host smart-992780e9-38f2-4077-b873-5479c9b46d98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809220256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2809220256
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3648517999
Short name T1477
Test name
Test status
Simulation time 3496067956 ps
CPU time 159.62 seconds
Started Feb 07 02:25:25 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 1067344 kb
Host smart-745c8423-0853-449d-b609-78290cc8d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648517999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3648517999
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1706429160
Short name T487
Test name
Test status
Simulation time 9503352109 ps
CPU time 41.47 seconds
Started Feb 07 02:25:33 PM PST 24
Finished Feb 07 02:26:15 PM PST 24
Peak memory 295056 kb
Host smart-0ced0b91-1ec8-46a4-bda9-371aecddc20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706429160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1706429160
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3713661543
Short name T942
Test name
Test status
Simulation time 19494432 ps
CPU time 0.64 seconds
Started Feb 07 02:25:29 PM PST 24
Finished Feb 07 02:25:31 PM PST 24
Peak memory 202632 kb
Host smart-9cbc9861-f2ff-44c9-af08-1df31d3acfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713661543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3713661543
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.2023851679
Short name T143
Test name
Test status
Simulation time 5588785267 ps
CPU time 123.61 seconds
Started Feb 07 02:25:25 PM PST 24
Finished Feb 07 02:27:31 PM PST 24
Peak memory 203796 kb
Host smart-82d53bdd-fe22-4914-a40c-4be6d2490568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023851679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2023851679
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.603529333
Short name T1460
Test name
Test status
Simulation time 15039135310 ps
CPU time 109.11 seconds
Started Feb 07 02:25:23 PM PST 24
Finished Feb 07 02:27:16 PM PST 24
Peak memory 350032 kb
Host smart-85f10269-da3c-4ac5-9e36-e47b68a37fb0
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603529333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample.
603529333
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3987264863
Short name T336
Test name
Test status
Simulation time 1392869260 ps
CPU time 80.34 seconds
Started Feb 07 02:25:30 PM PST 24
Finished Feb 07 02:26:51 PM PST 24
Peak memory 244852 kb
Host smart-796e5583-de30-4425-ba30-d541af6d9701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987264863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3987264863
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1173305595
Short name T689
Test name
Test status
Simulation time 1182895925 ps
CPU time 9.37 seconds
Started Feb 07 02:25:25 PM PST 24
Finished Feb 07 02:25:37 PM PST 24
Peak memory 212860 kb
Host smart-d268f62a-68ab-4e49-91ce-cdf80a196059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173305595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1173305595
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2802696745
Short name T888
Test name
Test status
Simulation time 1206219330 ps
CPU time 4.34 seconds
Started Feb 07 02:25:32 PM PST 24
Finished Feb 07 02:25:37 PM PST 24
Peak memory 203616 kb
Host smart-a29a5d6f-73e1-46bd-90e3-9919bc01cef9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802696745 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2802696745
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3659733928
Short name T1060
Test name
Test status
Simulation time 10260791603 ps
CPU time 11.63 seconds
Started Feb 07 02:25:34 PM PST 24
Finished Feb 07 02:25:47 PM PST 24
Peak memory 263744 kb
Host smart-bcca3966-13f1-44f5-bb40-1d4b2e2d0041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659733928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3659733928
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.250104847
Short name T1498
Test name
Test status
Simulation time 10333152171 ps
CPU time 3.64 seconds
Started Feb 07 02:25:31 PM PST 24
Finished Feb 07 02:25:36 PM PST 24
Peak memory 235252 kb
Host smart-e8342de8-1f5c-45ae-b44b-e702a6501343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250104847 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.250104847
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.297756937
Short name T1214
Test name
Test status
Simulation time 1796415571 ps
CPU time 2.68 seconds
Started Feb 07 02:25:37 PM PST 24
Finished Feb 07 02:25:41 PM PST 24
Peak memory 203588 kb
Host smart-e83e639e-b96f-4e06-aa7d-d975a7f25e88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297756937 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_hrst.297756937
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2973323480
Short name T335
Test name
Test status
Simulation time 7245904627 ps
CPU time 7.18 seconds
Started Feb 07 02:25:33 PM PST 24
Finished Feb 07 02:25:41 PM PST 24
Peak memory 205200 kb
Host smart-13f42d2e-5b5b-4820-923a-9bfdde33b5e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973323480 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2973323480
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2348132316
Short name T360
Test name
Test status
Simulation time 5732759906 ps
CPU time 10.02 seconds
Started Feb 07 02:25:31 PM PST 24
Finished Feb 07 02:25:42 PM PST 24
Peak memory 395404 kb
Host smart-2863078d-ed85-43a8-a637-fe908a549320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348132316 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2348132316
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.611782818
Short name T704
Test name
Test status
Simulation time 600528904 ps
CPU time 3.84 seconds
Started Feb 07 02:25:34 PM PST 24
Finished Feb 07 02:25:39 PM PST 24
Peak memory 203636 kb
Host smart-926dad5f-7936-46ae-8093-4e0f455b50c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611782818 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_perf.611782818
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.819992429
Short name T760
Test name
Test status
Simulation time 913534117 ps
CPU time 11.63 seconds
Started Feb 07 02:25:25 PM PST 24
Finished Feb 07 02:25:39 PM PST 24
Peak memory 203680 kb
Host smart-3139b606-3111-4202-a35d-eb99513237bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819992429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.819992429
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.3382878053
Short name T832
Test name
Test status
Simulation time 42895479699 ps
CPU time 1195.32 seconds
Started Feb 07 02:25:29 PM PST 24
Finished Feb 07 02:45:26 PM PST 24
Peak memory 7039412 kb
Host smart-98cab241-d60a-479f-be1b-8b597b0ab04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382878053 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.3382878053
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.952469635
Short name T394
Test name
Test status
Simulation time 1735984403 ps
CPU time 15.24 seconds
Started Feb 07 02:25:28 PM PST 24
Finished Feb 07 02:25:45 PM PST 24
Peak memory 204956 kb
Host smart-e3c13fbf-379c-4b41-99ab-a7ba50aa2b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952469635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.952469635
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.3614227089
Short name T900
Test name
Test status
Simulation time 15822608452 ps
CPU time 31.61 seconds
Started Feb 07 02:25:24 PM PST 24
Finished Feb 07 02:25:59 PM PST 24
Peak memory 841704 kb
Host smart-ad697fa9-a289-4d89-a4f3-6ec636072bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614227089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.3614227089
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2742110232
Short name T1098
Test name
Test status
Simulation time 19519367398 ps
CPU time 1145.65 seconds
Started Feb 07 02:25:23 PM PST 24
Finished Feb 07 02:44:33 PM PST 24
Peak memory 4636068 kb
Host smart-9b8489bb-e218-48fa-b98d-f8a713684987
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742110232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2742110232
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3374118518
Short name T29
Test name
Test status
Simulation time 3324995007 ps
CPU time 7.09 seconds
Started Feb 07 02:25:36 PM PST 24
Finished Feb 07 02:25:44 PM PST 24
Peak memory 214660 kb
Host smart-2c8a65e4-fb90-424c-9f55-c3ab4dda09af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374118518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3374118518
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_ovf.1131383878
Short name T1230
Test name
Test status
Simulation time 5574075820 ps
CPU time 43.25 seconds
Started Feb 07 02:25:28 PM PST 24
Finished Feb 07 02:26:14 PM PST 24
Peak memory 224760 kb
Host smart-e78a8b2e-ed25-4111-8e7b-b8239acac358
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131383878 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_tx_ovf.1131383878
Directory /workspace/33.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.622710988
Short name T966
Test name
Test status
Simulation time 13984853465 ps
CPU time 6.73 seconds
Started Feb 07 02:25:37 PM PST 24
Finished Feb 07 02:25:45 PM PST 24
Peak memory 203772 kb
Host smart-afd5d498-53d8-4f2f-bf9c-21cc7484c4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622710988 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_unexp_stop.622710988
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1884542619
Short name T324
Test name
Test status
Simulation time 16452354 ps
CPU time 0.61 seconds
Started Feb 07 02:26:00 PM PST 24
Finished Feb 07 02:26:02 PM PST 24
Peak memory 202316 kb
Host smart-31d2189f-b47e-4b80-abf4-b45565a35b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884542619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1884542619
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3286788645
Short name T1543
Test name
Test status
Simulation time 41928446 ps
CPU time 1.09 seconds
Started Feb 07 02:25:39 PM PST 24
Finished Feb 07 02:25:42 PM PST 24
Peak memory 220096 kb
Host smart-d1b4ba42-c90f-43ae-84ea-381ed17f383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286788645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3286788645
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1606602705
Short name T634
Test name
Test status
Simulation time 2023330541 ps
CPU time 9.24 seconds
Started Feb 07 02:25:36 PM PST 24
Finished Feb 07 02:25:46 PM PST 24
Peak memory 315200 kb
Host smart-49568e88-04e8-4a43-be66-4bb9ec15bb3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606602705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1606602705
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1803795743
Short name T1043
Test name
Test status
Simulation time 5544241866 ps
CPU time 81.06 seconds
Started Feb 07 02:25:38 PM PST 24
Finished Feb 07 02:27:01 PM PST 24
Peak memory 601784 kb
Host smart-5f7f356a-7e86-4ae9-b7cc-07cc706b6ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803795743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1803795743
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3037699400
Short name T1275
Test name
Test status
Simulation time 13986633746 ps
CPU time 222.68 seconds
Started Feb 07 02:25:41 PM PST 24
Finished Feb 07 02:29:30 PM PST 24
Peak memory 1149412 kb
Host smart-8cedb134-5726-4241-93bc-0152abde80ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037699400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3037699400
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3911296164
Short name T365
Test name
Test status
Simulation time 106170856 ps
CPU time 0.75 seconds
Started Feb 07 02:25:37 PM PST 24
Finished Feb 07 02:25:39 PM PST 24
Peak memory 203432 kb
Host smart-5c2d9232-22f6-4f57-9beb-1eb71b805c5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911296164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3911296164
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3472669662
Short name T1291
Test name
Test status
Simulation time 3053997349 ps
CPU time 4.53 seconds
Started Feb 07 02:25:37 PM PST 24
Finished Feb 07 02:25:43 PM PST 24
Peak memory 203816 kb
Host smart-5a4ba5ce-8e62-4251-8adf-774dc990ce7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472669662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3472669662
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.425206007
Short name T764
Test name
Test status
Simulation time 27227077297 ps
CPU time 409.4 seconds
Started Feb 07 02:25:39 PM PST 24
Finished Feb 07 02:32:30 PM PST 24
Peak memory 1853416 kb
Host smart-438f33f6-c47f-43f9-9479-32d8b5b18312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425206007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.425206007
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3135931310
Short name T687
Test name
Test status
Simulation time 8626931440 ps
CPU time 111.49 seconds
Started Feb 07 02:26:01 PM PST 24
Finished Feb 07 02:27:54 PM PST 24
Peak memory 236272 kb
Host smart-373eb02a-70c5-4e01-acaa-c5dd17a6204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135931310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3135931310
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1094052813
Short name T1362
Test name
Test status
Simulation time 38779704 ps
CPU time 0.63 seconds
Started Feb 07 02:25:48 PM PST 24
Finished Feb 07 02:25:51 PM PST 24
Peak memory 203344 kb
Host smart-9fc6c9a9-07e9-48a2-b8db-e549e006b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094052813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1094052813
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.36122066
Short name T1422
Test name
Test status
Simulation time 4151080042 ps
CPU time 12.51 seconds
Started Feb 07 02:25:48 PM PST 24
Finished Feb 07 02:26:03 PM PST 24
Peak memory 203788 kb
Host smart-6ce4cc43-2884-4a7a-accd-ef80dfaad82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36122066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.36122066
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.2090177285
Short name T342
Test name
Test status
Simulation time 3609184945 ps
CPU time 183.55 seconds
Started Feb 07 02:25:42 PM PST 24
Finished Feb 07 02:28:51 PM PST 24
Peak memory 281080 kb
Host smart-ef58685a-8530-46b7-99bb-b69744e1ea0b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090177285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample
.2090177285
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2084364755
Short name T586
Test name
Test status
Simulation time 7069749363 ps
CPU time 95.02 seconds
Started Feb 07 02:25:40 PM PST 24
Finished Feb 07 02:27:16 PM PST 24
Peak memory 241908 kb
Host smart-fc0f3fcd-3aa8-4f4e-8c1c-4dc96bc55aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084364755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2084364755
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3435870113
Short name T631
Test name
Test status
Simulation time 3371420906 ps
CPU time 16.86 seconds
Started Feb 07 02:25:40 PM PST 24
Finished Feb 07 02:26:03 PM PST 24
Peak memory 217724 kb
Host smart-0bd540b6-42ec-4b8a-9d41-8ffcfd29457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435870113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3435870113
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2510717245
Short name T1329
Test name
Test status
Simulation time 836849231 ps
CPU time 3.96 seconds
Started Feb 07 02:26:01 PM PST 24
Finished Feb 07 02:26:06 PM PST 24
Peak memory 203600 kb
Host smart-baf47e44-0c71-4375-ab1c-f95fd89edad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510717245 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2510717245
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1930304582
Short name T1518
Test name
Test status
Simulation time 10056458658 ps
CPU time 72.72 seconds
Started Feb 07 02:25:54 PM PST 24
Finished Feb 07 02:27:10 PM PST 24
Peak memory 567388 kb
Host smart-d76c1bed-02f8-4d69-9ac4-ba34bc21ceb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930304582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1930304582
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2618970335
Short name T366
Test name
Test status
Simulation time 10179028052 ps
CPU time 75.59 seconds
Started Feb 07 02:26:01 PM PST 24
Finished Feb 07 02:27:18 PM PST 24
Peak memory 673052 kb
Host smart-79427cab-ecfe-40fe-9ba0-f6a37c91bb7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618970335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2618970335
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2614908781
Short name T938
Test name
Test status
Simulation time 588880692 ps
CPU time 3.24 seconds
Started Feb 07 02:26:02 PM PST 24
Finished Feb 07 02:26:06 PM PST 24
Peak memory 203620 kb
Host smart-5abef13e-1112-431a-9f3b-787dd6d47620
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614908781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2614908781
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2807123801
Short name T433
Test name
Test status
Simulation time 3285454822 ps
CPU time 3.83 seconds
Started Feb 07 02:25:59 PM PST 24
Finished Feb 07 02:26:05 PM PST 24
Peak memory 203728 kb
Host smart-a5cf6580-534f-4dad-b494-d08e34b7cf4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807123801 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2807123801
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1043881224
Short name T1171
Test name
Test status
Simulation time 19395932725 ps
CPU time 262 seconds
Started Feb 07 02:25:55 PM PST 24
Finished Feb 07 02:30:20 PM PST 24
Peak memory 2303260 kb
Host smart-fb71b4b7-0c6f-42ad-a814-4b70cee3e0b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043881224 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1043881224
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.140528964
Short name T481
Test name
Test status
Simulation time 1681402597 ps
CPU time 4.88 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:26:10 PM PST 24
Peak memory 203672 kb
Host smart-fe17420c-a7a2-4761-9be1-6e2055feb5a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140528964 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_perf.140528964
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1764131551
Short name T1354
Test name
Test status
Simulation time 1625965645 ps
CPU time 16.75 seconds
Started Feb 07 02:25:54 PM PST 24
Finished Feb 07 02:26:14 PM PST 24
Peak memory 203616 kb
Host smart-e9928cfd-5703-4906-964d-3fa554c27887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764131551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1764131551
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.2727853796
Short name T1527
Test name
Test status
Simulation time 52804091304 ps
CPU time 39.9 seconds
Started Feb 07 02:26:00 PM PST 24
Finished Feb 07 02:26:42 PM PST 24
Peak memory 236284 kb
Host smart-60e57b3c-19d3-4f3d-b36c-cffc915cab9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727853796 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.2727853796
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.29249055
Short name T256
Test name
Test status
Simulation time 1089003261 ps
CPU time 9.94 seconds
Started Feb 07 02:25:53 PM PST 24
Finished Feb 07 02:26:07 PM PST 24
Peak memory 203580 kb
Host smart-5e66ca07-3ae0-4d98-aa05-977a565d9ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29249055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stress_rd.29249055
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2859854700
Short name T847
Test name
Test status
Simulation time 56737485209 ps
CPU time 50.2 seconds
Started Feb 07 02:25:55 PM PST 24
Finished Feb 07 02:26:48 PM PST 24
Peak memory 774632 kb
Host smart-0b3d1aee-9b60-4657-b961-a4f2b0d6e7eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859854700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2859854700
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.4290351244
Short name T331
Test name
Test status
Simulation time 20762600431 ps
CPU time 92.34 seconds
Started Feb 07 02:25:54 PM PST 24
Finished Feb 07 02:27:30 PM PST 24
Peak memory 1057388 kb
Host smart-708bdce3-ed07-451e-b16a-8cf3bfbd78fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290351244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.4290351244
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1687385938
Short name T770
Test name
Test status
Simulation time 18614613311 ps
CPU time 7.29 seconds
Started Feb 07 02:25:55 PM PST 24
Finished Feb 07 02:26:05 PM PST 24
Peak memory 203804 kb
Host smart-cd49f26a-e4e1-49a1-a9b5-6a53ab339420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687385938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1687385938
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_ovf.1544555771
Short name T145
Test name
Test status
Simulation time 18275647547 ps
CPU time 98.97 seconds
Started Feb 07 02:25:55 PM PST 24
Finished Feb 07 02:27:36 PM PST 24
Peak memory 336084 kb
Host smart-3e9ae0d1-3045-4a0f-aa7f-c61e3d30c869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544555771 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_tx_ovf.1544555771
Directory /workspace/34.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.2520273358
Short name T1467
Test name
Test status
Simulation time 1250481915 ps
CPU time 4.83 seconds
Started Feb 07 02:25:54 PM PST 24
Finished Feb 07 02:26:02 PM PST 24
Peak memory 206928 kb
Host smart-28a606e9-de03-452b-845b-a7602f3c3854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520273358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.2520273358
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.53362655
Short name T898
Test name
Test status
Simulation time 28229429 ps
CPU time 0.59 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:26:12 PM PST 24
Peak memory 202400 kb
Host smart-7d42a35e-d5c7-40ca-be83-f86c39d281ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53362655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.53362655
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1496085597
Short name T1352
Test name
Test status
Simulation time 81700980 ps
CPU time 1.73 seconds
Started Feb 07 02:26:00 PM PST 24
Finished Feb 07 02:26:03 PM PST 24
Peak memory 211808 kb
Host smart-3a2665d9-5c06-409b-b542-4a5e5c238c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496085597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1496085597
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2107284160
Short name T300
Test name
Test status
Simulation time 1588329945 ps
CPU time 43.45 seconds
Started Feb 07 02:26:04 PM PST 24
Finished Feb 07 02:26:49 PM PST 24
Peak memory 386888 kb
Host smart-710603ce-8290-4e4c-bd92-944c3fc991e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107284160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2107284160
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1918610816
Short name T341
Test name
Test status
Simulation time 20410702945 ps
CPU time 132.49 seconds
Started Feb 07 02:26:04 PM PST 24
Finished Feb 07 02:28:18 PM PST 24
Peak memory 922632 kb
Host smart-57359297-3105-4285-9cb3-1f89b276dce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918610816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1918610816
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3166389298
Short name T234
Test name
Test status
Simulation time 18214025107 ps
CPU time 211.74 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:29:36 PM PST 24
Peak memory 1251636 kb
Host smart-a5fe21eb-05f1-4cf2-a7db-b09a9e2bd209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166389298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3166389298
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3723615747
Short name T567
Test name
Test status
Simulation time 239317484 ps
CPU time 0.81 seconds
Started Feb 07 02:26:04 PM PST 24
Finished Feb 07 02:26:06 PM PST 24
Peak memory 203332 kb
Host smart-04fe5da2-1ecd-4faa-9d08-c686cb36a9ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723615747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3723615747
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2039285881
Short name T148
Test name
Test status
Simulation time 191679297 ps
CPU time 3.99 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:26:09 PM PST 24
Peak memory 203728 kb
Host smart-26ea740a-0ee8-4ef2-89cb-8a79d2a06eef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039285881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2039285881
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2309431496
Short name T1039
Test name
Test status
Simulation time 34046185068 ps
CPU time 431.21 seconds
Started Feb 07 02:26:01 PM PST 24
Finished Feb 07 02:33:13 PM PST 24
Peak memory 1936232 kb
Host smart-936a9b2e-b0da-49a0-8e98-5b817f8a2bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309431496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2309431496
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.892957196
Short name T1471
Test name
Test status
Simulation time 42147352705 ps
CPU time 61.1 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:27:13 PM PST 24
Peak memory 312424 kb
Host smart-1fa91855-4afa-47b3-a207-062b4561d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892957196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.892957196
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1376839611
Short name T814
Test name
Test status
Simulation time 46058637 ps
CPU time 0.63 seconds
Started Feb 07 02:26:04 PM PST 24
Finished Feb 07 02:26:06 PM PST 24
Peak memory 202564 kb
Host smart-f937c298-c825-4ed2-a5cf-37ab95fcbb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376839611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1376839611
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2980137108
Short name T1104
Test name
Test status
Simulation time 19221680157 ps
CPU time 248.24 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:30:13 PM PST 24
Peak memory 232580 kb
Host smart-aecaa25c-0e9c-4059-8595-7244be4d957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980137108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2980137108
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.3443506359
Short name T1015
Test name
Test status
Simulation time 12286953979 ps
CPU time 243.49 seconds
Started Feb 07 02:26:01 PM PST 24
Finished Feb 07 02:30:05 PM PST 24
Peak memory 317208 kb
Host smart-9daf4ac9-321e-4183-ba1f-834b9ea7c0ba
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443506359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample
.3443506359
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3042161603
Short name T826
Test name
Test status
Simulation time 1888038042 ps
CPU time 50.32 seconds
Started Feb 07 02:26:02 PM PST 24
Finished Feb 07 02:26:53 PM PST 24
Peak memory 264748 kb
Host smart-fcd65e37-63b7-4ab1-811c-cd5f5ca68b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042161603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3042161603
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3640124326
Short name T1152
Test name
Test status
Simulation time 3893355305 ps
CPU time 15.52 seconds
Started Feb 07 02:26:00 PM PST 24
Finished Feb 07 02:26:17 PM PST 24
Peak memory 218688 kb
Host smart-4fa48bcc-5afb-4300-a96d-c83761975c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640124326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3640124326
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3695448697
Short name T1417
Test name
Test status
Simulation time 854919716 ps
CPU time 3.56 seconds
Started Feb 07 02:26:09 PM PST 24
Finished Feb 07 02:26:13 PM PST 24
Peak memory 203608 kb
Host smart-584bb9ff-4de7-4f90-bd23-129090c681fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695448697 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3695448697
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3175901554
Short name T1544
Test name
Test status
Simulation time 10146719677 ps
CPU time 25.97 seconds
Started Feb 07 02:26:08 PM PST 24
Finished Feb 07 02:26:35 PM PST 24
Peak memory 370420 kb
Host smart-d080221b-7399-479a-b650-c50c378d953f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175901554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3175901554
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3895086211
Short name T564
Test name
Test status
Simulation time 10160251834 ps
CPU time 10.77 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:26:23 PM PST 24
Peak memory 314632 kb
Host smart-00d58d22-be40-4481-9627-02ecf5e4b593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895086211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3895086211
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.6969277
Short name T916
Test name
Test status
Simulation time 387812274 ps
CPU time 2.43 seconds
Started Feb 07 02:26:12 PM PST 24
Finished Feb 07 02:26:15 PM PST 24
Peak memory 203560 kb
Host smart-d8f46413-5517-4658-8c9c-3e14a947f046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6969277 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.i2c_target_hrst.6969277
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1420080339
Short name T789
Test name
Test status
Simulation time 1157495724 ps
CPU time 3 seconds
Started Feb 07 02:26:06 PM PST 24
Finished Feb 07 02:26:10 PM PST 24
Peak memory 203656 kb
Host smart-70c718ac-46ec-4c27-ad28-6993d29a006d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420080339 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1420080339
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.1883145365
Short name T1281
Test name
Test status
Simulation time 49882333368 ps
CPU time 671.56 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:37:17 PM PST 24
Peak memory 4900016 kb
Host smart-217402dc-780b-4f79-a8e5-74795d49c649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883145365 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1883145365
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.1765943131
Short name T1510
Test name
Test status
Simulation time 900257457 ps
CPU time 4.01 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:26:17 PM PST 24
Peak memory 206984 kb
Host smart-50ed52bf-db19-4575-86c9-25ada1a77218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765943131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.1765943131
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.354917743
Short name T944
Test name
Test status
Simulation time 2973389864 ps
CPU time 9.07 seconds
Started Feb 07 02:26:05 PM PST 24
Finished Feb 07 02:26:15 PM PST 24
Peak memory 203772 kb
Host smart-1177b3db-ef72-4d6d-946f-28a6fbe4e37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354917743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.354917743
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.3655733835
Short name T1458
Test name
Test status
Simulation time 46743111635 ps
CPU time 138.24 seconds
Started Feb 07 02:26:09 PM PST 24
Finished Feb 07 02:28:28 PM PST 24
Peak memory 335888 kb
Host smart-a6c9e234-203e-4c96-a19e-6b29a250f246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655733835 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.3655733835
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3040179187
Short name T100
Test name
Test status
Simulation time 2673966221 ps
CPU time 38.57 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:26:43 PM PST 24
Peak memory 234356 kb
Host smart-77149bc4-4ef4-44b9-a40b-8d5dd381b407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040179187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3040179187
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3171153572
Short name T1177
Test name
Test status
Simulation time 30327266127 ps
CPU time 22.76 seconds
Started Feb 07 02:26:02 PM PST 24
Finished Feb 07 02:26:25 PM PST 24
Peak memory 587900 kb
Host smart-cd5a8d27-8e42-4330-b56e-95d87b30da47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171153572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3171153572
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2094058175
Short name T1397
Test name
Test status
Simulation time 36708665037 ps
CPU time 151.03 seconds
Started Feb 07 02:26:03 PM PST 24
Finished Feb 07 02:28:36 PM PST 24
Peak memory 1330048 kb
Host smart-cc5c1ed4-59d6-4cd9-a7f6-0317342bacfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094058175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2094058175
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2864823846
Short name T1188
Test name
Test status
Simulation time 7373186842 ps
CPU time 7.12 seconds
Started Feb 07 02:26:02 PM PST 24
Finished Feb 07 02:26:10 PM PST 24
Peak memory 208376 kb
Host smart-0442dd35-f032-4a98-a796-3d71c080b7b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864823846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2864823846
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_ovf.1591448687
Short name T1318
Test name
Test status
Simulation time 2916104400 ps
CPU time 45.55 seconds
Started Feb 07 02:26:05 PM PST 24
Finished Feb 07 02:26:52 PM PST 24
Peak memory 225488 kb
Host smart-ee7f4ad3-e6b5-4caf-80ad-20743f8f159e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591448687 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_tx_ovf.1591448687
Directory /workspace/35.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.4158003912
Short name T214
Test name
Test status
Simulation time 1057533055 ps
CPU time 4.87 seconds
Started Feb 07 02:26:10 PM PST 24
Finished Feb 07 02:26:16 PM PST 24
Peak memory 206796 kb
Host smart-689d97d0-7bcf-41eb-b93e-99590cdade9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158003912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.4158003912
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.816321355
Short name T330
Test name
Test status
Simulation time 40886133 ps
CPU time 0.6 seconds
Started Feb 07 02:26:17 PM PST 24
Finished Feb 07 02:26:19 PM PST 24
Peak memory 202400 kb
Host smart-222f7d02-11b3-4e34-ad0f-61e3799c4a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816321355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.816321355
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.4195222918
Short name T1419
Test name
Test status
Simulation time 98750982 ps
CPU time 1.41 seconds
Started Feb 07 02:26:14 PM PST 24
Finished Feb 07 02:26:16 PM PST 24
Peak memory 214116 kb
Host smart-b3fa7e44-048d-4ad6-8657-4f541f7fc51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195222918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.4195222918
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.653532098
Short name T302
Test name
Test status
Simulation time 1655364298 ps
CPU time 22.13 seconds
Started Feb 07 02:26:08 PM PST 24
Finished Feb 07 02:26:31 PM PST 24
Peak memory 292900 kb
Host smart-ee3c8ec8-552b-486a-9d0d-5f00e6b94155
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653532098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.653532098
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2564929895
Short name T1292
Test name
Test status
Simulation time 10347058235 ps
CPU time 101.02 seconds
Started Feb 07 02:26:12 PM PST 24
Finished Feb 07 02:27:54 PM PST 24
Peak memory 875092 kb
Host smart-07d4d1d2-332f-400e-9801-488a75b89a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564929895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2564929895
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3233085611
Short name T451
Test name
Test status
Simulation time 6880351882 ps
CPU time 897.73 seconds
Started Feb 07 02:26:10 PM PST 24
Finished Feb 07 02:41:08 PM PST 24
Peak memory 1791168 kb
Host smart-0ab5b8e8-89ce-4984-8d15-91f87fd63c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233085611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3233085611
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1700903622
Short name T368
Test name
Test status
Simulation time 85763168 ps
CPU time 0.87 seconds
Started Feb 07 02:26:07 PM PST 24
Finished Feb 07 02:26:08 PM PST 24
Peak memory 203368 kb
Host smart-faa288f6-302a-411c-8322-49e1dea66d53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700903622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1700903622
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3781175260
Short name T777
Test name
Test status
Simulation time 739990239 ps
CPU time 12.13 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:26:24 PM PST 24
Peak memory 203512 kb
Host smart-cda8a6ff-395b-4d81-9d0b-095257ecbd7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781175260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3781175260
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.307736048
Short name T950
Test name
Test status
Simulation time 11673202644 ps
CPU time 289.89 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:31:02 PM PST 24
Peak memory 1633992 kb
Host smart-eb2c5ffd-e69f-4007-9b0e-ed748347946c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307736048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.307736048
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1233057691
Short name T640
Test name
Test status
Simulation time 7604535281 ps
CPU time 34.77 seconds
Started Feb 07 02:26:17 PM PST 24
Finished Feb 07 02:26:53 PM PST 24
Peak memory 248484 kb
Host smart-7a6e2825-905e-4715-a842-17f6e978a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233057691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1233057691
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.69023916
Short name T1410
Test name
Test status
Simulation time 37681173 ps
CPU time 0.62 seconds
Started Feb 07 02:26:09 PM PST 24
Finished Feb 07 02:26:11 PM PST 24
Peak memory 202572 kb
Host smart-f58998bf-b214-4cba-a3a4-6f814f5a92b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69023916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.69023916
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3862896701
Short name T1022
Test name
Test status
Simulation time 514171367 ps
CPU time 7.7 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:26:20 PM PST 24
Peak memory 211848 kb
Host smart-3a86e33a-183b-4ca8-8241-834f9dda7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862896701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3862896701
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.1050605814
Short name T620
Test name
Test status
Simulation time 2708122477 ps
CPU time 63.64 seconds
Started Feb 07 02:26:10 PM PST 24
Finished Feb 07 02:27:15 PM PST 24
Peak memory 317484 kb
Host smart-ca981d97-cf7b-4a65-bd74-deed4a88b007
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050605814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample
.1050605814
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.592426915
Short name T1063
Test name
Test status
Simulation time 1722178831 ps
CPU time 29.9 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:26:42 PM PST 24
Peak memory 232480 kb
Host smart-21e6afe5-b154-4bc1-a291-f54ca6278d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592426915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.592426915
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1496807035
Short name T132
Test name
Test status
Simulation time 148885501152 ps
CPU time 3201.56 seconds
Started Feb 07 02:26:13 PM PST 24
Finished Feb 07 03:19:36 PM PST 24
Peak memory 3842960 kb
Host smart-4c6a717b-ef0d-40ca-a836-c668582c88c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496807035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1496807035
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2369023621
Short name T691
Test name
Test status
Simulation time 17095118533 ps
CPU time 55.5 seconds
Started Feb 07 02:26:11 PM PST 24
Finished Feb 07 02:27:07 PM PST 24
Peak memory 220012 kb
Host smart-32262bd3-afcb-4199-b79e-76de437f54bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369023621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2369023621
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2329793326
Short name T1523
Test name
Test status
Simulation time 748853456 ps
CPU time 3.34 seconds
Started Feb 07 02:26:20 PM PST 24
Finished Feb 07 02:26:24 PM PST 24
Peak memory 203644 kb
Host smart-f2176c7f-a363-4c9e-9308-d4b0f5468f8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329793326 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2329793326
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.525494355
Short name T969
Test name
Test status
Simulation time 10145061179 ps
CPU time 10.95 seconds
Started Feb 07 02:26:20 PM PST 24
Finished Feb 07 02:26:32 PM PST 24
Peak memory 254872 kb
Host smart-ca375e97-3ede-436c-baa4-a8734ac7afea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525494355 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.525494355
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2138020156
Short name T1241
Test name
Test status
Simulation time 10340022117 ps
CPU time 13.63 seconds
Started Feb 07 02:26:20 PM PST 24
Finished Feb 07 02:26:34 PM PST 24
Peak memory 312500 kb
Host smart-fecac955-f0ed-4980-8394-29fcbb3af981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138020156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2138020156
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3682910426
Short name T1446
Test name
Test status
Simulation time 2061730672 ps
CPU time 2.54 seconds
Started Feb 07 02:26:18 PM PST 24
Finished Feb 07 02:26:21 PM PST 24
Peak memory 203680 kb
Host smart-9951b87c-3b58-4992-a2ac-e6b80111adf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682910426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3682910426
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3062732311
Short name T1198
Test name
Test status
Simulation time 679754281 ps
CPU time 3.09 seconds
Started Feb 07 02:26:12 PM PST 24
Finished Feb 07 02:26:16 PM PST 24
Peak memory 203620 kb
Host smart-7591b5a7-c93b-4e9d-92e2-524501b34d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062732311 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3062732311
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1063589562
Short name T677
Test name
Test status
Simulation time 13524514750 ps
CPU time 119.52 seconds
Started Feb 07 02:26:12 PM PST 24
Finished Feb 07 02:28:13 PM PST 24
Peak memory 1623884 kb
Host smart-41eab007-6aa7-4839-86a9-76d77a9260a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063589562 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1063589562
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.4093153336
Short name T1157
Test name
Test status
Simulation time 1095386658 ps
CPU time 3.18 seconds
Started Feb 07 02:26:17 PM PST 24
Finished Feb 07 02:26:22 PM PST 24
Peak memory 205624 kb
Host smart-2ae126b9-ede7-4226-b446-fdb31473de54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093153336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.4093153336
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1961242982
Short name T213
Test name
Test status
Simulation time 18481304450 ps
CPU time 43.34 seconds
Started Feb 07 02:26:12 PM PST 24
Finished Feb 07 02:26:56 PM PST 24
Peak memory 203764 kb
Host smart-7980082f-330f-4784-b0d6-60bcf20f21e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961242982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1961242982
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.3089724120
Short name T1150
Test name
Test status
Simulation time 38787882018 ps
CPU time 3112.57 seconds
Started Feb 07 02:26:17 PM PST 24
Finished Feb 07 03:18:10 PM PST 24
Peak memory 6057072 kb
Host smart-32ae07d4-0f3d-4dfb-92e9-d980210098a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089724120 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.3089724120
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2343369824
Short name T906
Test name
Test status
Simulation time 1605285498 ps
CPU time 28.99 seconds
Started Feb 07 02:26:13 PM PST 24
Finished Feb 07 02:26:43 PM PST 24
Peak memory 203616 kb
Host smart-8d079beb-1446-4eb8-9b05-8e50c8903fac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343369824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2343369824
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1786832405
Short name T975
Test name
Test status
Simulation time 38298648169 ps
CPU time 1792.1 seconds
Started Feb 07 02:26:12 PM PST 24
Finished Feb 07 02:56:05 PM PST 24
Peak memory 8685568 kb
Host smart-8fe46be1-7a5c-4ab1-b92a-8a0fcf5cb663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786832405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1786832405
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3453958104
Short name T555
Test name
Test status
Simulation time 25717130005 ps
CPU time 50.3 seconds
Started Feb 07 02:26:10 PM PST 24
Finished Feb 07 02:27:02 PM PST 24
Peak memory 602096 kb
Host smart-38423354-8410-47f0-992b-6f6aa6a8486d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453958104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3453958104
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1240904614
Short name T225
Test name
Test status
Simulation time 6601844855 ps
CPU time 7.8 seconds
Started Feb 07 02:26:21 PM PST 24
Finished Feb 07 02:26:30 PM PST 24
Peak memory 208316 kb
Host smart-f7d61abf-2d7e-4d36-9690-46a87314b8c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240904614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1240904614
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_ovf.146267754
Short name T1196
Test name
Test status
Simulation time 10297159466 ps
CPU time 67.43 seconds
Started Feb 07 02:26:19 PM PST 24
Finished Feb 07 02:27:27 PM PST 24
Peak memory 295880 kb
Host smart-93cc5301-df85-48dd-94c1-6ecfd6d01b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146267754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_tx_ovf.146267754
Directory /workspace/36.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.1917785876
Short name T1289
Test name
Test status
Simulation time 2124432505 ps
CPU time 5.79 seconds
Started Feb 07 02:26:17 PM PST 24
Finished Feb 07 02:26:24 PM PST 24
Peak memory 204212 kb
Host smart-bdcdc57f-c08a-4f1f-93dd-da74263d0ac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917785876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.1917785876
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2467013171
Short name T1204
Test name
Test status
Simulation time 16022904 ps
CPU time 0.61 seconds
Started Feb 07 02:26:39 PM PST 24
Finished Feb 07 02:26:40 PM PST 24
Peak memory 203268 kb
Host smart-517a0ee8-0ed4-4282-a368-097b7731ca91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467013171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2467013171
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3749509462
Short name T1447
Test name
Test status
Simulation time 63921414 ps
CPU time 1.07 seconds
Started Feb 07 02:26:27 PM PST 24
Finished Feb 07 02:26:28 PM PST 24
Peak memory 219952 kb
Host smart-c449ab93-9b3a-4824-bf05-17d06d6c21d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749509462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3749509462
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.496437700
Short name T1377
Test name
Test status
Simulation time 1111219095 ps
CPU time 30.85 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:27:01 PM PST 24
Peak memory 331708 kb
Host smart-8c0a6274-7a33-49cc-b2b5-ea26023dd27d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496437700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.496437700
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.427372034
Short name T1405
Test name
Test status
Simulation time 32797105281 ps
CPU time 123.17 seconds
Started Feb 07 02:26:28 PM PST 24
Finished Feb 07 02:28:32 PM PST 24
Peak memory 508600 kb
Host smart-def664fc-ab33-44a3-a361-8c0993cccef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427372034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.427372034
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2754479200
Short name T422
Test name
Test status
Simulation time 26106984115 ps
CPU time 332.07 seconds
Started Feb 07 02:26:28 PM PST 24
Finished Feb 07 02:32:01 PM PST 24
Peak memory 1486748 kb
Host smart-bdc3c67f-32cf-490a-baf4-02020a60bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754479200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2754479200
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1734460537
Short name T1366
Test name
Test status
Simulation time 234353907 ps
CPU time 0.96 seconds
Started Feb 07 02:26:26 PM PST 24
Finished Feb 07 02:26:27 PM PST 24
Peak memory 203580 kb
Host smart-e76a0b79-f405-4178-b7e7-b1d4d673a2b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734460537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1734460537
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.375744521
Short name T1306
Test name
Test status
Simulation time 690674113 ps
CPU time 4.58 seconds
Started Feb 07 02:26:26 PM PST 24
Finished Feb 07 02:26:31 PM PST 24
Peak memory 234540 kb
Host smart-d3d82fc5-6cae-44dd-b7d2-89bfc87edeab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375744521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
375744521
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1042419199
Short name T180
Test name
Test status
Simulation time 4949653240 ps
CPU time 233.52 seconds
Started Feb 07 02:26:26 PM PST 24
Finished Feb 07 02:30:20 PM PST 24
Peak memory 1337796 kb
Host smart-73e7f11f-6e48-48f2-be57-126e7d4ee0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042419199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1042419199
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3967743498
Short name T787
Test name
Test status
Simulation time 4071597871 ps
CPU time 97.23 seconds
Started Feb 07 02:26:44 PM PST 24
Finished Feb 07 02:28:22 PM PST 24
Peak memory 233140 kb
Host smart-78360e0e-b1ae-4d0f-942b-d7fff0b374b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967743498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3967743498
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.4232041639
Short name T5
Test name
Test status
Simulation time 16985037 ps
CPU time 0.68 seconds
Started Feb 07 02:26:19 PM PST 24
Finished Feb 07 02:26:21 PM PST 24
Peak memory 202576 kb
Host smart-236a39b4-5796-4ef5-8c1b-0dcdccbe697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232041639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4232041639
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.960102901
Short name T223
Test name
Test status
Simulation time 13556765562 ps
CPU time 399.65 seconds
Started Feb 07 02:26:27 PM PST 24
Finished Feb 07 02:33:07 PM PST 24
Peak memory 453952 kb
Host smart-8317fd7a-eb1b-4508-8a59-d72cc02ef6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960102901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.960102901
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.2656004366
Short name T642
Test name
Test status
Simulation time 6654747572 ps
CPU time 41.37 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:27:11 PM PST 24
Peak memory 284384 kb
Host smart-bddf1780-9ee8-4fd7-828b-cad2d400d1f3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656004366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample
.2656004366
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3630502131
Short name T718
Test name
Test status
Simulation time 6158927101 ps
CPU time 77.68 seconds
Started Feb 07 02:26:18 PM PST 24
Finished Feb 07 02:27:37 PM PST 24
Peak memory 232496 kb
Host smart-a2df4c44-524c-457a-8287-2005f0880471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630502131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3630502131
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.778970662
Short name T151
Test name
Test status
Simulation time 26427284210 ps
CPU time 916.26 seconds
Started Feb 07 02:26:27 PM PST 24
Finished Feb 07 02:41:44 PM PST 24
Peak memory 857572 kb
Host smart-5f123a47-1639-41b2-81f8-35cde7252c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778970662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.778970662
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.351851528
Short name T699
Test name
Test status
Simulation time 1069515066 ps
CPU time 18.76 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:26:48 PM PST 24
Peak memory 214160 kb
Host smart-e5da7d74-0cc5-48ff-9d4f-716007958093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351851528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.351851528
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2646562203
Short name T693
Test name
Test status
Simulation time 10004194826 ps
CPU time 5.08 seconds
Started Feb 07 02:26:44 PM PST 24
Finished Feb 07 02:26:50 PM PST 24
Peak memory 203672 kb
Host smart-54c7d3e2-e3fd-4186-985a-ed56350322d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646562203 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2646562203
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3585162020
Short name T1239
Test name
Test status
Simulation time 10138802070 ps
CPU time 11.95 seconds
Started Feb 07 02:26:27 PM PST 24
Finished Feb 07 02:26:40 PM PST 24
Peak memory 266348 kb
Host smart-58e37c45-375f-4ca5-b891-43ce33bca581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585162020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3585162020
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3188723887
Short name T1170
Test name
Test status
Simulation time 10269791653 ps
CPU time 28.53 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:26:58 PM PST 24
Peak memory 452072 kb
Host smart-37d5639d-706d-4f31-9059-c293c10a1c22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188723887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3188723887
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3691472521
Short name T1251
Test name
Test status
Simulation time 490187013 ps
CPU time 2.49 seconds
Started Feb 07 02:26:38 PM PST 24
Finished Feb 07 02:26:41 PM PST 24
Peak memory 203632 kb
Host smart-9a0da2fc-7493-4c0f-a72a-a625ecf5a174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691472521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3691472521
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1178148393
Short name T930
Test name
Test status
Simulation time 1213226940 ps
CPU time 4.99 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:26:34 PM PST 24
Peak memory 203560 kb
Host smart-4bfda5e5-a5d9-4c6f-8ac3-a47ea7e22e45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178148393 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1178148393
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1666217540
Short name T1207
Test name
Test status
Simulation time 12221020517 ps
CPU time 18.21 seconds
Started Feb 07 02:26:28 PM PST 24
Finished Feb 07 02:26:47 PM PST 24
Peak memory 597836 kb
Host smart-ce6619de-feca-4a71-b4f5-90729fa8ba0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666217540 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1666217540
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.1753328553
Short name T282
Test name
Test status
Simulation time 3706207508 ps
CPU time 4.36 seconds
Started Feb 07 02:26:38 PM PST 24
Finished Feb 07 02:26:43 PM PST 24
Peak memory 212676 kb
Host smart-b0727ffd-e949-46d6-8cb9-2d87aab010b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753328553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.1753328553
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3360993629
Short name T455
Test name
Test status
Simulation time 1264635770 ps
CPU time 12.67 seconds
Started Feb 07 02:26:26 PM PST 24
Finished Feb 07 02:26:39 PM PST 24
Peak memory 203664 kb
Host smart-412a870d-5083-43c1-ab37-bdf457e8361b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360993629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3360993629
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.3922341444
Short name T501
Test name
Test status
Simulation time 48314257716 ps
CPU time 185.85 seconds
Started Feb 07 02:26:34 PM PST 24
Finished Feb 07 02:29:41 PM PST 24
Peak memory 1939264 kb
Host smart-e26a9296-47cd-4423-b51f-9ab07b812fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922341444 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.3922341444
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1234981915
Short name T1160
Test name
Test status
Simulation time 44751641400 ps
CPU time 94.16 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:28:04 PM PST 24
Peak memory 209872 kb
Host smart-a40f0979-1747-471b-98f2-9ce21df38c6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234981915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1234981915
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1399765799
Short name T992
Test name
Test status
Simulation time 46464494975 ps
CPU time 3072.22 seconds
Started Feb 07 02:26:25 PM PST 24
Finished Feb 07 03:17:39 PM PST 24
Peak memory 10526076 kb
Host smart-a75c3b56-6c72-41c5-9460-a9f0cbf42f6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399765799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1399765799
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.756708613
Short name T1143
Test name
Test status
Simulation time 32725358803 ps
CPU time 240.96 seconds
Started Feb 07 02:26:28 PM PST 24
Finished Feb 07 02:30:29 PM PST 24
Peak memory 1941608 kb
Host smart-893dc37a-0a81-4f94-bfe8-5cf06968a7e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756708613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.756708613
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.431086513
Short name T1450
Test name
Test status
Simulation time 8444747452 ps
CPU time 7.68 seconds
Started Feb 07 02:26:32 PM PST 24
Finished Feb 07 02:26:41 PM PST 24
Peak memory 208484 kb
Host smart-15ef63d8-7879-4c00-953b-11f8e212321c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431086513 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.431086513
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_ovf.1155348066
Short name T1517
Test name
Test status
Simulation time 10560720698 ps
CPU time 39.39 seconds
Started Feb 07 02:26:29 PM PST 24
Finished Feb 07 02:27:09 PM PST 24
Peak memory 220240 kb
Host smart-ec018b26-7c07-4101-8a14-b99470b89d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155348066 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_tx_ovf.1155348066
Directory /workspace/37.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.3521116790
Short name T405
Test name
Test status
Simulation time 12771279774 ps
CPU time 7 seconds
Started Feb 07 02:26:26 PM PST 24
Finished Feb 07 02:26:33 PM PST 24
Peak memory 204680 kb
Host smart-37334f82-1f96-4d1e-bf4d-316ce917c364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521116790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.3521116790
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.42403830
Short name T953
Test name
Test status
Simulation time 55095231 ps
CPU time 0.65 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:26:57 PM PST 24
Peak memory 202376 kb
Host smart-31cd87e9-3589-4117-a3d9-2bfd1eb2fa14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.42403830
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.50586088
Short name T66
Test name
Test status
Simulation time 24627073 ps
CPU time 1.07 seconds
Started Feb 07 02:26:48 PM PST 24
Finished Feb 07 02:26:50 PM PST 24
Peak memory 203648 kb
Host smart-bffca848-1131-4fe9-9472-dddc201bc92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50586088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.50586088
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1532620563
Short name T1108
Test name
Test status
Simulation time 798949961 ps
CPU time 11.12 seconds
Started Feb 07 02:26:50 PM PST 24
Finished Feb 07 02:27:02 PM PST 24
Peak memory 243856 kb
Host smart-801efabe-0dac-4c8d-b1ee-8c13c6942acb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532620563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1532620563
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3427593065
Short name T1179
Test name
Test status
Simulation time 61753299470 ps
CPU time 253.17 seconds
Started Feb 07 02:26:47 PM PST 24
Finished Feb 07 02:31:01 PM PST 24
Peak memory 974232 kb
Host smart-49a4bb9d-1d31-45e6-aacb-47fa318394ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427593065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3427593065
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.4084875598
Short name T352
Test name
Test status
Simulation time 3584573340 ps
CPU time 165.51 seconds
Started Feb 07 02:26:47 PM PST 24
Finished Feb 07 02:29:33 PM PST 24
Peak memory 1040036 kb
Host smart-935283df-f2ec-40b7-98d3-fe0a3ab511bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084875598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.4084875598
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2439950814
Short name T383
Test name
Test status
Simulation time 254993169 ps
CPU time 0.77 seconds
Started Feb 07 02:26:48 PM PST 24
Finished Feb 07 02:26:49 PM PST 24
Peak memory 203380 kb
Host smart-f3db4a44-299e-41ad-9166-ce4823682fed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439950814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2439950814
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2661487294
Short name T1166
Test name
Test status
Simulation time 234915859 ps
CPU time 13.01 seconds
Started Feb 07 02:26:48 PM PST 24
Finished Feb 07 02:27:01 PM PST 24
Peak memory 250436 kb
Host smart-64c22679-b15d-4b8c-a0a2-e029116191f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661487294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2661487294
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.189072141
Short name T239
Test name
Test status
Simulation time 7038260072 ps
CPU time 584.47 seconds
Started Feb 07 02:26:49 PM PST 24
Finished Feb 07 02:36:34 PM PST 24
Peak memory 1496544 kb
Host smart-21e153d4-0bfa-4c4f-9e2d-ee5551f25b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189072141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.189072141
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.133308625
Short name T1199
Test name
Test status
Simulation time 4133911662 ps
CPU time 47.44 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:27:44 PM PST 24
Peak memory 262060 kb
Host smart-ba83c56d-a56d-4a23-841d-5b051dfa05d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133308625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.133308625
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1578639019
Short name T1140
Test name
Test status
Simulation time 17981759 ps
CPU time 0.63 seconds
Started Feb 07 02:26:38 PM PST 24
Finished Feb 07 02:26:39 PM PST 24
Peak memory 202576 kb
Host smart-41813aa8-d9d5-4588-b052-3272583065ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578639019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1578639019
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3618446603
Short name T675
Test name
Test status
Simulation time 8724431983 ps
CPU time 59.54 seconds
Started Feb 07 02:26:47 PM PST 24
Finished Feb 07 02:27:48 PM PST 24
Peak memory 220180 kb
Host smart-ade843fe-8be8-4d50-9b1a-d00978586af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618446603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3618446603
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.936614278
Short name T816
Test name
Test status
Simulation time 8062971364 ps
CPU time 100.62 seconds
Started Feb 07 02:26:48 PM PST 24
Finished Feb 07 02:28:29 PM PST 24
Peak memory 299900 kb
Host smart-501e280c-1152-4353-99e1-704f64964ca8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936614278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample.
936614278
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3979717876
Short name T348
Test name
Test status
Simulation time 9438598323 ps
CPU time 131.07 seconds
Started Feb 07 02:26:36 PM PST 24
Finished Feb 07 02:28:48 PM PST 24
Peak memory 251172 kb
Host smart-df0b0e95-f800-4475-af0b-efab557853fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979717876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3979717876
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.764829912
Short name T714
Test name
Test status
Simulation time 987113505 ps
CPU time 42.94 seconds
Started Feb 07 02:26:53 PM PST 24
Finished Feb 07 02:27:36 PM PST 24
Peak memory 219936 kb
Host smart-d0d1b867-cb27-4691-877f-c82f0578a82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764829912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.764829912
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1516067595
Short name T1321
Test name
Test status
Simulation time 4439622492 ps
CPU time 4.79 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:27:03 PM PST 24
Peak memory 203764 kb
Host smart-aef7c923-bdc5-456c-9863-16b5c2c86685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516067595 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1516067595
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3396393056
Short name T1508
Test name
Test status
Simulation time 10030396588 ps
CPU time 48.91 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:27:47 PM PST 24
Peak memory 464844 kb
Host smart-1f53edff-a1c0-4466-8a4c-12c113cad9ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396393056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3396393056
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1637769100
Short name T511
Test name
Test status
Simulation time 10332944855 ps
CPU time 28.16 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 02:27:28 PM PST 24
Peak memory 409648 kb
Host smart-08ae00c2-db03-4d94-8e1c-1a1284513880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637769100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1637769100
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.592477866
Short name T167
Test name
Test status
Simulation time 2376346877 ps
CPU time 2.95 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 02:27:02 PM PST 24
Peak memory 203772 kb
Host smart-155fdb9a-d52d-4c9e-a018-63901e694469
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592477866 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.592477866
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1877614500
Short name T743
Test name
Test status
Simulation time 17949100363 ps
CPU time 3.72 seconds
Started Feb 07 02:26:46 PM PST 24
Finished Feb 07 02:26:51 PM PST 24
Peak memory 203756 kb
Host smart-d7c3c02e-e2a5-48f6-b2fb-7cf22ac5de10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877614500 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1877614500
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2475020489
Short name T621
Test name
Test status
Simulation time 10972297765 ps
CPU time 218.88 seconds
Started Feb 07 02:26:48 PM PST 24
Finished Feb 07 02:30:28 PM PST 24
Peak memory 2388632 kb
Host smart-a066d73b-a0ad-432b-89e4-eb40ae33fa10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475020489 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2475020489
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1715108971
Short name T424
Test name
Test status
Simulation time 430745440 ps
CPU time 2.73 seconds
Started Feb 07 02:27:03 PM PST 24
Finished Feb 07 02:27:07 PM PST 24
Peak memory 203604 kb
Host smart-bde48c84-ff76-4dac-a0c3-9b09da5021f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715108971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1715108971
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2475258634
Short name T549
Test name
Test status
Simulation time 1770223370 ps
CPU time 6.12 seconds
Started Feb 07 02:26:50 PM PST 24
Finished Feb 07 02:26:57 PM PST 24
Peak memory 203640 kb
Host smart-d250eef6-bc2c-4c21-b740-7335d7ed9164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475258634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2475258634
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.340592706
Short name T161
Test name
Test status
Simulation time 61021096161 ps
CPU time 1117.68 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:45:34 PM PST 24
Peak memory 6038316 kb
Host smart-7a2e4b5a-f2b6-414d-b072-19dcc2e67ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340592706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_stress_all.340592706
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3419978591
Short name T729
Test name
Test status
Simulation time 1427428971 ps
CPU time 57.14 seconds
Started Feb 07 02:26:47 PM PST 24
Finished Feb 07 02:27:45 PM PST 24
Peak memory 203572 kb
Host smart-b0aaf4a9-fbf9-4e5b-9f0b-649d6075c4fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419978591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3419978591
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2676461636
Short name T763
Test name
Test status
Simulation time 41741779835 ps
CPU time 203.83 seconds
Started Feb 07 02:26:47 PM PST 24
Finished Feb 07 02:30:11 PM PST 24
Peak memory 2232316 kb
Host smart-d0e5b66f-a329-4029-a4e7-7fbc62c2f65c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676461636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2676461636
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3313740249
Short name T292
Test name
Test status
Simulation time 36508945243 ps
CPU time 2548.38 seconds
Started Feb 07 02:26:49 PM PST 24
Finished Feb 07 03:09:19 PM PST 24
Peak memory 3877164 kb
Host smart-e5dcd876-a3df-4620-8910-1b3d63133bcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313740249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3313740249
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1379965808
Short name T270
Test name
Test status
Simulation time 1326663652 ps
CPU time 6.95 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:27:03 PM PST 24
Peak memory 209328 kb
Host smart-270f11af-5aeb-4c24-be94-646939972610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379965808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1379965808
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_ovf.477855789
Short name T859
Test name
Test status
Simulation time 3569487704 ps
CPU time 77 seconds
Started Feb 07 02:26:49 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 314840 kb
Host smart-7ea760f4-2a50-419d-8a7c-c8845c760b87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477855789 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_tx_ovf.477855789
Directory /workspace/38.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.779075993
Short name T914
Test name
Test status
Simulation time 5275091981 ps
CPU time 7.57 seconds
Started Feb 07 02:27:02 PM PST 24
Finished Feb 07 02:27:10 PM PST 24
Peak memory 203752 kb
Host smart-8993f9cb-b3ba-4e8a-8384-6316b809441d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779075993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_unexp_stop.779075993
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1979769946
Short name T504
Test name
Test status
Simulation time 21625691 ps
CPU time 0.58 seconds
Started Feb 07 02:27:18 PM PST 24
Finished Feb 07 02:27:19 PM PST 24
Peak memory 202420 kb
Host smart-72613c16-5197-4bea-b283-725ae31c2e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979769946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1979769946
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3481742492
Short name T737
Test name
Test status
Simulation time 49866249 ps
CPU time 1.15 seconds
Started Feb 07 02:26:58 PM PST 24
Finished Feb 07 02:26:59 PM PST 24
Peak memory 219988 kb
Host smart-a72f3d06-e33d-4312-9292-60dc8f70ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481742492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3481742492
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1636202062
Short name T354
Test name
Test status
Simulation time 1469806936 ps
CPU time 6.27 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:27:03 PM PST 24
Peak memory 263776 kb
Host smart-f851d20a-abcd-4b3c-947b-a18d976f4e3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636202062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1636202062
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2368309429
Short name T1178
Test name
Test status
Simulation time 29131307004 ps
CPU time 179.68 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:29:56 PM PST 24
Peak memory 799024 kb
Host smart-57d7e256-c2fe-450d-8ca7-a4f9689a8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368309429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2368309429
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2960460558
Short name T323
Test name
Test status
Simulation time 5430279587 ps
CPU time 681.66 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:38:19 PM PST 24
Peak memory 1532108 kb
Host smart-8f308f92-db46-4117-81c1-eb7ad69bc7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960460558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2960460558
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.961316900
Short name T1001
Test name
Test status
Simulation time 203968548 ps
CPU time 0.9 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:26:58 PM PST 24
Peak memory 203552 kb
Host smart-1e4003ab-e723-44aa-8744-eba4e8d3198c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961316900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.961316900
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2686368052
Short name T1139
Test name
Test status
Simulation time 279266315 ps
CPU time 14.25 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 02:27:14 PM PST 24
Peak memory 203692 kb
Host smart-cae0684c-577f-4986-8593-552cab9e428f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686368052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2686368052
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1847679316
Short name T858
Test name
Test status
Simulation time 13844372834 ps
CPU time 448.84 seconds
Started Feb 07 02:26:58 PM PST 24
Finished Feb 07 02:34:28 PM PST 24
Peak memory 1893780 kb
Host smart-3aeaa101-c3b6-4fbf-9859-12cc9a8a9be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847679316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1847679316
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.4283205018
Short name T1019
Test name
Test status
Simulation time 2725673508 ps
CPU time 144.34 seconds
Started Feb 07 02:27:09 PM PST 24
Finished Feb 07 02:29:34 PM PST 24
Peak memory 235440 kb
Host smart-fa67506a-00a2-424f-810b-b12568824620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283205018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.4283205018
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.3238765153
Short name T1389
Test name
Test status
Simulation time 96280882 ps
CPU time 0.62 seconds
Started Feb 07 02:26:56 PM PST 24
Finished Feb 07 02:26:57 PM PST 24
Peak memory 202568 kb
Host smart-fe369e77-2836-47dc-8145-17e974c43274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238765153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3238765153
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3544298937
Short name T713
Test name
Test status
Simulation time 26513916218 ps
CPU time 236.18 seconds
Started Feb 07 02:26:55 PM PST 24
Finished Feb 07 02:30:52 PM PST 24
Peak memory 203772 kb
Host smart-798a9a0d-45b0-4ba5-884d-b13a46fe9670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544298937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3544298937
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.2481926301
Short name T1263
Test name
Test status
Simulation time 5680478102 ps
CPU time 193.53 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:30:12 PM PST 24
Peak memory 403104 kb
Host smart-ab49e12e-b2f9-484c-8e9f-17891f07759f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481926301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample
.2481926301
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1667180870
Short name T450
Test name
Test status
Simulation time 2709396688 ps
CPU time 70.29 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:28:08 PM PST 24
Peak memory 285064 kb
Host smart-a1c2a723-47b6-4f39-b8e9-db58af11c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667180870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1667180870
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.17436028
Short name T140
Test name
Test status
Simulation time 153090188109 ps
CPU time 2439.65 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 03:07:40 PM PST 24
Peak memory 3509656 kb
Host smart-5922db6b-8114-4794-ae75-f2a5f5676cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17436028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.17436028
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.4173773364
Short name T1347
Test name
Test status
Simulation time 1102663001 ps
CPU time 47.13 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 02:27:47 PM PST 24
Peak memory 211900 kb
Host smart-2b8bbaa4-d727-445f-a93a-486913fd7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173773364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.4173773364
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1423473173
Short name T1353
Test name
Test status
Simulation time 3126986039 ps
CPU time 5.23 seconds
Started Feb 07 02:27:09 PM PST 24
Finished Feb 07 02:27:15 PM PST 24
Peak memory 203756 kb
Host smart-5978b578-cce9-49cc-bcc3-5532117dab93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423473173 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1423473173
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1976340637
Short name T1049
Test name
Test status
Simulation time 10094256690 ps
CPU time 46.56 seconds
Started Feb 07 02:27:07 PM PST 24
Finished Feb 07 02:27:54 PM PST 24
Peak memory 445088 kb
Host smart-dc2a88d8-f001-40ae-9258-f79bf899ad69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976340637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1976340637
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1189852966
Short name T242
Test name
Test status
Simulation time 10042120082 ps
CPU time 69.26 seconds
Started Feb 07 02:27:10 PM PST 24
Finished Feb 07 02:28:20 PM PST 24
Peak memory 608844 kb
Host smart-b0b1acf4-6daa-409a-b5d1-772441b0cd73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189852966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1189852966
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1525051501
Short name T1506
Test name
Test status
Simulation time 495742642 ps
CPU time 2.66 seconds
Started Feb 07 02:27:09 PM PST 24
Finished Feb 07 02:27:12 PM PST 24
Peak memory 203624 kb
Host smart-5197c502-c7bc-4fd8-b350-a02c2eacae9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525051501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1525051501
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.109238043
Short name T1448
Test name
Test status
Simulation time 1431577622 ps
CPU time 5.64 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:27:03 PM PST 24
Peak memory 204412 kb
Host smart-5de45e51-ff18-4c89-8930-1b96ad3558ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109238043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.109238043
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2710596490
Short name T490
Test name
Test status
Simulation time 5226594868 ps
CPU time 24.93 seconds
Started Feb 07 02:27:09 PM PST 24
Finished Feb 07 02:27:35 PM PST 24
Peak memory 641048 kb
Host smart-68977899-b081-4d8e-acda-a6f649b4268e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710596490 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2710596490
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.4282413625
Short name T1267
Test name
Test status
Simulation time 3768131741 ps
CPU time 4.45 seconds
Started Feb 07 02:27:09 PM PST 24
Finished Feb 07 02:27:14 PM PST 24
Peak memory 203716 kb
Host smart-52de6587-138a-4243-b116-4d06c66e10e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282413625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.4282413625
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2570787378
Short name T1067
Test name
Test status
Simulation time 15006486882 ps
CPU time 9.87 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 02:27:10 PM PST 24
Peak memory 203708 kb
Host smart-c58b5f74-f6e9-4bf1-96a8-45dbb2684abb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570787378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2570787378
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.4228146202
Short name T1246
Test name
Test status
Simulation time 391615622 ps
CPU time 16.35 seconds
Started Feb 07 02:26:57 PM PST 24
Finished Feb 07 02:27:14 PM PST 24
Peak memory 203612 kb
Host smart-ee565e9f-148d-46c0-881f-bf4a87179064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228146202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.4228146202
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.4098919936
Short name T774
Test name
Test status
Simulation time 36434056744 ps
CPU time 1554.14 seconds
Started Feb 07 02:26:59 PM PST 24
Finished Feb 07 02:52:54 PM PST 24
Peak memory 8267084 kb
Host smart-7f6d69d5-5116-45ce-9c15-baf731f2cd08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098919936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.4098919936
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1055409035
Short name T233
Test name
Test status
Simulation time 8973300035 ps
CPU time 517.85 seconds
Started Feb 07 02:26:58 PM PST 24
Finished Feb 07 02:35:36 PM PST 24
Peak memory 1671792 kb
Host smart-03c50cd6-188b-4cb6-8d80-034a14b4ea99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055409035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1055409035
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2158906904
Short name T536
Test name
Test status
Simulation time 1710880623 ps
CPU time 6.96 seconds
Started Feb 07 02:27:13 PM PST 24
Finished Feb 07 02:27:20 PM PST 24
Peak memory 203652 kb
Host smart-9080f8d7-35f3-4160-a5c9-ea6606c474a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158906904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2158906904
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_ovf.1328041071
Short name T756
Test name
Test status
Simulation time 2212131053 ps
CPU time 33.83 seconds
Started Feb 07 02:27:08 PM PST 24
Finished Feb 07 02:27:42 PM PST 24
Peak memory 212812 kb
Host smart-e6430d3d-9de5-4fe4-b470-2144327ffc8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328041071 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_tx_ovf.1328041071
Directory /workspace/39.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.4214201524
Short name T672
Test name
Test status
Simulation time 999255306 ps
CPU time 6.2 seconds
Started Feb 07 02:27:08 PM PST 24
Finished Feb 07 02:27:14 PM PST 24
Peak memory 203584 kb
Host smart-ca4c069d-1cea-446c-84e4-175d44666359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214201524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.4214201524
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2232580523
Short name T1217
Test name
Test status
Simulation time 50888118 ps
CPU time 0.59 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:22 PM PST 24
Peak memory 202380 kb
Host smart-f2687987-a940-43fa-8a4f-f47fa204837f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232580523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2232580523
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1035288544
Short name T739
Test name
Test status
Simulation time 36198207 ps
CPU time 1.04 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 203312 kb
Host smart-03ff14f0-d0c2-44ec-b0c8-84603db69107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035288544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1035288544
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.621642711
Short name T1073
Test name
Test status
Simulation time 575550360 ps
CPU time 15.74 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:19:30 PM PST 24
Peak memory 263920 kb
Host smart-def17d16-4883-4eaa-82af-f2412870bf16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621642711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.621642711
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2930274132
Short name T1109
Test name
Test status
Simulation time 3608793266 ps
CPU time 162.92 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:22:02 PM PST 24
Peak memory 1103508 kb
Host smart-0171312c-b61f-4956-9349-eec00d095647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930274132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2930274132
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.132062114
Short name T823
Test name
Test status
Simulation time 5801218708 ps
CPU time 355.16 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:25:09 PM PST 24
Peak memory 1609912 kb
Host smart-3fd8e850-b2da-417a-854d-d866699b007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132062114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.132062114
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.787440269
Short name T1301
Test name
Test status
Simulation time 101266901 ps
CPU time 1.01 seconds
Started Feb 07 02:19:11 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 203636 kb
Host smart-b74fc942-f262-42a2-ae92-47716c36d650
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787440269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.787440269
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2168236012
Short name T1208
Test name
Test status
Simulation time 951065226 ps
CPU time 10 seconds
Started Feb 07 02:19:14 PM PST 24
Finished Feb 07 02:19:27 PM PST 24
Peak memory 203548 kb
Host smart-bf13e359-de14-4bba-9789-2c4ef5cae361
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168236012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2168236012
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3002879469
Short name T1122
Test name
Test status
Simulation time 12398667566 ps
CPU time 304.25 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:24:19 PM PST 24
Peak memory 1699968 kb
Host smart-2e8ec312-fe98-4cc7-abee-3750126b1f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002879469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3002879469
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.162158176
Short name T846
Test name
Test status
Simulation time 39997372192 ps
CPU time 164.92 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:22:03 PM PST 24
Peak memory 260444 kb
Host smart-71585a79-1411-4c20-9bb3-4bdad8f30b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162158176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.162158176
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3659812358
Short name T4
Test name
Test status
Simulation time 46236430 ps
CPU time 0.62 seconds
Started Feb 07 02:19:09 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 202580 kb
Host smart-fa823264-2063-4d37-858c-605e11b0cfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659812358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3659812358
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2400163705
Short name T1256
Test name
Test status
Simulation time 2752880339 ps
CPU time 62.68 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:20:17 PM PST 24
Peak memory 281192 kb
Host smart-93ce1b27-bd1f-4f27-b55f-67d03d4ea433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400163705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2400163705
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.1550684284
Short name T535
Test name
Test status
Simulation time 5753482884 ps
CPU time 106.22 seconds
Started Feb 07 02:19:14 PM PST 24
Finished Feb 07 02:21:03 PM PST 24
Peak memory 260816 kb
Host smart-73aef34d-0f35-4784-9f46-03792bd11248
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550684284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.
1550684284
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1212028407
Short name T993
Test name
Test status
Simulation time 1319672699 ps
CPU time 30.78 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:19:45 PM PST 24
Peak memory 245484 kb
Host smart-1383149b-ad07-4781-a84a-8375acac6f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212028407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1212028407
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3724115230
Short name T179
Test name
Test status
Simulation time 18314637965 ps
CPU time 120.1 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:21:14 PM PST 24
Peak memory 340116 kb
Host smart-75571c76-6907-421d-96a7-2650ffb213d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724115230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3724115230
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.757543533
Short name T438
Test name
Test status
Simulation time 4635783790 ps
CPU time 53.95 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:20:08 PM PST 24
Peak memory 211932 kb
Host smart-60ac6df3-1612-4859-b8a7-61c4ece2c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757543533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.757543533
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3014187570
Short name T71
Test name
Test status
Simulation time 603893827 ps
CPU time 0.97 seconds
Started Feb 07 02:19:14 PM PST 24
Finished Feb 07 02:19:17 PM PST 24
Peak memory 220612 kb
Host smart-2f901647-8cc6-4525-9771-130aa725a387
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014187570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3014187570
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1604354859
Short name T719
Test name
Test status
Simulation time 1599268156 ps
CPU time 6.06 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:19:21 PM PST 24
Peak memory 203588 kb
Host smart-fdd3cfaf-25dc-4215-b60a-59664bda9abb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604354859 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1604354859
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3916166766
Short name T1262
Test name
Test status
Simulation time 10287843001 ps
CPU time 10.56 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:19:29 PM PST 24
Peak memory 242900 kb
Host smart-620e2958-8fb8-4c47-a3c2-46beddc82a0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916166766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3916166766
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.400331101
Short name T1361
Test name
Test status
Simulation time 10212050993 ps
CPU time 10.34 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 283692 kb
Host smart-24ef3f8f-b9bb-41ae-a9be-e9bf948754fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400331101 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.400331101
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1127278188
Short name T1526
Test name
Test status
Simulation time 1245935652 ps
CPU time 2.13 seconds
Started Feb 07 02:19:14 PM PST 24
Finished Feb 07 02:19:19 PM PST 24
Peak memory 203592 kb
Host smart-1e6315fb-2dda-478f-8b36-a434d3a46946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127278188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1127278188
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.4278069504
Short name T1449
Test name
Test status
Simulation time 11002183313 ps
CPU time 3.89 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:19:18 PM PST 24
Peak memory 203756 kb
Host smart-e8bb613d-fc7c-44ef-b3ae-337cd0ad3b47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278069504 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.4278069504
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.654142802
Short name T219
Test name
Test status
Simulation time 5810318909 ps
CPU time 61.88 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:20:20 PM PST 24
Peak memory 1177252 kb
Host smart-07b8ddc1-4581-4ba9-8418-742bf26cdf40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654142802 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.654142802
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.1113378773
Short name T1499
Test name
Test status
Simulation time 5780074994 ps
CPU time 4.43 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 205564 kb
Host smart-ee3dfe8b-bc30-448b-849f-34fb66f13403
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113378773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.1113378773
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.671183059
Short name T337
Test name
Test status
Simulation time 621424760 ps
CPU time 8.37 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:19:26 PM PST 24
Peak memory 203652 kb
Host smart-3d914086-1d13-4329-a4ba-2524fe86717c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671183059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.671183059
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.2246938242
Short name T434
Test name
Test status
Simulation time 45889029490 ps
CPU time 1034.8 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:36:39 PM PST 24
Peak memory 4124500 kb
Host smart-59a654f3-4549-4be7-8e0b-72ba96a096ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246938242 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.2246938242
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.4288651854
Short name T1145
Test name
Test status
Simulation time 1119305587 ps
CPU time 10.52 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:19:26 PM PST 24
Peak memory 203648 kb
Host smart-e1700aea-ebfa-4c02-9880-c5345da88a9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288651854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.4288651854
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1211820261
Short name T1418
Test name
Test status
Simulation time 17836802138 ps
CPU time 39 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:19:53 PM PST 24
Peak memory 964196 kb
Host smart-8256107b-7dcf-49cb-8ca0-a047c85b21af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211820261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1211820261
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.703010730
Short name T54
Test name
Test status
Simulation time 37603836112 ps
CPU time 629.63 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:29:44 PM PST 24
Peak memory 1556692 kb
Host smart-d316500d-9588-4cb1-91c5-9052d3d28e40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703010730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.703010730
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1078554312
Short name T416
Test name
Test status
Simulation time 1228087808 ps
CPU time 6.06 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:19:20 PM PST 24
Peak memory 203652 kb
Host smart-4e6e94e6-6e35-4bdc-8307-9390eb1e09a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078554312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1078554312
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_ovf.1227254417
Short name T955
Test name
Test status
Simulation time 40115887977 ps
CPU time 129.62 seconds
Started Feb 07 02:19:17 PM PST 24
Finished Feb 07 02:21:28 PM PST 24
Peak memory 357500 kb
Host smart-31e6895c-2438-4db3-9752-c2bb7ce258e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227254417 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_tx_ovf.1227254417
Directory /workspace/4.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1552798218
Short name T908
Test name
Test status
Simulation time 2295816053 ps
CPU time 10.05 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:19:27 PM PST 24
Peak memory 208848 kb
Host smart-0a0687a7-6c82-4dfc-9bc1-a427fe36cd2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552798218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1552798218
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2112023097
Short name T1387
Test name
Test status
Simulation time 34532676 ps
CPU time 0.58 seconds
Started Feb 07 02:27:25 PM PST 24
Finished Feb 07 02:27:26 PM PST 24
Peak memory 202368 kb
Host smart-4a057b9c-e351-4481-acca-d0acd2752a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112023097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2112023097
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2110010745
Short name T403
Test name
Test status
Simulation time 39392557 ps
CPU time 1.61 seconds
Started Feb 07 02:27:19 PM PST 24
Finished Feb 07 02:27:21 PM PST 24
Peak memory 211780 kb
Host smart-a61ecb0b-3838-4b45-a936-1060672e2e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110010745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2110010745
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3441494691
Short name T309
Test name
Test status
Simulation time 417996101 ps
CPU time 8.77 seconds
Started Feb 07 02:27:20 PM PST 24
Finished Feb 07 02:27:30 PM PST 24
Peak memory 295328 kb
Host smart-e40be292-82a5-4a8b-b4fa-c95a17396165
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441494691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3441494691
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1461753101
Short name T561
Test name
Test status
Simulation time 2008949527 ps
CPU time 47.54 seconds
Started Feb 07 02:27:18 PM PST 24
Finished Feb 07 02:28:06 PM PST 24
Peak memory 454104 kb
Host smart-86dcbc86-f841-4623-b1fa-57be0a2e74d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461753101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1461753101
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1591053518
Short name T1481
Test name
Test status
Simulation time 6341827443 ps
CPU time 843.72 seconds
Started Feb 07 02:27:20 PM PST 24
Finished Feb 07 02:41:25 PM PST 24
Peak memory 1751504 kb
Host smart-e12a77bf-dae5-4b22-9ee1-bdc5f4620cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591053518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1591053518
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3749090514
Short name T50
Test name
Test status
Simulation time 115293038 ps
CPU time 0.94 seconds
Started Feb 07 02:27:20 PM PST 24
Finished Feb 07 02:27:21 PM PST 24
Peak memory 203420 kb
Host smart-de68f402-5654-4954-9d47-1592785ad545
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749090514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3749090514
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.4240949294
Short name T660
Test name
Test status
Simulation time 143628871 ps
CPU time 7.59 seconds
Started Feb 07 02:27:20 PM PST 24
Finished Feb 07 02:27:28 PM PST 24
Peak memory 203684 kb
Host smart-f5257776-96ea-451d-9613-9112e98880c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240949294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.4240949294
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.4074736439
Short name T1264
Test name
Test status
Simulation time 6947609343 ps
CPU time 141.8 seconds
Started Feb 07 02:27:23 PM PST 24
Finished Feb 07 02:29:45 PM PST 24
Peak memory 1071988 kb
Host smart-0e74b2f1-0b0b-4874-9006-0ab47d0f78af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074736439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.4074736439
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3336866245
Short name T1539
Test name
Test status
Simulation time 1246050809 ps
CPU time 58.04 seconds
Started Feb 07 02:27:35 PM PST 24
Finished Feb 07 02:28:36 PM PST 24
Peak memory 234348 kb
Host smart-1fef4c1e-b369-40f5-926f-0673b2706590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336866245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3336866245
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.4198485062
Short name T410
Test name
Test status
Simulation time 21943879 ps
CPU time 0.62 seconds
Started Feb 07 02:27:25 PM PST 24
Finished Feb 07 02:27:26 PM PST 24
Peak memory 202564 kb
Host smart-59400bef-28fd-407f-af75-55f11a8ff432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198485062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.4198485062
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3055140157
Short name T1044
Test name
Test status
Simulation time 6889401086 ps
CPU time 129.87 seconds
Started Feb 07 02:27:18 PM PST 24
Finished Feb 07 02:29:29 PM PST 24
Peak memory 343728 kb
Host smart-2c79e673-cf78-4563-92f8-b3a511f21abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055140157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3055140157
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.2467883549
Short name T1194
Test name
Test status
Simulation time 2631691473 ps
CPU time 222.59 seconds
Started Feb 07 02:27:20 PM PST 24
Finished Feb 07 02:31:04 PM PST 24
Peak memory 298808 kb
Host smart-3d0143a9-c23a-46ea-94c7-6b4607b03e6b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467883549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample
.2467883549
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2373584519
Short name T655
Test name
Test status
Simulation time 14009391398 ps
CPU time 143.25 seconds
Started Feb 07 02:27:19 PM PST 24
Finished Feb 07 02:29:43 PM PST 24
Peak memory 250996 kb
Host smart-14c11e22-018a-4904-afdd-5cba9dc11e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373584519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2373584519
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2955468843
Short name T131
Test name
Test status
Simulation time 47448762004 ps
CPU time 474.99 seconds
Started Feb 07 02:27:18 PM PST 24
Finished Feb 07 02:35:14 PM PST 24
Peak memory 1504352 kb
Host smart-9e51c41a-322f-4fa4-90e0-9535df3c30fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955468843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2955468843
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1363056458
Short name T1484
Test name
Test status
Simulation time 1634977505 ps
CPU time 36.09 seconds
Started Feb 07 02:27:19 PM PST 24
Finished Feb 07 02:27:56 PM PST 24
Peak memory 211864 kb
Host smart-d460a70c-f5a2-43fa-ab82-accfebd10b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363056458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1363056458
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1898215208
Short name T556
Test name
Test status
Simulation time 1051907741 ps
CPU time 4.2 seconds
Started Feb 07 02:27:38 PM PST 24
Finished Feb 07 02:27:43 PM PST 24
Peak memory 203660 kb
Host smart-f44ef9ad-a52c-4054-9860-ffb048770c3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898215208 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1898215208
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2387278375
Short name T210
Test name
Test status
Simulation time 10095727778 ps
CPU time 63.16 seconds
Started Feb 07 02:27:30 PM PST 24
Finished Feb 07 02:28:38 PM PST 24
Peak memory 551268 kb
Host smart-1a64af6a-978c-4a0d-91bd-99737b0c6b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387278375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2387278375
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4160423767
Short name T817
Test name
Test status
Simulation time 10357070517 ps
CPU time 4.18 seconds
Started Feb 07 02:27:34 PM PST 24
Finished Feb 07 02:27:42 PM PST 24
Peak memory 250024 kb
Host smart-cbcd13f8-03e4-4a91-ab0c-7edf8eaa557e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160423767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4160423767
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.511710202
Short name T1155
Test name
Test status
Simulation time 1062527440 ps
CPU time 2.19 seconds
Started Feb 07 02:27:27 PM PST 24
Finished Feb 07 02:27:30 PM PST 24
Peak memory 203652 kb
Host smart-76fbac5b-892c-4bae-abf0-1c9ab9e15e50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511710202 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.511710202
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1167524969
Short name T1538
Test name
Test status
Simulation time 1699278156 ps
CPU time 6.39 seconds
Started Feb 07 02:27:35 PM PST 24
Finished Feb 07 02:27:44 PM PST 24
Peak memory 203596 kb
Host smart-5961ed2c-3328-471a-8afc-9e439eafeb41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167524969 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1167524969
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3941135837
Short name T1076
Test name
Test status
Simulation time 20939027403 ps
CPU time 4.89 seconds
Started Feb 07 02:27:26 PM PST 24
Finished Feb 07 02:27:31 PM PST 24
Peak memory 203712 kb
Host smart-fef1a37d-482a-4941-8926-feb50ad5a6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941135837 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3941135837
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.1982016221
Short name T996
Test name
Test status
Simulation time 606290511 ps
CPU time 3.7 seconds
Started Feb 07 02:27:31 PM PST 24
Finished Feb 07 02:27:38 PM PST 24
Peak memory 203428 kb
Host smart-29690b64-aa54-4d1e-91a4-579d79734116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982016221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.1982016221
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1804503169
Short name T355
Test name
Test status
Simulation time 1815480595 ps
CPU time 46.11 seconds
Started Feb 07 02:27:26 PM PST 24
Finished Feb 07 02:28:13 PM PST 24
Peak memory 203612 kb
Host smart-8c908b1f-7798-475a-901d-f0d931485384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804503169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1804503169
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.2259808535
Short name T563
Test name
Test status
Simulation time 49206273114 ps
CPU time 2014.96 seconds
Started Feb 07 02:27:33 PM PST 24
Finished Feb 07 03:01:10 PM PST 24
Peak memory 3117448 kb
Host smart-0ea39f78-6d98-4465-b0d6-cafd6d7bc8e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259808535 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.2259808535
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.539777853
Short name T1482
Test name
Test status
Simulation time 4710776286 ps
CPU time 45.54 seconds
Started Feb 07 02:27:19 PM PST 24
Finished Feb 07 02:28:06 PM PST 24
Peak memory 203788 kb
Host smart-0b3b5059-4e1a-495a-ae50-9089abcce16d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539777853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.539777853
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1663835401
Short name T971
Test name
Test status
Simulation time 32615521208 ps
CPU time 863.7 seconds
Started Feb 07 02:27:18 PM PST 24
Finished Feb 07 02:41:43 PM PST 24
Peak memory 5721308 kb
Host smart-54e7e54b-de55-4d26-8871-9e0bfde8e7ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663835401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1663835401
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1160318175
Short name T497
Test name
Test status
Simulation time 31031061079 ps
CPU time 588.44 seconds
Started Feb 07 02:27:38 PM PST 24
Finished Feb 07 02:37:28 PM PST 24
Peak memory 1634800 kb
Host smart-3db058fa-ed62-4783-a26a-55658cb07276
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160318175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1160318175
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3413879180
Short name T102
Test name
Test status
Simulation time 5082241426 ps
CPU time 7.01 seconds
Started Feb 07 02:27:36 PM PST 24
Finished Feb 07 02:27:45 PM PST 24
Peak memory 210088 kb
Host smart-4aaa7ab3-3a0a-4565-8cc9-fa52deaa6a8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413879180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3413879180
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_ovf.2694901946
Short name T876
Test name
Test status
Simulation time 5411082522 ps
CPU time 34.65 seconds
Started Feb 07 02:27:29 PM PST 24
Finished Feb 07 02:28:08 PM PST 24
Peak memory 213000 kb
Host smart-7cab117d-9be4-42ae-9a18-e65bc1e520d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694901946 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_tx_ovf.2694901946
Directory /workspace/40.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.517690926
Short name T95
Test name
Test status
Simulation time 5862567946 ps
CPU time 4.58 seconds
Started Feb 07 02:27:29 PM PST 24
Finished Feb 07 02:27:34 PM PST 24
Peak memory 203688 kb
Host smart-44b7b81a-6c87-4670-a586-c5a18749e5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517690926 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_unexp_stop.517690926
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1250480253
Short name T984
Test name
Test status
Simulation time 14757867 ps
CPU time 0.59 seconds
Started Feb 07 02:27:49 PM PST 24
Finished Feb 07 02:27:53 PM PST 24
Peak memory 202388 kb
Host smart-7eaa8c8c-3fdc-40a8-87d5-45a8de6f081e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250480253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1250480253
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2803167254
Short name T1478
Test name
Test status
Simulation time 194040611 ps
CPU time 1.01 seconds
Started Feb 07 02:27:43 PM PST 24
Finished Feb 07 02:27:45 PM PST 24
Peak memory 211864 kb
Host smart-1d3a8d82-5119-4e75-81f5-44592080521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803167254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2803167254
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3719405071
Short name T850
Test name
Test status
Simulation time 725593759 ps
CPU time 6.92 seconds
Started Feb 07 02:27:45 PM PST 24
Finished Feb 07 02:27:53 PM PST 24
Peak memory 280300 kb
Host smart-aa30965f-c069-45ef-a84b-91fee65f68e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719405071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3719405071
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1662702593
Short name T1520
Test name
Test status
Simulation time 10797486509 ps
CPU time 160.53 seconds
Started Feb 07 02:27:45 PM PST 24
Finished Feb 07 02:30:27 PM PST 24
Peak memory 251656 kb
Host smart-4894c8a7-2ba9-41a5-8f07-4471f19d0200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662702593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1662702593
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.185749081
Short name T476
Test name
Test status
Simulation time 3684388631 ps
CPU time 198.82 seconds
Started Feb 07 02:27:42 PM PST 24
Finished Feb 07 02:31:02 PM PST 24
Peak memory 1123272 kb
Host smart-91ade3c6-2f89-4925-8f4b-b7a9b6ecee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185749081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.185749081
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3195108556
Short name T48
Test name
Test status
Simulation time 137499163 ps
CPU time 1.08 seconds
Started Feb 07 02:27:43 PM PST 24
Finished Feb 07 02:27:45 PM PST 24
Peak memory 203568 kb
Host smart-2fc404c4-c8a6-4642-a616-887aba7c62f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195108556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3195108556
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2198539295
Short name T404
Test name
Test status
Simulation time 543866127 ps
CPU time 3.7 seconds
Started Feb 07 02:27:44 PM PST 24
Finished Feb 07 02:27:50 PM PST 24
Peak memory 203560 kb
Host smart-179f6917-78b1-44a9-ae51-214c7d1fc5f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198539295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2198539295
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2827102477
Short name T569
Test name
Test status
Simulation time 12595366386 ps
CPU time 124.92 seconds
Started Feb 07 02:27:43 PM PST 24
Finished Feb 07 02:29:50 PM PST 24
Peak memory 1011196 kb
Host smart-d8654c5e-20c6-4f16-9845-7ba348fe68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827102477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2827102477
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.625837477
Short name T509
Test name
Test status
Simulation time 12900419708 ps
CPU time 137.19 seconds
Started Feb 07 02:27:50 PM PST 24
Finished Feb 07 02:30:10 PM PST 24
Peak memory 244580 kb
Host smart-c58b5423-9f95-4d1f-b196-5da1c396773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625837477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.625837477
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.900657902
Short name T870
Test name
Test status
Simulation time 57660337 ps
CPU time 0.62 seconds
Started Feb 07 02:27:34 PM PST 24
Finished Feb 07 02:27:37 PM PST 24
Peak memory 202568 kb
Host smart-28cabf03-9d0b-4b3a-87ef-70f73d96fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900657902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.900657902
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3830019928
Short name T142
Test name
Test status
Simulation time 49164955265 ps
CPU time 2354.78 seconds
Started Feb 07 02:27:44 PM PST 24
Finished Feb 07 03:07:01 PM PST 24
Peak memory 245492 kb
Host smart-b5a49be6-aa60-4b82-8260-3c8ef724c1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830019928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3830019928
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.976874102
Short name T1502
Test name
Test status
Simulation time 13805984699 ps
CPU time 173.02 seconds
Started Feb 07 02:27:35 PM PST 24
Finished Feb 07 02:30:31 PM PST 24
Peak memory 301156 kb
Host smart-8d6b1bac-d997-45c9-bdb8-4ba6f7facc19
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976874102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample.
976874102
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1282597682
Short name T516
Test name
Test status
Simulation time 1720682490 ps
CPU time 40.2 seconds
Started Feb 07 02:27:34 PM PST 24
Finished Feb 07 02:28:15 PM PST 24
Peak memory 263440 kb
Host smart-289e3a9b-eebe-4869-9843-e175a219e4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282597682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1282597682
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.78456902
Short name T319
Test name
Test status
Simulation time 18030042632 ps
CPU time 22.89 seconds
Started Feb 07 02:27:44 PM PST 24
Finished Feb 07 02:28:08 PM PST 24
Peak memory 219716 kb
Host smart-43f5d649-95c2-419c-8df4-4853eb94a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78456902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.78456902
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2099871540
Short name T1244
Test name
Test status
Simulation time 9789399036 ps
CPU time 5.05 seconds
Started Feb 07 02:27:51 PM PST 24
Finished Feb 07 02:27:58 PM PST 24
Peak memory 203676 kb
Host smart-60ddf795-a87e-41d2-b575-c079a7137419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099871540 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2099871540
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.557348894
Short name T1493
Test name
Test status
Simulation time 10027429047 ps
CPU time 52.01 seconds
Started Feb 07 02:27:54 PM PST 24
Finished Feb 07 02:28:48 PM PST 24
Peak memory 397876 kb
Host smart-824622f7-38d0-427d-b28f-3b9ba1660c08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557348894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.557348894
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2079003168
Short name T822
Test name
Test status
Simulation time 10149719364 ps
CPU time 12.18 seconds
Started Feb 07 02:27:50 PM PST 24
Finished Feb 07 02:28:05 PM PST 24
Peak memory 295672 kb
Host smart-6603c331-b333-4ce7-b9fd-d007bad5c164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079003168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2079003168
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1099288070
Short name T540
Test name
Test status
Simulation time 2271867088 ps
CPU time 2.81 seconds
Started Feb 07 02:27:47 PM PST 24
Finished Feb 07 02:27:55 PM PST 24
Peak memory 203628 kb
Host smart-2e6a442b-10c5-43c8-9af6-bf0279977e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099288070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1099288070
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2379446157
Short name T946
Test name
Test status
Simulation time 1716408993 ps
CPU time 6.48 seconds
Started Feb 07 02:27:45 PM PST 24
Finished Feb 07 02:27:53 PM PST 24
Peak memory 203620 kb
Host smart-20f816ce-3a84-4ea4-869f-4247d4a0199b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379446157 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2379446157
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3390698740
Short name T359
Test name
Test status
Simulation time 4571484535 ps
CPU time 7.48 seconds
Started Feb 07 02:27:42 PM PST 24
Finished Feb 07 02:27:50 PM PST 24
Peak memory 333720 kb
Host smart-8b305dff-fff3-4657-8745-279faa49244f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390698740 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3390698740
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.3430325796
Short name T327
Test name
Test status
Simulation time 1711134701 ps
CPU time 4.79 seconds
Started Feb 07 02:27:54 PM PST 24
Finished Feb 07 02:28:01 PM PST 24
Peak memory 203660 kb
Host smart-5dc35dcf-97ac-4b9c-b5ff-04cba5073c19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430325796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.3430325796
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1136292594
Short name T96
Test name
Test status
Simulation time 1652213244 ps
CPU time 20.5 seconds
Started Feb 07 02:27:43 PM PST 24
Finished Feb 07 02:28:04 PM PST 24
Peak memory 203628 kb
Host smart-73b69fdf-236e-4779-9061-1b92e8421e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136292594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1136292594
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.2561224884
Short name T398
Test name
Test status
Simulation time 10353134799 ps
CPU time 67.16 seconds
Started Feb 07 02:27:50 PM PST 24
Finished Feb 07 02:29:00 PM PST 24
Peak memory 238288 kb
Host smart-ec7fcc7d-98a0-4fed-84f3-1625430e0061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561224884 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.2561224884
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1628165665
Short name T443
Test name
Test status
Simulation time 2091738128 ps
CPU time 80.96 seconds
Started Feb 07 02:27:43 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 205392 kb
Host smart-167807c0-9dbc-40b0-b5fe-28002fa2d8e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628165665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1628165665
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2927487434
Short name T868
Test name
Test status
Simulation time 61796181695 ps
CPU time 1944.7 seconds
Started Feb 07 02:27:42 PM PST 24
Finished Feb 07 03:00:08 PM PST 24
Peak memory 7757644 kb
Host smart-6250a852-8ccc-402f-b203-daaf25ada8b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927487434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2927487434
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1083260326
Short name T1186
Test name
Test status
Simulation time 23011406205 ps
CPU time 447.01 seconds
Started Feb 07 02:27:44 PM PST 24
Finished Feb 07 02:35:13 PM PST 24
Peak memory 2714364 kb
Host smart-41a43c56-c55c-4ed5-81b9-c2de71d0fcbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083260326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1083260326
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.899888008
Short name T1545
Test name
Test status
Simulation time 31745878814 ps
CPU time 8.22 seconds
Started Feb 07 02:27:43 PM PST 24
Finished Feb 07 02:27:52 PM PST 24
Peak memory 214920 kb
Host smart-3cedb27c-f4dc-4777-98e1-66e631dcbb58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899888008 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_timeout.899888008
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_ovf.3250293422
Short name T216
Test name
Test status
Simulation time 13702166888 ps
CPU time 35.48 seconds
Started Feb 07 02:27:45 PM PST 24
Finished Feb 07 02:28:22 PM PST 24
Peak memory 216836 kb
Host smart-ffb3d9da-8439-4d33-b5e7-57ba24cacfaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250293422 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_tx_ovf.3250293422
Directory /workspace/41.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.3885505130
Short name T1298
Test name
Test status
Simulation time 5856785832 ps
CPU time 6.76 seconds
Started Feb 07 02:27:51 PM PST 24
Finished Feb 07 02:28:02 PM PST 24
Peak memory 211932 kb
Host smart-d8454269-7042-43f8-b364-61d56e6d4bb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885505130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.3885505130
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.943622367
Short name T701
Test name
Test status
Simulation time 14914698 ps
CPU time 0.67 seconds
Started Feb 07 02:28:11 PM PST 24
Finished Feb 07 02:28:13 PM PST 24
Peak memory 202380 kb
Host smart-10578202-8145-4cec-a1ef-36f3de52d2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943622367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.943622367
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1719016301
Short name T727
Test name
Test status
Simulation time 23351263 ps
CPU time 1.07 seconds
Started Feb 07 02:27:47 PM PST 24
Finished Feb 07 02:27:54 PM PST 24
Peak memory 211908 kb
Host smart-e4762b27-bc14-4ee5-b7a4-8410e3b700ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719016301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1719016301
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1940547432
Short name T1456
Test name
Test status
Simulation time 296489301 ps
CPU time 6.11 seconds
Started Feb 07 02:27:49 PM PST 24
Finished Feb 07 02:27:59 PM PST 24
Peak memory 241856 kb
Host smart-a8cd0ddd-b8dc-4d32-a06d-b4ea60260aef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940547432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1940547432
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3676991633
Short name T1401
Test name
Test status
Simulation time 3635594917 ps
CPU time 134.65 seconds
Started Feb 07 02:27:48 PM PST 24
Finished Feb 07 02:30:07 PM PST 24
Peak memory 1074616 kb
Host smart-3393524e-ed6a-4b45-b2ba-6cc21fcac923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676991633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3676991633
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1305691367
Short name T1270
Test name
Test status
Simulation time 25927247013 ps
CPU time 555.46 seconds
Started Feb 07 02:27:54 PM PST 24
Finished Feb 07 02:37:12 PM PST 24
Peak memory 1854364 kb
Host smart-ea21cbcc-065e-49e7-a129-bdb5a2861282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305691367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1305691367
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2409193723
Short name T990
Test name
Test status
Simulation time 280243969 ps
CPU time 0.79 seconds
Started Feb 07 02:27:46 PM PST 24
Finished Feb 07 02:27:53 PM PST 24
Peak memory 203400 kb
Host smart-1e3e9d6c-cadc-4b00-b6c2-94b5f32c299a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409193723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2409193723
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3832315178
Short name T238
Test name
Test status
Simulation time 18736395994 ps
CPU time 426.52 seconds
Started Feb 07 02:27:52 PM PST 24
Finished Feb 07 02:35:02 PM PST 24
Peak memory 1223608 kb
Host smart-bf83526b-20bb-4e0d-b19e-5a786ba38620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832315178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3832315178
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.4132947773
Short name T43
Test name
Test status
Simulation time 3791334670 ps
CPU time 114.97 seconds
Started Feb 07 02:28:02 PM PST 24
Finished Feb 07 02:29:58 PM PST 24
Peak memory 258476 kb
Host smart-f9501d02-181c-497f-8c23-92308551c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132947773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.4132947773
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1230080223
Short name T527
Test name
Test status
Simulation time 17421762 ps
CPU time 0.67 seconds
Started Feb 07 02:27:50 PM PST 24
Finished Feb 07 02:27:53 PM PST 24
Peak memory 202612 kb
Host smart-cf7abd5e-deb0-41a5-a333-3a3fcc825017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230080223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1230080223
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2945682106
Short name T1090
Test name
Test status
Simulation time 2252541792 ps
CPU time 25.15 seconds
Started Feb 07 02:27:51 PM PST 24
Finished Feb 07 02:28:19 PM PST 24
Peak memory 203760 kb
Host smart-1ce54ddb-abed-4066-abf0-6aa7c0525734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945682106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2945682106
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.2083404864
Short name T653
Test name
Test status
Simulation time 5375811129 ps
CPU time 119.02 seconds
Started Feb 07 02:27:52 PM PST 24
Finished Feb 07 02:29:55 PM PST 24
Peak memory 330564 kb
Host smart-1d927010-38d8-4fa4-aeb0-ec556e89c99b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083404864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample
.2083404864
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2854008645
Short name T251
Test name
Test status
Simulation time 2071300071 ps
CPU time 40.66 seconds
Started Feb 07 02:27:51 PM PST 24
Finished Feb 07 02:28:34 PM PST 24
Peak memory 274808 kb
Host smart-a2e36878-3f0d-4e21-9218-fc7ec1c6ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854008645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2854008645
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3236657321
Short name T1054
Test name
Test status
Simulation time 31850056477 ps
CPU time 898.5 seconds
Started Feb 07 02:27:51 PM PST 24
Finished Feb 07 02:42:52 PM PST 24
Peak memory 910952 kb
Host smart-a8607ab1-3250-421d-bfe9-8e25b0b5b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236657321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3236657321
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3756994199
Short name T358
Test name
Test status
Simulation time 7537210695 ps
CPU time 12.94 seconds
Started Feb 07 02:27:51 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 220104 kb
Host smart-f946edb2-8948-429d-bf91-2e58ad869722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756994199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3756994199
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.727004656
Short name T600
Test name
Test status
Simulation time 1243135000 ps
CPU time 4.74 seconds
Started Feb 07 02:28:02 PM PST 24
Finished Feb 07 02:28:08 PM PST 24
Peak memory 203620 kb
Host smart-4af86589-7f71-42db-b4da-3b5d9ee1bfed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727004656 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.727004656
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3414955285
Short name T1350
Test name
Test status
Simulation time 10105970312 ps
CPU time 59.83 seconds
Started Feb 07 02:28:04 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 558364 kb
Host smart-97d43e03-6a01-4080-972d-0f2e0a1c4050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414955285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3414955285
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.799522231
Short name T301
Test name
Test status
Simulation time 10155470688 ps
CPU time 14.42 seconds
Started Feb 07 02:28:00 PM PST 24
Finished Feb 07 02:28:15 PM PST 24
Peak memory 340852 kb
Host smart-99fc4267-aca3-47cf-ab3e-0c844bc539bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799522231 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.799522231
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.4238016378
Short name T1211
Test name
Test status
Simulation time 637651351 ps
CPU time 2.79 seconds
Started Feb 07 02:28:02 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 203688 kb
Host smart-0d6e888f-bbe6-4a2c-942c-64f6fa954100
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238016378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.4238016378
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.4231080778
Short name T1144
Test name
Test status
Simulation time 1299928030 ps
CPU time 4.73 seconds
Started Feb 07 02:28:01 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 203632 kb
Host smart-69bf8a92-304d-428d-867d-fe96d14360b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231080778 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.4231080778
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3511376724
Short name T460
Test name
Test status
Simulation time 17429058299 ps
CPU time 79.03 seconds
Started Feb 07 02:28:02 PM PST 24
Finished Feb 07 02:29:23 PM PST 24
Peak memory 998152 kb
Host smart-61d42a0b-b385-4f50-89a2-b19d0436aa36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511376724 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3511376724
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.1863010136
Short name T1192
Test name
Test status
Simulation time 10971747152 ps
CPU time 4.65 seconds
Started Feb 07 02:28:02 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 206152 kb
Host smart-9098f887-ec83-4e19-a256-df926bec0e08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863010136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.1863010136
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1391355518
Short name T308
Test name
Test status
Simulation time 5123335201 ps
CPU time 34.18 seconds
Started Feb 07 02:28:06 PM PST 24
Finished Feb 07 02:28:45 PM PST 24
Peak memory 203756 kb
Host smart-504792ec-bfb0-47d1-8e21-fbf2ea710062
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391355518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1391355518
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1484237504
Short name T1406
Test name
Test status
Simulation time 29116984238 ps
CPU time 709.97 seconds
Started Feb 07 02:28:03 PM PST 24
Finished Feb 07 02:39:55 PM PST 24
Peak memory 4737056 kb
Host smart-f202aeb9-abf9-4c29-9e2e-c23bb8ca0feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484237504 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1484237504
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2689643512
Short name T873
Test name
Test status
Simulation time 1264254451 ps
CPU time 5.83 seconds
Started Feb 07 02:28:03 PM PST 24
Finished Feb 07 02:28:10 PM PST 24
Peak memory 203620 kb
Host smart-c4e65744-cc64-4b09-aadd-4ed74e027b83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689643512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2689643512
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2805541878
Short name T1479
Test name
Test status
Simulation time 31909010850 ps
CPU time 19.05 seconds
Started Feb 07 02:28:00 PM PST 24
Finished Feb 07 02:28:20 PM PST 24
Peak memory 515400 kb
Host smart-7a1c8586-08db-47ff-9834-6bb4c71e442f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805541878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2805541878
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3641706524
Short name T439
Test name
Test status
Simulation time 48490947007 ps
CPU time 152.96 seconds
Started Feb 07 02:28:03 PM PST 24
Finished Feb 07 02:30:38 PM PST 24
Peak memory 959176 kb
Host smart-104f9e79-68d0-457a-b009-50fb030b120d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641706524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3641706524
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3582989724
Short name T796
Test name
Test status
Simulation time 4463987143 ps
CPU time 9.28 seconds
Started Feb 07 02:28:00 PM PST 24
Finished Feb 07 02:28:10 PM PST 24
Peak memory 213132 kb
Host smart-54e333c1-1539-4efe-9914-c174c852b568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582989724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3582989724
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_ovf.1009059717
Short name T351
Test name
Test status
Simulation time 61487135454 ps
CPU time 104.88 seconds
Started Feb 07 02:28:01 PM PST 24
Finished Feb 07 02:29:46 PM PST 24
Peak memory 334732 kb
Host smart-1efba494-3b03-4ddb-88da-d0778c32a9b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009059717 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_tx_ovf.1009059717
Directory /workspace/42.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.3172228047
Short name T659
Test name
Test status
Simulation time 5463329109 ps
CPU time 7.92 seconds
Started Feb 07 02:28:00 PM PST 24
Finished Feb 07 02:28:09 PM PST 24
Peak memory 212600 kb
Host smart-b032f29f-c119-49c8-8275-78d77c4d1543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172228047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.3172228047
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2084050350
Short name T918
Test name
Test status
Simulation time 31516516 ps
CPU time 0.59 seconds
Started Feb 07 02:28:19 PM PST 24
Finished Feb 07 02:28:20 PM PST 24
Peak memory 202304 kb
Host smart-838352da-ec15-4217-8f17-82a75af533f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084050350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2084050350
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1596941971
Short name T666
Test name
Test status
Simulation time 129473329 ps
CPU time 1.23 seconds
Started Feb 07 02:28:16 PM PST 24
Finished Feb 07 02:28:18 PM PST 24
Peak memory 211780 kb
Host smart-11ea1e21-fe52-4b45-ac48-195c9efb8fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596941971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1596941971
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2738211138
Short name T194
Test name
Test status
Simulation time 3261559471 ps
CPU time 9.83 seconds
Started Feb 07 02:28:17 PM PST 24
Finished Feb 07 02:28:28 PM PST 24
Peak memory 322904 kb
Host smart-0876b14e-d990-4837-8f73-5f1eb4f76452
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738211138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2738211138
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2234296868
Short name T475
Test name
Test status
Simulation time 3004591224 ps
CPU time 94.26 seconds
Started Feb 07 02:28:11 PM PST 24
Finished Feb 07 02:29:47 PM PST 24
Peak memory 646920 kb
Host smart-dc078244-8634-4684-97c3-01228c0b73e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234296868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2234296868
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1870081360
Short name T878
Test name
Test status
Simulation time 6802577385 ps
CPU time 561.19 seconds
Started Feb 07 02:28:04 PM PST 24
Finished Feb 07 02:37:27 PM PST 24
Peak memory 1784780 kb
Host smart-f3f63a21-386d-43ca-8751-3c3b7e18c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870081360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1870081360
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2014522723
Short name T334
Test name
Test status
Simulation time 284258910 ps
CPU time 1.04 seconds
Started Feb 07 02:28:05 PM PST 24
Finished Feb 07 02:28:07 PM PST 24
Peak memory 203600 kb
Host smart-e337076d-93ff-4c9b-979d-fa4a6ffe9899
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014522723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2014522723
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3636072529
Short name T346
Test name
Test status
Simulation time 1077969263 ps
CPU time 15.4 seconds
Started Feb 07 02:28:12 PM PST 24
Finished Feb 07 02:28:30 PM PST 24
Peak memory 258600 kb
Host smart-1e5c816a-c94f-46d0-a311-7df094c05de9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636072529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3636072529
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.619235396
Short name T923
Test name
Test status
Simulation time 17861107553 ps
CPU time 212.73 seconds
Started Feb 07 02:28:10 PM PST 24
Finished Feb 07 02:31:45 PM PST 24
Peak memory 1276512 kb
Host smart-f8b4eadd-862d-4e2d-8614-9b64a510d018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619235396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.619235396
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1315908173
Short name T1259
Test name
Test status
Simulation time 2187990595 ps
CPU time 69.89 seconds
Started Feb 07 02:28:21 PM PST 24
Finished Feb 07 02:29:31 PM PST 24
Peak memory 402000 kb
Host smart-1c69f8c4-3dde-4cc4-924e-4383fbde6282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315908173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1315908173
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.4196033048
Short name T495
Test name
Test status
Simulation time 41029958 ps
CPU time 0.67 seconds
Started Feb 07 02:28:12 PM PST 24
Finished Feb 07 02:28:15 PM PST 24
Peak memory 202508 kb
Host smart-43c4c2dd-4b03-4d9b-868d-cfafbac016ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196033048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.4196033048
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1472262573
Short name T316
Test name
Test status
Simulation time 12987059669 ps
CPU time 464.16 seconds
Started Feb 07 02:28:12 PM PST 24
Finished Feb 07 02:35:59 PM PST 24
Peak memory 249916 kb
Host smart-b8e6d83d-319a-457c-9131-76e67c951d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472262573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1472262573
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.2144985356
Short name T1112
Test name
Test status
Simulation time 1625723835 ps
CPU time 52.63 seconds
Started Feb 07 02:28:14 PM PST 24
Finished Feb 07 02:29:08 PM PST 24
Peak memory 268140 kb
Host smart-340e2c91-eddc-4dd9-aafc-7788d49edc16
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144985356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample
.2144985356
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.982823680
Short name T1375
Test name
Test status
Simulation time 1456219651 ps
CPU time 72.3 seconds
Started Feb 07 02:28:02 PM PST 24
Finished Feb 07 02:29:15 PM PST 24
Peak memory 228144 kb
Host smart-1c282767-fb99-4bd1-a41e-e510301eb649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982823680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.982823680
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.953575123
Short name T133
Test name
Test status
Simulation time 51868824131 ps
CPU time 3282.22 seconds
Started Feb 07 02:28:14 PM PST 24
Finished Feb 07 03:22:58 PM PST 24
Peak memory 1795508 kb
Host smart-a9feacaf-6f8e-4ce6-8ea9-b911e9405799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953575123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.953575123
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1297179502
Short name T1356
Test name
Test status
Simulation time 6270313402 ps
CPU time 11.77 seconds
Started Feb 07 02:28:13 PM PST 24
Finished Feb 07 02:28:27 PM PST 24
Peak memory 211912 kb
Host smart-81bbe700-23de-42e8-ba9a-4dc24f3dca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297179502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1297179502
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2177269074
Short name T1284
Test name
Test status
Simulation time 8326119543 ps
CPU time 4.97 seconds
Started Feb 07 02:28:19 PM PST 24
Finished Feb 07 02:28:25 PM PST 24
Peak memory 203680 kb
Host smart-b043150c-ad14-4ac1-a93b-7cbe89e951d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177269074 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2177269074
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1720107734
Short name T500
Test name
Test status
Simulation time 10099081266 ps
CPU time 9.62 seconds
Started Feb 07 02:28:24 PM PST 24
Finished Feb 07 02:28:34 PM PST 24
Peak memory 253156 kb
Host smart-8c33a826-0a24-4fbd-8952-ef6bb6ff22d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720107734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1720107734
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3198375092
Short name T409
Test name
Test status
Simulation time 10642515009 ps
CPU time 12.18 seconds
Started Feb 07 02:28:21 PM PST 24
Finished Feb 07 02:28:33 PM PST 24
Peak memory 297356 kb
Host smart-0c0e1a35-82ce-4861-92f9-68e41d5a4da5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198375092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3198375092
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.793716155
Short name T35
Test name
Test status
Simulation time 539974960 ps
CPU time 2.45 seconds
Started Feb 07 02:28:19 PM PST 24
Finished Feb 07 02:28:22 PM PST 24
Peak memory 203668 kb
Host smart-b7eae96c-49bb-41bb-9629-ea0f0e749f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793716155 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.793716155
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2003520852
Short name T1378
Test name
Test status
Simulation time 8724698658 ps
CPU time 5.21 seconds
Started Feb 07 02:28:11 PM PST 24
Finished Feb 07 02:28:18 PM PST 24
Peak memory 205552 kb
Host smart-a5ea1bc2-58f0-43b1-84da-2706bf25314e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003520852 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2003520852
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1541109012
Short name T1475
Test name
Test status
Simulation time 20757929028 ps
CPU time 283.52 seconds
Started Feb 07 02:28:14 PM PST 24
Finished Feb 07 02:32:59 PM PST 24
Peak memory 2512784 kb
Host smart-cc77667d-060a-49a6-a6c9-a2ca12e0b755
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541109012 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1541109012
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.4162079626
Short name T664
Test name
Test status
Simulation time 1812352885 ps
CPU time 5.38 seconds
Started Feb 07 02:28:24 PM PST 24
Finished Feb 07 02:28:30 PM PST 24
Peak memory 208984 kb
Host smart-47090f27-fb6d-4bc5-b1ac-118bd1598801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162079626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.4162079626
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.4161711640
Short name T1433
Test name
Test status
Simulation time 2438039748 ps
CPU time 14.93 seconds
Started Feb 07 02:28:12 PM PST 24
Finished Feb 07 02:28:30 PM PST 24
Peak memory 203772 kb
Host smart-e964df01-75c4-4e60-bc08-550c04dfacc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161711640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.4161711640
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.2558812300
Short name T1421
Test name
Test status
Simulation time 60679661061 ps
CPU time 2801.49 seconds
Started Feb 07 02:28:22 PM PST 24
Finished Feb 07 03:15:05 PM PST 24
Peak memory 9941720 kb
Host smart-85a7217e-7705-40fc-b545-3255b280af3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558812300 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.2558812300
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3101676381
Short name T1384
Test name
Test status
Simulation time 6854630971 ps
CPU time 56.12 seconds
Started Feb 07 02:28:11 PM PST 24
Finished Feb 07 02:29:09 PM PST 24
Peak memory 204032 kb
Host smart-3d5e96e5-a7e8-467e-a1b2-11257e97d436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101676381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3101676381
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3650674064
Short name T245
Test name
Test status
Simulation time 40186132809 ps
CPU time 1856.39 seconds
Started Feb 07 02:28:18 PM PST 24
Finished Feb 07 02:59:16 PM PST 24
Peak memory 8908168 kb
Host smart-3e422b6b-8fec-4d0a-abf6-f977ce805120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650674064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3650674064
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1619042405
Short name T1213
Test name
Test status
Simulation time 16505657701 ps
CPU time 149.14 seconds
Started Feb 07 02:28:11 PM PST 24
Finished Feb 07 02:30:41 PM PST 24
Peak memory 1471680 kb
Host smart-0e3a7a4e-96a2-4085-97a5-24c905bfa4ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619042405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1619042405
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1196871579
Short name T1357
Test name
Test status
Simulation time 2174470620 ps
CPU time 8.3 seconds
Started Feb 07 02:28:13 PM PST 24
Finished Feb 07 02:28:24 PM PST 24
Peak memory 203792 kb
Host smart-ae36c8cd-26ae-43ae-9610-579a61f8253f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196871579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1196871579
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_ovf.3575796468
Short name T440
Test name
Test status
Simulation time 10406087861 ps
CPU time 36.84 seconds
Started Feb 07 02:28:09 PM PST 24
Finished Feb 07 02:28:49 PM PST 24
Peak memory 213944 kb
Host smart-5ac329af-a4ee-4d5a-a643-d85744a6232e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575796468 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_tx_ovf.3575796468
Directory /workspace/43.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.3331359572
Short name T393
Test name
Test status
Simulation time 1648158268 ps
CPU time 3.67 seconds
Started Feb 07 02:28:18 PM PST 24
Finished Feb 07 02:28:22 PM PST 24
Peak memory 203596 kb
Host smart-56e4b86f-35c3-4d7b-89b2-757cf8be6ab3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331359572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.i2c_target_unexp_stop.3331359572
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2435320229
Short name T1512
Test name
Test status
Simulation time 51324475 ps
CPU time 0.67 seconds
Started Feb 07 02:28:37 PM PST 24
Finished Feb 07 02:28:38 PM PST 24
Peak memory 202388 kb
Host smart-e8df9719-2350-4355-9fd8-485f6487e319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435320229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2435320229
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.4186440546
Short name T954
Test name
Test status
Simulation time 30288058 ps
CPU time 0.94 seconds
Started Feb 07 02:28:28 PM PST 24
Finished Feb 07 02:28:30 PM PST 24
Peak memory 203556 kb
Host smart-974ad4e9-fc49-46e1-bb13-4f3459c3d70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186440546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.4186440546
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.672948044
Short name T512
Test name
Test status
Simulation time 465218963 ps
CPU time 8.64 seconds
Started Feb 07 02:28:29 PM PST 24
Finished Feb 07 02:28:38 PM PST 24
Peak memory 305208 kb
Host smart-2a986127-1b8a-4cbd-b5c3-b3c4a6780f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672948044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.672948044
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1148158866
Short name T1491
Test name
Test status
Simulation time 3274332597 ps
CPU time 133.33 seconds
Started Feb 07 02:28:29 PM PST 24
Finished Feb 07 02:30:43 PM PST 24
Peak memory 971648 kb
Host smart-2cf5b481-0d12-4e6b-a647-11facf9bead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148158866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1148158866
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2665000625
Short name T186
Test name
Test status
Simulation time 23539990295 ps
CPU time 386.64 seconds
Started Feb 07 02:28:24 PM PST 24
Finished Feb 07 02:34:51 PM PST 24
Peak memory 1645508 kb
Host smart-1476e287-9bf6-4de3-93b7-860f13fef56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665000625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2665000625
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2892791910
Short name T486
Test name
Test status
Simulation time 95435076 ps
CPU time 0.96 seconds
Started Feb 07 02:28:27 PM PST 24
Finished Feb 07 02:28:29 PM PST 24
Peak memory 203576 kb
Host smart-e6f92a00-fafe-4bc0-a2ce-086fc329a915
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892791910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2892791910
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.312310094
Short name T235
Test name
Test status
Simulation time 174702878 ps
CPU time 4.67 seconds
Started Feb 07 02:28:28 PM PST 24
Finished Feb 07 02:28:33 PM PST 24
Peak memory 234216 kb
Host smart-bdb5a53b-a42f-4645-b775-153792abc795
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312310094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
312310094
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3913847182
Short name T1299
Test name
Test status
Simulation time 12614539378 ps
CPU time 686.02 seconds
Started Feb 07 02:28:20 PM PST 24
Finished Feb 07 02:39:47 PM PST 24
Peak memory 1703720 kb
Host smart-c0ede2a6-1d60-4b7b-935f-d32012805bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913847182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3913847182
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1785854684
Short name T1052
Test name
Test status
Simulation time 2150972156 ps
CPU time 191.45 seconds
Started Feb 07 02:28:46 PM PST 24
Finished Feb 07 02:31:58 PM PST 24
Peak memory 404316 kb
Host smart-267fd3a1-7854-4a5e-a540-176bfeccade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785854684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1785854684
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3281304484
Short name T837
Test name
Test status
Simulation time 43842135 ps
CPU time 0.61 seconds
Started Feb 07 02:28:24 PM PST 24
Finished Feb 07 02:28:25 PM PST 24
Peak memory 202620 kb
Host smart-71f2a5b1-bd05-4c77-b314-39d1f885e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281304484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3281304484
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1357081122
Short name T560
Test name
Test status
Simulation time 6001756243 ps
CPU time 92.76 seconds
Started Feb 07 02:28:30 PM PST 24
Finished Feb 07 02:30:04 PM PST 24
Peak memory 246860 kb
Host smart-f76015cd-9515-48df-8ffb-9e6a08d65f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357081122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1357081122
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.4223467713
Short name T613
Test name
Test status
Simulation time 2736854756 ps
CPU time 135.28 seconds
Started Feb 07 02:28:21 PM PST 24
Finished Feb 07 02:30:37 PM PST 24
Peak memory 365832 kb
Host smart-b6bc6398-6e44-4db8-8bb7-272e547fd9e9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223467713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample
.4223467713
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2201821045
Short name T798
Test name
Test status
Simulation time 3248277289 ps
CPU time 45.27 seconds
Started Feb 07 02:28:19 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 297256 kb
Host smart-994f4607-75dd-42ac-8617-547c48a84944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201821045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2201821045
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.2614121826
Short name T773
Test name
Test status
Simulation time 81165558620 ps
CPU time 2451.51 seconds
Started Feb 07 02:28:27 PM PST 24
Finished Feb 07 03:09:19 PM PST 24
Peak memory 3024808 kb
Host smart-d6aef445-bac8-4b02-9fdc-2f65161b36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614121826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.2614121826
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3648024863
Short name T1454
Test name
Test status
Simulation time 1019013408 ps
CPU time 22.51 seconds
Started Feb 07 02:28:31 PM PST 24
Finished Feb 07 02:28:54 PM PST 24
Peak memory 211760 kb
Host smart-7bc79169-2b78-4fe0-9b36-4c53b27ece6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648024863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3648024863
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2698036982
Short name T482
Test name
Test status
Simulation time 4928023439 ps
CPU time 3.82 seconds
Started Feb 07 02:28:35 PM PST 24
Finished Feb 07 02:28:39 PM PST 24
Peak memory 203708 kb
Host smart-15d2c774-a70b-4d24-b5b7-8c3271041a54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698036982 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2698036982
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.537974090
Short name T198
Test name
Test status
Simulation time 10060654350 ps
CPU time 23.43 seconds
Started Feb 07 02:28:39 PM PST 24
Finished Feb 07 02:29:03 PM PST 24
Peak memory 316708 kb
Host smart-2a8da49b-9909-4496-b1d9-60866b3a8bf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537974090 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.537974090
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.982605306
Short name T978
Test name
Test status
Simulation time 10173633012 ps
CPU time 13.66 seconds
Started Feb 07 02:28:38 PM PST 24
Finished Feb 07 02:28:52 PM PST 24
Peak memory 295832 kb
Host smart-50184a3b-bace-45d7-a2fd-2a448e700b78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982605306 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.982605306
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3060989131
Short name T157
Test name
Test status
Simulation time 449223916 ps
CPU time 2.16 seconds
Started Feb 07 02:28:36 PM PST 24
Finished Feb 07 02:28:39 PM PST 24
Peak memory 203668 kb
Host smart-5ae299cd-999f-4231-87a5-a7b4ce894316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060989131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3060989131
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2148678400
Short name T1189
Test name
Test status
Simulation time 7295316986 ps
CPU time 6.4 seconds
Started Feb 07 02:28:28 PM PST 24
Finished Feb 07 02:28:35 PM PST 24
Peak memory 203736 kb
Host smart-90a7c851-e156-4bb5-8ab4-c0d266f95806
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148678400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2148678400
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2674504166
Short name T1514
Test name
Test status
Simulation time 4527398147 ps
CPU time 42.49 seconds
Started Feb 07 02:28:30 PM PST 24
Finished Feb 07 02:29:13 PM PST 24
Peak memory 925720 kb
Host smart-d46532d5-b02d-4d52-8ed9-6966f7006ab5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674504166 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2674504166
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.1920468121
Short name T1105
Test name
Test status
Simulation time 471760690 ps
CPU time 2.89 seconds
Started Feb 07 02:28:37 PM PST 24
Finished Feb 07 02:28:40 PM PST 24
Peak memory 203612 kb
Host smart-44276a48-9af7-41c4-b47d-e93b06a54b25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920468121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.1920468121
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.77215708
Short name T1024
Test name
Test status
Simulation time 17703024642 ps
CPU time 48.03 seconds
Started Feb 07 02:28:27 PM PST 24
Finished Feb 07 02:29:16 PM PST 24
Peak memory 203792 kb
Host smart-6cf97b92-3dda-48ba-8d33-0a76408ca646
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77215708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_targ
et_smoke.77215708
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.263501094
Short name T1464
Test name
Test status
Simulation time 22228525428 ps
CPU time 317.38 seconds
Started Feb 07 02:28:38 PM PST 24
Finished Feb 07 02:33:56 PM PST 24
Peak memory 1854712 kb
Host smart-2087aea4-dae3-409e-8ede-5fb6af98de58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263501094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.263501094
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2235813839
Short name T543
Test name
Test status
Simulation time 2302022098 ps
CPU time 37 seconds
Started Feb 07 02:28:29 PM PST 24
Finished Feb 07 02:29:07 PM PST 24
Peak memory 224416 kb
Host smart-d0110e7f-83ee-4d15-9d25-ec58ee232d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235813839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2235813839
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3711911830
Short name T1438
Test name
Test status
Simulation time 29437682319 ps
CPU time 871.79 seconds
Started Feb 07 02:28:28 PM PST 24
Finished Feb 07 02:43:01 PM PST 24
Peak memory 6216000 kb
Host smart-e44fa074-6356-4d02-9fec-99a58f6bc625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711911830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3711911830
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2450081448
Short name T608
Test name
Test status
Simulation time 39552877231 ps
CPU time 281.71 seconds
Started Feb 07 02:28:27 PM PST 24
Finished Feb 07 02:33:10 PM PST 24
Peak memory 1785896 kb
Host smart-b9b7e97e-cad0-46fa-b4ca-bc450b2a2495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450081448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2450081448
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.100765377
Short name T215
Test name
Test status
Simulation time 3770122342 ps
CPU time 6.86 seconds
Started Feb 07 02:28:28 PM PST 24
Finished Feb 07 02:28:35 PM PST 24
Peak memory 203632 kb
Host smart-35238bdd-2830-43e0-8563-66d53229b893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100765377 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.100765377
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_ovf.2248486129
Short name T795
Test name
Test status
Simulation time 3571467235 ps
CPU time 278.05 seconds
Started Feb 07 02:28:27 PM PST 24
Finished Feb 07 02:33:06 PM PST 24
Peak memory 536940 kb
Host smart-e14cec2e-0673-455c-8399-9234bbec836c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248486129 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_tx_ovf.2248486129
Directory /workspace/44.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.2173901286
Short name T1154
Test name
Test status
Simulation time 2096976542 ps
CPU time 5.16 seconds
Started Feb 07 02:28:30 PM PST 24
Finished Feb 07 02:28:36 PM PST 24
Peak memory 203588 kb
Host smart-180c2f41-4938-4f0e-8fff-aafb817521be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173901286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.2173901286
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1714259394
Short name T639
Test name
Test status
Simulation time 33156082 ps
CPU time 0.59 seconds
Started Feb 07 02:29:10 PM PST 24
Finished Feb 07 02:29:11 PM PST 24
Peak memory 202364 kb
Host smart-a97b1a83-b3a4-43f0-a25f-0871d7adf6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714259394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1714259394
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1352929288
Short name T389
Test name
Test status
Simulation time 44408687 ps
CPU time 1.2 seconds
Started Feb 07 02:28:40 PM PST 24
Finished Feb 07 02:28:42 PM PST 24
Peak memory 211868 kb
Host smart-b48598ab-47e1-454c-a74c-a078dcd6de1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352929288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1352929288
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1800772636
Short name T321
Test name
Test status
Simulation time 1352877046 ps
CPU time 3.47 seconds
Started Feb 07 02:28:46 PM PST 24
Finished Feb 07 02:28:50 PM PST 24
Peak memory 230344 kb
Host smart-c6fe8e1c-ea58-465c-8c0f-d7bcc8828750
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800772636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1800772636
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2797620045
Short name T1249
Test name
Test status
Simulation time 9035445552 ps
CPU time 69.42 seconds
Started Feb 07 02:28:40 PM PST 24
Finished Feb 07 02:29:50 PM PST 24
Peak memory 701008 kb
Host smart-5a8eea7d-72f0-482c-b001-0ff397a7f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797620045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2797620045
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3770859319
Short name T825
Test name
Test status
Simulation time 4912476748 ps
CPU time 558.39 seconds
Started Feb 07 02:28:46 PM PST 24
Finished Feb 07 02:38:05 PM PST 24
Peak memory 1379076 kb
Host smart-23c8b192-bd97-4900-883b-e2ff8b0067fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770859319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3770859319
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3477537109
Short name T1547
Test name
Test status
Simulation time 103402429 ps
CPU time 0.97 seconds
Started Feb 07 02:28:38 PM PST 24
Finished Feb 07 02:28:39 PM PST 24
Peak memory 203388 kb
Host smart-256d2239-9042-4a98-9c2d-cba2bd44e08b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477537109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3477537109
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1377433759
Short name T630
Test name
Test status
Simulation time 241735812 ps
CPU time 13.26 seconds
Started Feb 07 02:28:41 PM PST 24
Finished Feb 07 02:28:55 PM PST 24
Peak memory 250132 kb
Host smart-db3e284f-c129-462a-96be-1f0975ac5281
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377433759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1377433759
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2282937907
Short name T1435
Test name
Test status
Simulation time 9400094370 ps
CPU time 432.45 seconds
Started Feb 07 02:28:37 PM PST 24
Finished Feb 07 02:35:50 PM PST 24
Peak memory 1271808 kb
Host smart-6322f352-8166-4fdf-ab46-fdb47088c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282937907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2282937907
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.418859471
Short name T325
Test name
Test status
Simulation time 4384173445 ps
CPU time 57.66 seconds
Started Feb 07 02:29:01 PM PST 24
Finished Feb 07 02:30:00 PM PST 24
Peak memory 293328 kb
Host smart-33caff0d-f1bc-491b-93bf-386d7c108a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418859471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.418859471
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.4215972419
Short name T6
Test name
Test status
Simulation time 27710653 ps
CPU time 0.63 seconds
Started Feb 07 02:28:38 PM PST 24
Finished Feb 07 02:28:39 PM PST 24
Peak memory 202560 kb
Host smart-19a6c2d3-f97a-4eef-b7a2-53ac755b4cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215972419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.4215972419
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.163252552
Short name T1398
Test name
Test status
Simulation time 2788578860 ps
CPU time 83.36 seconds
Started Feb 07 02:28:37 PM PST 24
Finished Feb 07 02:30:02 PM PST 24
Peak memory 248188 kb
Host smart-969d3260-e778-4b50-8219-a513dc1c8f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163252552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.163252552
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.3650870470
Short name T452
Test name
Test status
Simulation time 9483518710 ps
CPU time 117.15 seconds
Started Feb 07 02:28:41 PM PST 24
Finished Feb 07 02:30:39 PM PST 24
Peak memory 314820 kb
Host smart-a4f58c1c-9321-470e-aaa2-d8d070696719
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650870470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample
.3650870470
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.253551442
Short name T963
Test name
Test status
Simulation time 2050442470 ps
CPU time 53.87 seconds
Started Feb 07 02:28:39 PM PST 24
Finished Feb 07 02:29:34 PM PST 24
Peak memory 219980 kb
Host smart-028f4407-abcc-4ce7-8b78-835d6a783ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253551442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.253551442
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.4005945500
Short name T1149
Test name
Test status
Simulation time 10123591273 ps
CPU time 977.76 seconds
Started Feb 07 02:28:40 PM PST 24
Finished Feb 07 02:44:59 PM PST 24
Peak memory 1577332 kb
Host smart-28b6e765-b92f-4e90-9367-af65d879bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005945500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.4005945500
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1301207742
Short name T1305
Test name
Test status
Simulation time 2044116869 ps
CPU time 11.95 seconds
Started Feb 07 02:28:46 PM PST 24
Finished Feb 07 02:28:58 PM PST 24
Peak memory 214100 kb
Host smart-54a9c3f0-b80d-42dd-9817-c9c28584f593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301207742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1301207742
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1595029745
Short name T679
Test name
Test status
Simulation time 2960620210 ps
CPU time 5.33 seconds
Started Feb 07 02:28:53 PM PST 24
Finished Feb 07 02:28:59 PM PST 24
Peak memory 203772 kb
Host smart-84c7a61b-fbf7-417d-a2cb-1a068962a3d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595029745 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1595029745
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.111389382
Short name T268
Test name
Test status
Simulation time 10863253147 ps
CPU time 10.82 seconds
Started Feb 07 02:28:55 PM PST 24
Finished Feb 07 02:29:07 PM PST 24
Peak memory 253124 kb
Host smart-cc9a34e4-dce0-4c75-af8e-6db2a4e8c723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111389382 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.111389382
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.845301496
Short name T588
Test name
Test status
Simulation time 11254630291 ps
CPU time 8.55 seconds
Started Feb 07 02:28:54 PM PST 24
Finished Feb 07 02:29:03 PM PST 24
Peak memory 287928 kb
Host smart-befea093-53a4-487f-b748-84885dca9b51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845301496 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.845301496
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1718982878
Short name T296
Test name
Test status
Simulation time 999882841 ps
CPU time 3.52 seconds
Started Feb 07 02:28:55 PM PST 24
Finished Feb 07 02:29:00 PM PST 24
Peak memory 203512 kb
Host smart-cfc114cc-1831-405c-9eb8-93467c76252a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718982878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1718982878
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.851086891
Short name T231
Test name
Test status
Simulation time 5725394304 ps
CPU time 5.21 seconds
Started Feb 07 02:28:42 PM PST 24
Finished Feb 07 02:28:49 PM PST 24
Peak memory 203652 kb
Host smart-34cb9195-57d2-4ec5-980e-eb69ad508052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851086891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_intr_smoke.851086891
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2915171394
Short name T1013
Test name
Test status
Simulation time 5092627712 ps
CPU time 19.32 seconds
Started Feb 07 02:28:55 PM PST 24
Finished Feb 07 02:29:15 PM PST 24
Peak memory 609884 kb
Host smart-195bb100-d732-4465-9054-dca69b9be97d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915171394 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2915171394
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.4062893109
Short name T254
Test name
Test status
Simulation time 1589808477 ps
CPU time 3.59 seconds
Started Feb 07 02:28:53 PM PST 24
Finished Feb 07 02:28:57 PM PST 24
Peak memory 203576 kb
Host smart-dc9b30d3-bd36-4693-92c8-f987141edbb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062893109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.4062893109
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.4100604448
Short name T931
Test name
Test status
Simulation time 7438478973 ps
CPU time 43.63 seconds
Started Feb 07 02:28:40 PM PST 24
Finished Feb 07 02:29:24 PM PST 24
Peak memory 203756 kb
Host smart-c5d7a0bf-ea1e-47d9-9801-66a9514a2083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100604448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.4100604448
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.3556502581
Short name T667
Test name
Test status
Simulation time 35165078131 ps
CPU time 336.6 seconds
Started Feb 07 02:29:14 PM PST 24
Finished Feb 07 02:34:51 PM PST 24
Peak memory 472584 kb
Host smart-e152fdfa-8f8a-4c74-bf9e-4a712e59f6a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556502581 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.3556502581
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1007041809
Short name T1497
Test name
Test status
Simulation time 4125733765 ps
CPU time 31.82 seconds
Started Feb 07 02:28:41 PM PST 24
Finished Feb 07 02:29:14 PM PST 24
Peak memory 220396 kb
Host smart-49a251a0-6044-45d7-861c-06ebef1c4ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007041809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1007041809
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2001197127
Short name T1002
Test name
Test status
Simulation time 7669862632 ps
CPU time 17.43 seconds
Started Feb 07 02:28:42 PM PST 24
Finished Feb 07 02:29:01 PM PST 24
Peak memory 539560 kb
Host smart-48d22a17-a30b-4445-8b50-5da51d236e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001197127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2001197127
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2467705692
Short name T601
Test name
Test status
Simulation time 1397394428 ps
CPU time 6.46 seconds
Started Feb 07 02:28:54 PM PST 24
Finished Feb 07 02:29:01 PM PST 24
Peak memory 212816 kb
Host smart-51ecb245-ebd6-440a-b6e6-9163875e97cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467705692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2467705692
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_ovf.3816926430
Short name T431
Test name
Test status
Simulation time 10026635982 ps
CPU time 58.99 seconds
Started Feb 07 02:28:55 PM PST 24
Finished Feb 07 02:29:55 PM PST 24
Peak memory 305512 kb
Host smart-1c1de4aa-9d91-41e6-97cb-dcc4734becbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816926430 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_tx_ovf.3816926430
Directory /workspace/45.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.1751778436
Short name T1444
Test name
Test status
Simulation time 975351196 ps
CPU time 5.01 seconds
Started Feb 07 02:28:54 PM PST 24
Finished Feb 07 02:29:00 PM PST 24
Peak memory 204360 kb
Host smart-90e312ef-659a-4bef-9d2c-d903fd98bf54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751778436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.1751778436
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.4247160181
Short name T1323
Test name
Test status
Simulation time 15879799 ps
CPU time 0.6 seconds
Started Feb 07 02:29:10 PM PST 24
Finished Feb 07 02:29:11 PM PST 24
Peak memory 203276 kb
Host smart-cdf66f5a-b262-4e95-ad94-292730f6853d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247160181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.4247160181
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3601106781
Short name T402
Test name
Test status
Simulation time 28990732 ps
CPU time 1.16 seconds
Started Feb 07 02:29:03 PM PST 24
Finished Feb 07 02:29:06 PM PST 24
Peak memory 203684 kb
Host smart-5a01e36c-f588-4adb-ac7e-afdba263a0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601106781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3601106781
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3481452702
Short name T1115
Test name
Test status
Simulation time 431905236 ps
CPU time 21.74 seconds
Started Feb 07 02:29:03 PM PST 24
Finished Feb 07 02:29:26 PM PST 24
Peak memory 289580 kb
Host smart-81aa70ab-b585-4488-8601-09be1bbaf794
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481452702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3481452702
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1491273553
Short name T1129
Test name
Test status
Simulation time 13505154980 ps
CPU time 212.93 seconds
Started Feb 07 02:29:02 PM PST 24
Finished Feb 07 02:32:35 PM PST 24
Peak memory 839592 kb
Host smart-8a00b29e-8fa4-4207-b21a-af07fb354c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491273553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1491273553
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.502228612
Short name T945
Test name
Test status
Simulation time 3161318601 ps
CPU time 282.32 seconds
Started Feb 07 02:29:05 PM PST 24
Finished Feb 07 02:33:48 PM PST 24
Peak memory 922444 kb
Host smart-d70eaa65-2f63-4f07-b61a-e330f3d5b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502228612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.502228612
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2703209370
Short name T840
Test name
Test status
Simulation time 924007754 ps
CPU time 0.97 seconds
Started Feb 07 02:29:03 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 203604 kb
Host smart-e1de46fe-23e3-402a-ad6b-19f008898be2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703209370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2703209370
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1569458656
Short name T1119
Test name
Test status
Simulation time 577223490 ps
CPU time 7.03 seconds
Started Feb 07 02:29:10 PM PST 24
Finished Feb 07 02:29:18 PM PST 24
Peak memory 261192 kb
Host smart-dd3b4a93-053a-4ec0-be2c-7c00736a153c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569458656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1569458656
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4067189086
Short name T1322
Test name
Test status
Simulation time 6716886791 ps
CPU time 357.46 seconds
Started Feb 07 02:29:04 PM PST 24
Finished Feb 07 02:35:02 PM PST 24
Peak memory 1843972 kb
Host smart-1cae103e-4abd-423b-a687-af44b76a791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067189086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4067189086
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.4170065435
Short name T1007
Test name
Test status
Simulation time 5764691128 ps
CPU time 79.4 seconds
Started Feb 07 02:29:12 PM PST 24
Finished Feb 07 02:30:32 PM PST 24
Peak memory 365168 kb
Host smart-c6fe26a5-c0c1-423d-8e28-32b3ed3cafef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170065435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.4170065435
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.1249357890
Short name T1248
Test name
Test status
Simulation time 19533626 ps
CPU time 0.63 seconds
Started Feb 07 02:29:03 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 202504 kb
Host smart-20d6ace4-a346-4495-b544-2fd227a102b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249357890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1249357890
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.4242696396
Short name T939
Test name
Test status
Simulation time 10681942032 ps
CPU time 170.44 seconds
Started Feb 07 02:29:02 PM PST 24
Finished Feb 07 02:31:53 PM PST 24
Peak memory 211912 kb
Host smart-30728fbd-6893-4471-986b-c35ae294e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242696396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.4242696396
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.1958145028
Short name T833
Test name
Test status
Simulation time 12681988198 ps
CPU time 117.57 seconds
Started Feb 07 02:29:04 PM PST 24
Finished Feb 07 02:31:03 PM PST 24
Peak memory 328640 kb
Host smart-6a515397-427c-444d-922e-ced430ffe854
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958145028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample
.1958145028
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3159523994
Short name T986
Test name
Test status
Simulation time 6064539216 ps
CPU time 174.82 seconds
Started Feb 07 02:29:11 PM PST 24
Finished Feb 07 02:32:07 PM PST 24
Peak memory 254116 kb
Host smart-1faa7a09-2d42-4521-9830-01059ba99f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159523994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3159523994
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.1941923579
Short name T12
Test name
Test status
Simulation time 79844576777 ps
CPU time 2947.62 seconds
Started Feb 07 02:29:04 PM PST 24
Finished Feb 07 03:18:13 PM PST 24
Peak memory 1978592 kb
Host smart-72e7f2cb-f6db-4069-af47-3fd7ae4fede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941923579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.1941923579
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2518809317
Short name T589
Test name
Test status
Simulation time 4350416365 ps
CPU time 18.77 seconds
Started Feb 07 02:29:12 PM PST 24
Finished Feb 07 02:29:31 PM PST 24
Peak memory 228140 kb
Host smart-4a142f85-a752-4641-a078-aa0e6ace034a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518809317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2518809317
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2558198316
Short name T1408
Test name
Test status
Simulation time 510791639 ps
CPU time 2.54 seconds
Started Feb 07 02:29:02 PM PST 24
Finished Feb 07 02:29:05 PM PST 24
Peak memory 203564 kb
Host smart-c4751518-2a43-4739-94cf-1e553db61e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558198316 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2558198316
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1335186299
Short name T1233
Test name
Test status
Simulation time 10254651297 ps
CPU time 11.23 seconds
Started Feb 07 02:29:02 PM PST 24
Finished Feb 07 02:29:14 PM PST 24
Peak memory 287408 kb
Host smart-adc557e6-2fab-4045-93e3-826af0a120fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335186299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1335186299
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1754780985
Short name T680
Test name
Test status
Simulation time 10356384492 ps
CPU time 12.43 seconds
Started Feb 07 02:29:04 PM PST 24
Finished Feb 07 02:29:17 PM PST 24
Peak memory 284148 kb
Host smart-baebc7f7-7376-4670-8be5-3f1ba3d72014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754780985 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1754780985
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.4252247889
Short name T1297
Test name
Test status
Simulation time 3063446021 ps
CPU time 1.99 seconds
Started Feb 07 02:29:12 PM PST 24
Finished Feb 07 02:29:15 PM PST 24
Peak memory 203700 kb
Host smart-22448ec9-0a44-4a1a-8946-934ced2b8587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252247889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.4252247889
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.853010583
Short name T733
Test name
Test status
Simulation time 956176266 ps
CPU time 4.31 seconds
Started Feb 07 02:29:02 PM PST 24
Finished Feb 07 02:29:08 PM PST 24
Peak memory 203584 kb
Host smart-2ee755e5-f4b8-4999-aceb-4ce0e58cc6d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853010583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.853010583
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1325909245
Short name T17
Test name
Test status
Simulation time 10563862624 ps
CPU time 71.69 seconds
Started Feb 07 02:29:04 PM PST 24
Finished Feb 07 02:30:16 PM PST 24
Peak memory 1204060 kb
Host smart-7d0b80ec-d1eb-4d01-9a95-cedc9016889b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325909245 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1325909245
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.3948857339
Short name T228
Test name
Test status
Simulation time 631068727 ps
CPU time 3.92 seconds
Started Feb 07 02:29:02 PM PST 24
Finished Feb 07 02:29:07 PM PST 24
Peak memory 203556 kb
Host smart-f0e4e597-a3d4-4f5e-b860-effce18899ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948857339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.3948857339
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1164117964
Short name T828
Test name
Test status
Simulation time 1174738342 ps
CPU time 10.34 seconds
Started Feb 07 02:29:03 PM PST 24
Finished Feb 07 02:29:15 PM PST 24
Peak memory 203624 kb
Host smart-edb5a452-e14a-4fd3-b2f6-ee8a22c136f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164117964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1164117964
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.189468081
Short name T168
Test name
Test status
Simulation time 48042321523 ps
CPU time 64.99 seconds
Started Feb 07 02:29:11 PM PST 24
Finished Feb 07 02:30:17 PM PST 24
Peak memory 220532 kb
Host smart-b0b187c9-c333-4e0b-b97f-0146c3f4f9cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189468081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_stress_all.189468081
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2682881547
Short name T1225
Test name
Test status
Simulation time 9616302552 ps
CPU time 44.67 seconds
Started Feb 07 02:29:13 PM PST 24
Finished Feb 07 02:29:58 PM PST 24
Peak memory 203712 kb
Host smart-4ec43ee4-f43f-4968-8d84-ae3c0bdfd596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682881547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2682881547
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.489808240
Short name T1142
Test name
Test status
Simulation time 47345717095 ps
CPU time 339.55 seconds
Started Feb 07 02:29:04 PM PST 24
Finished Feb 07 02:34:44 PM PST 24
Peak memory 3192552 kb
Host smart-b9d719e7-4476-4823-8f06-c64a45095199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489808240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.489808240
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3222221004
Short name T1337
Test name
Test status
Simulation time 9496784013 ps
CPU time 16.13 seconds
Started Feb 07 02:29:05 PM PST 24
Finished Feb 07 02:29:22 PM PST 24
Peak memory 321096 kb
Host smart-b03e5449-e110-426d-8467-84f1afb58417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222221004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3222221004
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2609907578
Short name T1242
Test name
Test status
Simulation time 4117735524 ps
CPU time 8.28 seconds
Started Feb 07 02:29:12 PM PST 24
Finished Feb 07 02:29:21 PM PST 24
Peak memory 211148 kb
Host smart-7dd9af8b-d25f-44a5-b749-2fc1f460aec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609907578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2609907578
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_ovf.3945280172
Short name T838
Test name
Test status
Simulation time 2383289525 ps
CPU time 30.15 seconds
Started Feb 07 02:29:03 PM PST 24
Finished Feb 07 02:29:35 PM PST 24
Peak memory 216292 kb
Host smart-98ac740d-4ad0-4289-bec3-01359c9c7d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945280172 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_tx_ovf.3945280172
Directory /workspace/46.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.2043538283
Short name T792
Test name
Test status
Simulation time 1520584932 ps
CPU time 7.28 seconds
Started Feb 07 02:29:16 PM PST 24
Finished Feb 07 02:29:24 PM PST 24
Peak memory 205380 kb
Host smart-98453770-13a7-4d7e-b4bb-d493a2b2efb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043538283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.2043538283
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3099111512
Short name T258
Test name
Test status
Simulation time 24477436 ps
CPU time 0.6 seconds
Started Feb 07 02:29:20 PM PST 24
Finished Feb 07 02:29:21 PM PST 24
Peak memory 203232 kb
Host smart-5ad6fc0f-6b37-4e90-9d04-da4594943031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099111512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3099111512
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2316082909
Short name T1474
Test name
Test status
Simulation time 162540614 ps
CPU time 1.36 seconds
Started Feb 07 02:29:14 PM PST 24
Finished Feb 07 02:29:16 PM PST 24
Peak memory 219944 kb
Host smart-a315277c-ec82-46ef-8c49-80adc429d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316082909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2316082909
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3980859744
Short name T1330
Test name
Test status
Simulation time 859250908 ps
CPU time 22.64 seconds
Started Feb 07 02:29:13 PM PST 24
Finished Feb 07 02:29:37 PM PST 24
Peak memory 293376 kb
Host smart-6806739f-a859-42bd-8e92-745bac796686
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980859744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3980859744
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1957591336
Short name T637
Test name
Test status
Simulation time 3785414710 ps
CPU time 321.41 seconds
Started Feb 07 02:29:10 PM PST 24
Finished Feb 07 02:34:33 PM PST 24
Peak memory 1107892 kb
Host smart-41edad0d-737a-4844-9720-c9c55e51af75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957591336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1957591336
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3985890916
Short name T928
Test name
Test status
Simulation time 13625888187 ps
CPU time 315.25 seconds
Started Feb 07 02:29:13 PM PST 24
Finished Feb 07 02:34:29 PM PST 24
Peak memory 983540 kb
Host smart-69b541dc-b641-4976-8a85-6d82f189a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985890916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3985890916
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1022154122
Short name T541
Test name
Test status
Simulation time 147428308 ps
CPU time 0.86 seconds
Started Feb 07 02:29:12 PM PST 24
Finished Feb 07 02:29:13 PM PST 24
Peak memory 203428 kb
Host smart-a07e037d-36ee-4255-b737-6943ba3c0ac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022154122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1022154122
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.546582509
Short name T1492
Test name
Test status
Simulation time 479641164 ps
CPU time 4.45 seconds
Started Feb 07 02:29:16 PM PST 24
Finished Feb 07 02:29:21 PM PST 24
Peak memory 233668 kb
Host smart-56ca70d5-3a9a-42a0-bcbc-f1c137f6d15b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546582509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
546582509
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.79522211
Short name T1533
Test name
Test status
Simulation time 22570182807 ps
CPU time 256.06 seconds
Started Feb 07 02:29:13 PM PST 24
Finished Feb 07 02:33:29 PM PST 24
Peak memory 1535164 kb
Host smart-7c03eba8-5d69-4146-aab2-f839b5e74ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79522211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.79522211
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2225372522
Short name T602
Test name
Test status
Simulation time 1934275215 ps
CPU time 60.78 seconds
Started Feb 07 02:29:17 PM PST 24
Finished Feb 07 02:30:19 PM PST 24
Peak memory 334460 kb
Host smart-6754d739-cdb4-46d4-bccb-6c31bd0f8dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225372522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2225372522
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.1453708016
Short name T538
Test name
Test status
Simulation time 49085212 ps
CPU time 0.61 seconds
Started Feb 07 02:29:14 PM PST 24
Finished Feb 07 02:29:15 PM PST 24
Peak memory 202584 kb
Host smart-df910ada-0da4-4f9c-a619-c0d9a7431ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453708016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1453708016
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3076658778
Short name T554
Test name
Test status
Simulation time 24754228324 ps
CPU time 152.73 seconds
Started Feb 07 02:29:16 PM PST 24
Finished Feb 07 02:31:49 PM PST 24
Peak memory 327284 kb
Host smart-2f91592b-6161-4de5-b653-15d957258fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076658778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3076658778
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.1530417958
Short name T259
Test name
Test status
Simulation time 12842593218 ps
CPU time 320.09 seconds
Started Feb 07 02:29:13 PM PST 24
Finished Feb 07 02:34:34 PM PST 24
Peak memory 324100 kb
Host smart-4add1557-eb02-41ac-8a9b-440f6e4b2e3b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530417958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample
.1530417958
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3423582403
Short name T1332
Test name
Test status
Simulation time 10960201180 ps
CPU time 122.25 seconds
Started Feb 07 02:29:14 PM PST 24
Finished Feb 07 02:31:17 PM PST 24
Peak memory 248552 kb
Host smart-88b1f846-89f2-4710-916a-83d1e66825cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423582403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3423582403
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3378147147
Short name T1085
Test name
Test status
Simulation time 46748165767 ps
CPU time 1220.7 seconds
Started Feb 07 02:29:14 PM PST 24
Finished Feb 07 02:49:35 PM PST 24
Peak memory 2213476 kb
Host smart-5067986b-8760-46bd-9f21-8616c5663d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378147147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3378147147
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.505415451
Short name T1470
Test name
Test status
Simulation time 3941693568 ps
CPU time 11.55 seconds
Started Feb 07 02:29:16 PM PST 24
Finished Feb 07 02:29:28 PM PST 24
Peak memory 220196 kb
Host smart-5b2af8b4-8497-4689-ad7c-d6e544d4cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505415451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.505415451
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.617946951
Short name T1046
Test name
Test status
Simulation time 1198611195 ps
CPU time 4.07 seconds
Started Feb 07 02:29:25 PM PST 24
Finished Feb 07 02:29:29 PM PST 24
Peak memory 203636 kb
Host smart-2f414d4f-8f96-468c-8ffc-eea79e795f7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617946951 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.617946951
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2097568348
Short name T889
Test name
Test status
Simulation time 10050541524 ps
CPU time 62.77 seconds
Started Feb 07 02:29:18 PM PST 24
Finished Feb 07 02:30:21 PM PST 24
Peak memory 543528 kb
Host smart-4c5d0ab3-23d7-422b-9da5-2c8213207652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097568348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2097568348
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.788472520
Short name T786
Test name
Test status
Simulation time 10377500586 ps
CPU time 19.19 seconds
Started Feb 07 02:29:24 PM PST 24
Finished Feb 07 02:29:44 PM PST 24
Peak memory 331552 kb
Host smart-fb3a2464-621a-4885-8b78-a3ac74e68398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788472520 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.788472520
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.865707106
Short name T413
Test name
Test status
Simulation time 622033002 ps
CPU time 2.97 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:29:22 PM PST 24
Peak memory 203564 kb
Host smart-00006417-5702-4f0c-9da7-82cdf914427f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865707106 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.865707106
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.4113852612
Short name T1348
Test name
Test status
Simulation time 1717526161 ps
CPU time 3.67 seconds
Started Feb 07 02:29:18 PM PST 24
Finished Feb 07 02:29:22 PM PST 24
Peak memory 203652 kb
Host smart-04033b08-2540-4c62-85ec-f22a90f7f84d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113852612 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.4113852612
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1382140442
Short name T162
Test name
Test status
Simulation time 21424193664 ps
CPU time 310.19 seconds
Started Feb 07 02:29:21 PM PST 24
Finished Feb 07 02:34:32 PM PST 24
Peak memory 2601140 kb
Host smart-49fc4997-acd8-4b27-afde-ee3c6279d8bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382140442 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1382140442
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.1629011267
Short name T386
Test name
Test status
Simulation time 1467240977 ps
CPU time 4.38 seconds
Started Feb 07 02:29:20 PM PST 24
Finished Feb 07 02:29:25 PM PST 24
Peak memory 203616 kb
Host smart-ab863fa4-690e-456d-a334-666a1d1deb67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629011267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.1629011267
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2585540307
Short name T1534
Test name
Test status
Simulation time 1171451920 ps
CPU time 15.26 seconds
Started Feb 07 02:29:17 PM PST 24
Finished Feb 07 02:29:33 PM PST 24
Peak memory 203608 kb
Host smart-d34397b8-6c55-4550-aa21-8ad089019a86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585540307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2585540307
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.1479394233
Short name T474
Test name
Test status
Simulation time 110036567342 ps
CPU time 622.6 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:39:42 PM PST 24
Peak memory 798488 kb
Host smart-30606380-b927-4965-a5b0-92ac37f7fc82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479394233 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.1479394233
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1714663363
Short name T1381
Test name
Test status
Simulation time 3028775586 ps
CPU time 62.27 seconds
Started Feb 07 02:29:11 PM PST 24
Finished Feb 07 02:30:14 PM PST 24
Peak memory 203732 kb
Host smart-2f824fe2-d0d4-4906-9bd9-30b9b88ad9c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714663363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1714663363
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.3585613371
Short name T1185
Test name
Test status
Simulation time 65607197528 ps
CPU time 1814.69 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:59:35 PM PST 24
Peak memory 7787184 kb
Host smart-0be93a4e-0e30-40e8-b36f-70bd92110dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585613371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.3585613371
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3724064544
Short name T207
Test name
Test status
Simulation time 16636988405 ps
CPU time 296 seconds
Started Feb 07 02:29:13 PM PST 24
Finished Feb 07 02:34:10 PM PST 24
Peak memory 1031004 kb
Host smart-04d959b2-b3d3-4f15-b902-3506643f927c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724064544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3724064544
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1150946508
Short name T919
Test name
Test status
Simulation time 5688161696 ps
CPU time 7.14 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:29:27 PM PST 24
Peak memory 203688 kb
Host smart-030b3ae2-f75a-43f7-952c-b2f53841505d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150946508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1150946508
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_ovf.2593797630
Short name T1296
Test name
Test status
Simulation time 5504627421 ps
CPU time 103.38 seconds
Started Feb 07 02:29:24 PM PST 24
Finished Feb 07 02:31:08 PM PST 24
Peak memory 341744 kb
Host smart-3e2d9a0a-2b84-47a2-8040-4875533ed04b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593797630 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_tx_ovf.2593797630
Directory /workspace/47.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.209670891
Short name T591
Test name
Test status
Simulation time 6046983706 ps
CPU time 6.69 seconds
Started Feb 07 02:29:18 PM PST 24
Finished Feb 07 02:29:25 PM PST 24
Peak memory 203756 kb
Host smart-9c1762e2-e629-4540-b66f-e1bbef0bb6fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209670891 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_unexp_stop.209670891
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1221459305
Short name T90
Test name
Test status
Simulation time 19137318 ps
CPU time 0.62 seconds
Started Feb 07 02:29:47 PM PST 24
Finished Feb 07 02:29:53 PM PST 24
Peak memory 202388 kb
Host smart-0d980187-59d9-4c8e-abc1-cccfff34e92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221459305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1221459305
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3506998552
Short name T1472
Test name
Test status
Simulation time 50293218 ps
CPU time 1.61 seconds
Started Feb 07 02:29:31 PM PST 24
Finished Feb 07 02:29:33 PM PST 24
Peak memory 219800 kb
Host smart-7e2c74cc-52fc-49a5-99bc-2c9beb2b4069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506998552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3506998552
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.474142563
Short name T518
Test name
Test status
Simulation time 356600379 ps
CPU time 7.01 seconds
Started Feb 07 02:29:20 PM PST 24
Finished Feb 07 02:29:27 PM PST 24
Peak memory 263504 kb
Host smart-561a8160-bc50-4b37-8028-35e33b7a5942
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474142563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.474142563
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2104560550
Short name T400
Test name
Test status
Simulation time 2626145381 ps
CPU time 82.64 seconds
Started Feb 07 02:29:20 PM PST 24
Finished Feb 07 02:30:43 PM PST 24
Peak memory 686080 kb
Host smart-e1cc79de-0605-4ff7-9efd-9593c307b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104560550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2104560550
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1421961360
Short name T255
Test name
Test status
Simulation time 4419148815 ps
CPU time 222.75 seconds
Started Feb 07 02:29:18 PM PST 24
Finished Feb 07 02:33:02 PM PST 24
Peak memory 1241388 kb
Host smart-79be7c70-374e-471d-ae9b-23ec5b7565a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421961360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1421961360
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2996645600
Short name T841
Test name
Test status
Simulation time 71419039 ps
CPU time 0.78 seconds
Started Feb 07 02:29:20 PM PST 24
Finished Feb 07 02:29:22 PM PST 24
Peak memory 203344 kb
Host smart-d49bf8bd-9efc-4b9d-85f5-19a60643618a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996645600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2996645600
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.357759489
Short name T257
Test name
Test status
Simulation time 1812940249 ps
CPU time 12.09 seconds
Started Feb 07 02:29:24 PM PST 24
Finished Feb 07 02:29:37 PM PST 24
Peak memory 244072 kb
Host smart-7d4687e2-f6c4-499f-8ec9-528f7fc34d93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357759489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
357759489
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4066597874
Short name T1163
Test name
Test status
Simulation time 62448542262 ps
CPU time 265.47 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:33:45 PM PST 24
Peak memory 1637996 kb
Host smart-d49e7d0b-a9fd-42b3-94f2-2db58f0575e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066597874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4066597874
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1079306079
Short name T813
Test name
Test status
Simulation time 2270617905 ps
CPU time 117.24 seconds
Started Feb 07 02:29:49 PM PST 24
Finished Feb 07 02:31:50 PM PST 24
Peak memory 259176 kb
Host smart-8ec1c134-216e-42b9-aa5e-5c3b0e2116f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079306079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1079306079
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3835011358
Short name T1058
Test name
Test status
Simulation time 41503226 ps
CPU time 0.62 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:29:20 PM PST 24
Peak memory 202616 kb
Host smart-f82efcf3-daec-4af2-82d5-fe9a5b981041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835011358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3835011358
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3666756910
Short name T370
Test name
Test status
Simulation time 12644390808 ps
CPU time 662.13 seconds
Started Feb 07 02:29:29 PM PST 24
Finished Feb 07 02:40:32 PM PST 24
Peak memory 248448 kb
Host smart-19e89093-14d1-4e87-ab20-6c34cf74ca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666756910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3666756910
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.3207081945
Short name T694
Test name
Test status
Simulation time 4709761306 ps
CPU time 187.32 seconds
Started Feb 07 02:29:20 PM PST 24
Finished Feb 07 02:32:28 PM PST 24
Peak memory 279240 kb
Host smart-4e2c19f7-2ac6-4471-b03d-af6ecffe0992
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207081945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample
.3207081945
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1734988366
Short name T1260
Test name
Test status
Simulation time 1813673061 ps
CPU time 49.14 seconds
Started Feb 07 02:29:19 PM PST 24
Finished Feb 07 02:30:09 PM PST 24
Peak memory 321672 kb
Host smart-7fa9b250-678d-476e-839d-541fe8b5aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734988366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1734988366
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2513040479
Short name T937
Test name
Test status
Simulation time 690704387 ps
CPU time 9.89 seconds
Started Feb 07 02:29:29 PM PST 24
Finished Feb 07 02:29:40 PM PST 24
Peak memory 211828 kb
Host smart-e5da1223-9a74-4698-b462-0771e00ee5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513040479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2513040479
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1593715220
Short name T1226
Test name
Test status
Simulation time 4570754583 ps
CPU time 4.41 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:29:56 PM PST 24
Peak memory 203712 kb
Host smart-4c3b5cd2-dac8-408c-9b85-18e240928efc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593715220 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1593715220
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3995235300
Short name T765
Test name
Test status
Simulation time 10102711885 ps
CPU time 49.44 seconds
Started Feb 07 02:29:47 PM PST 24
Finished Feb 07 02:30:37 PM PST 24
Peak memory 456176 kb
Host smart-86bdc73e-194a-46fc-90d9-f7f546de205e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995235300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3995235300
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4184680564
Short name T429
Test name
Test status
Simulation time 10147712025 ps
CPU time 26.72 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:30:19 PM PST 24
Peak memory 364648 kb
Host smart-3ac7d520-20b1-4637-8c6a-aa93c893f6ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184680564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4184680564
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3938777330
Short name T149
Test name
Test status
Simulation time 550343114 ps
CPU time 2.73 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:29:55 PM PST 24
Peak memory 203568 kb
Host smart-023fc5dd-95bc-4ddd-92ef-8b71ece2dd43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938777330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3938777330
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.818598936
Short name T728
Test name
Test status
Simulation time 6384445332 ps
CPU time 6.46 seconds
Started Feb 07 02:29:30 PM PST 24
Finished Feb 07 02:29:37 PM PST 24
Peak memory 203724 kb
Host smart-e4b89ccc-e275-4ab7-a5fa-e680c0a2b515
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818598936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.818598936
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1328975994
Short name T635
Test name
Test status
Simulation time 22016322015 ps
CPU time 1038.72 seconds
Started Feb 07 02:29:33 PM PST 24
Finished Feb 07 02:46:53 PM PST 24
Peak memory 5239448 kb
Host smart-b472be44-c15f-4c81-b57d-876ac820fc86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328975994 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1328975994
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.303571743
Short name T1428
Test name
Test status
Simulation time 474846711 ps
CPU time 2.9 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:29:55 PM PST 24
Peak memory 203604 kb
Host smart-8dc81369-8289-45d2-ac03-0f346c025510
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303571743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_perf.303571743
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1290538442
Short name T1107
Test name
Test status
Simulation time 5424396373 ps
CPU time 16.02 seconds
Started Feb 07 02:29:30 PM PST 24
Finished Feb 07 02:29:46 PM PST 24
Peak memory 203656 kb
Host smart-e18d5ed4-41e8-4c65-a807-5bbe37d4c1e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290538442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1290538442
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.2094454881
Short name T15
Test name
Test status
Simulation time 48628180803 ps
CPU time 976.07 seconds
Started Feb 07 02:29:50 PM PST 24
Finished Feb 07 02:46:09 PM PST 24
Peak memory 1006572 kb
Host smart-5826de4e-1dd4-4526-9b4b-079940fa9f6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094454881 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.2094454881
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.4127680696
Short name T547
Test name
Test status
Simulation time 7264606490 ps
CPU time 73.65 seconds
Started Feb 07 02:29:28 PM PST 24
Finished Feb 07 02:30:42 PM PST 24
Peak memory 204392 kb
Host smart-da3eb4af-5e7f-4da4-9300-72adfc028a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127680696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.4127680696
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.4084441944
Short name T303
Test name
Test status
Simulation time 25921818094 ps
CPU time 24.93 seconds
Started Feb 07 02:29:27 PM PST 24
Finished Feb 07 02:29:53 PM PST 24
Peak memory 637484 kb
Host smart-26a427e5-4730-4719-8f40-efe00b7237f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084441944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.4084441944
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3893996625
Short name T1224
Test name
Test status
Simulation time 35337975909 ps
CPU time 105.03 seconds
Started Feb 07 02:29:27 PM PST 24
Finished Feb 07 02:31:13 PM PST 24
Peak memory 945132 kb
Host smart-94b68e39-61eb-4ecd-94fa-4eba3a2a8973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893996625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3893996625
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1278496308
Short name T1476
Test name
Test status
Simulation time 2016287269 ps
CPU time 7.56 seconds
Started Feb 07 02:29:28 PM PST 24
Finished Feb 07 02:29:36 PM PST 24
Peak memory 203632 kb
Host smart-2177ac6f-8b78-4e74-a09b-77e2d1dfaaa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278496308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1278496308
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_ovf.287924867
Short name T253
Test name
Test status
Simulation time 4104172025 ps
CPU time 46.65 seconds
Started Feb 07 02:29:28 PM PST 24
Finished Feb 07 02:30:15 PM PST 24
Peak memory 235804 kb
Host smart-5125014d-b6c0-42a8-bd8f-81076f3923fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287924867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_tx_ovf.287924867
Directory /workspace/48.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.2587483139
Short name T1339
Test name
Test status
Simulation time 3931714795 ps
CPU time 6.28 seconds
Started Feb 07 02:29:47 PM PST 24
Finished Feb 07 02:29:57 PM PST 24
Peak memory 203808 kb
Host smart-98753125-9139-4ef1-ac79-24dfec1d8ef9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587483139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.2587483139
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.16727399
Short name T590
Test name
Test status
Simulation time 18355109 ps
CPU time 0.6 seconds
Started Feb 07 02:30:04 PM PST 24
Finished Feb 07 02:30:11 PM PST 24
Peak memory 203192 kb
Host smart-c019584b-b6be-4d79-978d-1943abe2731d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16727399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.16727399
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2178351058
Short name T1376
Test name
Test status
Simulation time 33875903 ps
CPU time 1.16 seconds
Started Feb 07 02:29:58 PM PST 24
Finished Feb 07 02:29:59 PM PST 24
Peak memory 211840 kb
Host smart-23864666-897c-4ba7-b7d2-45faea4d9f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178351058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2178351058
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2041607282
Short name T1191
Test name
Test status
Simulation time 257558506 ps
CPU time 5.01 seconds
Started Feb 07 02:29:49 PM PST 24
Finished Feb 07 02:29:57 PM PST 24
Peak memory 230832 kb
Host smart-2148a490-fb90-41b4-8bb0-ba6609155f0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041607282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2041607282
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.828332815
Short name T1271
Test name
Test status
Simulation time 2995767038 ps
CPU time 106.57 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:31:39 PM PST 24
Peak memory 854544 kb
Host smart-34894409-f63f-4f25-8977-dd06e3929f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828332815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.828332815
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.16976273
Short name T388
Test name
Test status
Simulation time 12307430266 ps
CPU time 321.81 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:35:14 PM PST 24
Peak memory 1612004 kb
Host smart-4fa9d212-15e0-4360-a3b2-8ee48b5c1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16976273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.16976273
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2763152691
Short name T643
Test name
Test status
Simulation time 495229522 ps
CPU time 0.94 seconds
Started Feb 07 02:29:50 PM PST 24
Finished Feb 07 02:29:53 PM PST 24
Peak memory 203464 kb
Host smart-5f687aee-4458-45a5-8c29-30a5adf57ba7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763152691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2763152691
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3502533922
Short name T525
Test name
Test status
Simulation time 651561807 ps
CPU time 9.32 seconds
Started Feb 07 02:29:58 PM PST 24
Finished Feb 07 02:30:09 PM PST 24
Peak memory 203620 kb
Host smart-0e7a772a-8b57-4573-9787-919e64c344f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502533922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3502533922
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1845148108
Short name T1340
Test name
Test status
Simulation time 17611294740 ps
CPU time 413.16 seconds
Started Feb 07 02:29:57 PM PST 24
Finished Feb 07 02:36:51 PM PST 24
Peak memory 1258960 kb
Host smart-06721eea-577a-4771-9bfc-9997d645e818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845148108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1845148108
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3590591327
Short name T803
Test name
Test status
Simulation time 6589269756 ps
CPU time 91.3 seconds
Started Feb 07 02:30:04 PM PST 24
Finished Feb 07 02:31:42 PM PST 24
Peak memory 234020 kb
Host smart-6a948c62-dc87-430e-a087-5c0c1dc30cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590591327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3590591327
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.821570686
Short name T1412
Test name
Test status
Simulation time 30448780 ps
CPU time 0.63 seconds
Started Feb 07 02:29:55 PM PST 24
Finished Feb 07 02:29:57 PM PST 24
Peak memory 202644 kb
Host smart-5c1c7736-664e-406e-b53e-8de824a5964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821570686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.821570686
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.607044302
Short name T887
Test name
Test status
Simulation time 3513138389 ps
CPU time 16.93 seconds
Started Feb 07 02:29:50 PM PST 24
Finished Feb 07 02:30:09 PM PST 24
Peak memory 228228 kb
Host smart-82b751a0-b834-45ea-b199-c7e11e0d46b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607044302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.607044302
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.3052100353
Short name T99
Test name
Test status
Simulation time 2669962606 ps
CPU time 85.81 seconds
Started Feb 07 02:29:56 PM PST 24
Finished Feb 07 02:31:23 PM PST 24
Peak memory 244588 kb
Host smart-3085a36f-312c-4f56-b802-9858a3052bec
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052100353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample
.3052100353
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.262808258
Short name T507
Test name
Test status
Simulation time 2381264320 ps
CPU time 57.29 seconds
Started Feb 07 02:29:50 PM PST 24
Finished Feb 07 02:30:50 PM PST 24
Peak memory 277084 kb
Host smart-2eecb697-b18b-47c8-8943-7b448cac5482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262808258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.262808258
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.3599769367
Short name T748
Test name
Test status
Simulation time 23568205350 ps
CPU time 963.23 seconds
Started Feb 07 02:29:54 PM PST 24
Finished Feb 07 02:46:00 PM PST 24
Peak memory 1796032 kb
Host smart-3dc0fb18-eca5-4fc0-946d-3ff0850c289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599769367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.3599769367
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.1230528076
Short name T399
Test name
Test status
Simulation time 4262337575 ps
CPU time 17.83 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:30:10 PM PST 24
Peak memory 219832 kb
Host smart-fed78b9f-fe9e-482e-9b94-784d7e5b21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230528076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.1230528076
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1206270072
Short name T1231
Test name
Test status
Simulation time 964009438 ps
CPU time 3.95 seconds
Started Feb 07 02:30:03 PM PST 24
Finished Feb 07 02:30:14 PM PST 24
Peak memory 203696 kb
Host smart-31d9764e-2894-4aa9-a017-43a9baef5cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206270072 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1206270072
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2199947862
Short name T614
Test name
Test status
Simulation time 10212234133 ps
CPU time 12.54 seconds
Started Feb 07 02:29:56 PM PST 24
Finished Feb 07 02:30:09 PM PST 24
Peak memory 295088 kb
Host smart-cb322b40-1074-4049-a5a6-7d86430bb117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199947862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2199947862
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2312402083
Short name T1254
Test name
Test status
Simulation time 10152304257 ps
CPU time 25.91 seconds
Started Feb 07 02:30:03 PM PST 24
Finished Feb 07 02:30:36 PM PST 24
Peak memory 373000 kb
Host smart-a53974e9-3668-478b-b997-848477544fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312402083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2312402083
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.3653806628
Short name T650
Test name
Test status
Simulation time 599293222 ps
CPU time 2.95 seconds
Started Feb 07 02:30:06 PM PST 24
Finished Feb 07 02:30:14 PM PST 24
Peak memory 203668 kb
Host smart-3937959e-a1b7-45d7-91c9-36896868c215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653806628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.3653806628
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2884439047
Short name T312
Test name
Test status
Simulation time 806956616 ps
CPU time 4 seconds
Started Feb 07 02:29:57 PM PST 24
Finished Feb 07 02:30:02 PM PST 24
Peak memory 203744 kb
Host smart-65e32507-67c0-4156-8383-165a76350904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884439047 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2884439047
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2030571102
Short name T264
Test name
Test status
Simulation time 15300700568 ps
CPU time 76.24 seconds
Started Feb 07 02:30:01 PM PST 24
Finished Feb 07 02:31:22 PM PST 24
Peak memory 954264 kb
Host smart-2ab56699-40e9-4d49-be24-4ca838d701c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030571102 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2030571102
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.2636168064
Short name T1232
Test name
Test status
Simulation time 3341397236 ps
CPU time 4.45 seconds
Started Feb 07 02:30:09 PM PST 24
Finished Feb 07 02:30:18 PM PST 24
Peak memory 206872 kb
Host smart-6d25cc9a-424c-403f-9524-7e5e0e6424bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636168064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.2636168064
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2719094944
Short name T291
Test name
Test status
Simulation time 929919052 ps
CPU time 23.51 seconds
Started Feb 07 02:29:57 PM PST 24
Finished Feb 07 02:30:21 PM PST 24
Peak memory 203540 kb
Host smart-eec844ef-36d3-4922-b1a4-6c2c8b7d1222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719094944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2719094944
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.981660602
Short name T800
Test name
Test status
Simulation time 13249924695 ps
CPU time 1087.68 seconds
Started Feb 07 02:30:03 PM PST 24
Finished Feb 07 02:48:18 PM PST 24
Peak memory 1840232 kb
Host smart-1223e771-8cd7-464c-a306-c107a2110d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981660602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.981660602
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1425525069
Short name T1431
Test name
Test status
Simulation time 371079029 ps
CPU time 6.53 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:29:59 PM PST 24
Peak memory 203580 kb
Host smart-7d94cb97-039d-4445-b794-5e4729cf1585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425525069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1425525069
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2980665918
Short name T802
Test name
Test status
Simulation time 49946907736 ps
CPU time 2717.63 seconds
Started Feb 07 02:29:49 PM PST 24
Finished Feb 07 03:15:10 PM PST 24
Peak memory 11374044 kb
Host smart-58fa86fe-bed2-42e7-aee8-f06d764c8991
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980665918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2980665918
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1027685529
Short name T577
Test name
Test status
Simulation time 44548964789 ps
CPU time 942.46 seconds
Started Feb 07 02:29:48 PM PST 24
Finished Feb 07 02:45:35 PM PST 24
Peak memory 2214036 kb
Host smart-f27df807-a5e2-4feb-89f5-2053cf6af0eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027685529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1027685529
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.646956109
Short name T645
Test name
Test status
Simulation time 5414651142 ps
CPU time 5.74 seconds
Started Feb 07 02:29:49 PM PST 24
Finished Feb 07 02:29:58 PM PST 24
Peak memory 203704 kb
Host smart-482a1caa-17cd-4843-ae9b-d986c68b5794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646956109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.646956109
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_ovf.1323253778
Short name T791
Test name
Test status
Simulation time 2906853146 ps
CPU time 147.99 seconds
Started Feb 07 02:29:51 PM PST 24
Finished Feb 07 02:32:21 PM PST 24
Peak memory 408968 kb
Host smart-c4301270-41ed-4ee4-8d83-33d6a2a4028e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323253778 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_tx_ovf.1323253778
Directory /workspace/49.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.14579768
Short name T534
Test name
Test status
Simulation time 5723604370 ps
CPU time 6.32 seconds
Started Feb 07 02:29:51 PM PST 24
Finished Feb 07 02:29:59 PM PST 24
Peak memory 207628 kb
Host smart-5fa23f0c-b152-4487-889b-dd5ffd94ae41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14579768 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_unexp_stop.14579768
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3723606560
Short name T1134
Test name
Test status
Simulation time 32096699 ps
CPU time 0.59 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 202408 kb
Host smart-06762f9d-bf80-4a25-a892-07755e5f691f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723606560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3723606560
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1355554158
Short name T1184
Test name
Test status
Simulation time 42682825 ps
CPU time 1.22 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:19:20 PM PST 24
Peak memory 219720 kb
Host smart-ff1e324e-fe96-4497-a5e3-ef94eeda3d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355554158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1355554158
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.62950643
Short name T1200
Test name
Test status
Simulation time 335657888 ps
CPU time 6.32 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:19:25 PM PST 24
Peak memory 240344 kb
Host smart-8fc66793-cfbc-41b3-a0b2-dfe35536525e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62950643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.62950643
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2568712366
Short name T599
Test name
Test status
Simulation time 6336107712 ps
CPU time 263.58 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:23:42 PM PST 24
Peak memory 976464 kb
Host smart-c996eb91-c5a0-4fa2-b846-1d0c9ea16e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568712366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2568712366
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3949217019
Short name T418
Test name
Test status
Simulation time 13806733547 ps
CPU time 159.94 seconds
Started Feb 07 02:19:17 PM PST 24
Finished Feb 07 02:21:59 PM PST 24
Peak memory 1015540 kb
Host smart-8da03cfe-2a05-4e7f-a7a6-f3efc7296abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949217019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3949217019
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2743930359
Short name T1131
Test name
Test status
Simulation time 273760206 ps
CPU time 0.85 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:19:19 PM PST 24
Peak memory 203376 kb
Host smart-3e12047a-63f2-46bd-94da-b0c01ef99d77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743930359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2743930359
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2336356188
Short name T628
Test name
Test status
Simulation time 288219484 ps
CPU time 8.82 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:30 PM PST 24
Peak memory 228700 kb
Host smart-44442dc8-af93-4402-bf22-901f82ca4437
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336356188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2336356188
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.4008973159
Short name T200
Test name
Test status
Simulation time 24014890485 ps
CPU time 611.46 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:29:30 PM PST 24
Peak memory 1586204 kb
Host smart-e75aa91d-79d5-4204-8ac1-950e78206193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008973159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.4008973159
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1895699090
Short name T32
Test name
Test status
Simulation time 2687963926 ps
CPU time 153.09 seconds
Started Feb 07 02:19:17 PM PST 24
Finished Feb 07 02:21:52 PM PST 24
Peak memory 254892 kb
Host smart-7fa27262-e2e8-40bd-9eb1-f6eae1044538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895699090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1895699090
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2140045982
Short name T617
Test name
Test status
Simulation time 16053116 ps
CPU time 0.66 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:19:19 PM PST 24
Peak memory 202560 kb
Host smart-5f799326-0fb2-407a-b012-141e18f932a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140045982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2140045982
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.504132866
Short name T811
Test name
Test status
Simulation time 2568110875 ps
CPU time 128.26 seconds
Started Feb 07 02:19:17 PM PST 24
Finished Feb 07 02:21:27 PM PST 24
Peak memory 221200 kb
Host smart-ab8b503d-b5d5-448a-a4d2-cbb75358eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504132866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.504132866
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.3328086814
Short name T224
Test name
Test status
Simulation time 5026387897 ps
CPU time 81.36 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:20:39 PM PST 24
Peak memory 244572 kb
Host smart-a6e70730-10f1-47bb-ace9-52ead1c27825
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328086814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.
3328086814
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2285543465
Short name T638
Test name
Test status
Simulation time 5334336038 ps
CPU time 32.34 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:19:56 PM PST 24
Peak memory 300516 kb
Host smart-e99961bc-b64d-43b6-a910-a101847b5dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285543465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2285543465
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2727294315
Short name T723
Test name
Test status
Simulation time 775018260 ps
CPU time 36.45 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:20:02 PM PST 24
Peak memory 211844 kb
Host smart-402d9760-9f3a-4bd7-8500-eccfbd613b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727294315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2727294315
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2754151821
Short name T861
Test name
Test status
Simulation time 3808265938 ps
CPU time 3.9 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:19:18 PM PST 24
Peak memory 203688 kb
Host smart-27bafe66-61cd-4670-a39b-ff7cb0c097ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754151821 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2754151821
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3330522194
Short name T16
Test name
Test status
Simulation time 10215298452 ps
CPU time 31.12 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:54 PM PST 24
Peak memory 427304 kb
Host smart-2208fc66-c791-45eb-ae4f-0637f5721485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330522194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3330522194
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2974534450
Short name T1212
Test name
Test status
Simulation time 10141267993 ps
CPU time 26.76 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:19:41 PM PST 24
Peak memory 406716 kb
Host smart-a27430a3-7b11-459a-aee6-f99bbaf0b273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974534450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2974534450
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3937845514
Short name T156
Test name
Test status
Simulation time 483967781 ps
CPU time 2.53 seconds
Started Feb 07 02:19:10 PM PST 24
Finished Feb 07 02:19:17 PM PST 24
Peak memory 203580 kb
Host smart-13e875c9-d67d-4cbc-b1a3-63c9e0622ea3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937845514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3937845514
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3365144456
Short name T1462
Test name
Test status
Simulation time 9101346748 ps
CPU time 6.7 seconds
Started Feb 07 02:19:18 PM PST 24
Finished Feb 07 02:19:26 PM PST 24
Peak memory 203756 kb
Host smart-ff75a4da-ad25-4b21-93d4-a430c50ad757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365144456 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3365144456
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.4207249030
Short name T1521
Test name
Test status
Simulation time 4587855541 ps
CPU time 14.19 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:19:32 PM PST 24
Peak memory 514288 kb
Host smart-b10effc3-d60f-4118-bf8e-0cb7c0a61f68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207249030 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.4207249030
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.3912454202
Short name T276
Test name
Test status
Simulation time 801578617 ps
CPU time 3.93 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:19:27 PM PST 24
Peak memory 207036 kb
Host smart-9eceeaf1-217a-439a-aeae-ded6674ec7f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912454202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.3912454202
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2044218686
Short name T570
Test name
Test status
Simulation time 5571048399 ps
CPU time 37.81 seconds
Started Feb 07 02:19:17 PM PST 24
Finished Feb 07 02:19:57 PM PST 24
Peak memory 203692 kb
Host smart-cefbcb64-06ab-4288-86d9-bb1e10389d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044218686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2044218686
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.3122890779
Short name T698
Test name
Test status
Simulation time 48217674224 ps
CPU time 2507.75 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 03:01:03 PM PST 24
Peak memory 10320220 kb
Host smart-cd94fe8b-35f1-47a9-a178-02533af06fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122890779 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.3122890779
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3001197693
Short name T1146
Test name
Test status
Simulation time 4672024338 ps
CPU time 48.93 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:20:07 PM PST 24
Peak memory 203724 kb
Host smart-16f40baf-648a-473f-8e34-a04505ff0370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001197693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3001197693
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2059626927
Short name T1202
Test name
Test status
Simulation time 40529350694 ps
CPU time 318.61 seconds
Started Feb 07 02:19:18 PM PST 24
Finished Feb 07 02:24:39 PM PST 24
Peak memory 3045956 kb
Host smart-c2ab1311-ffe1-483f-b943-0b0f005849c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059626927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2059626927
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3517536883
Short name T453
Test name
Test status
Simulation time 34854795514 ps
CPU time 232.53 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:23:19 PM PST 24
Peak memory 1639312 kb
Host smart-1d1ad517-1438-478f-a5f4-c66b8f859846
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517536883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3517536883
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3288230740
Short name T852
Test name
Test status
Simulation time 3518949035 ps
CPU time 7.64 seconds
Started Feb 07 02:19:12 PM PST 24
Finished Feb 07 02:19:22 PM PST 24
Peak memory 214168 kb
Host smart-a6ed89e9-87c7-45a4-898c-37c1e3350ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288230740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3288230740
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_ovf.264486523
Short name T1439
Test name
Test status
Simulation time 4545835514 ps
CPU time 47.31 seconds
Started Feb 07 02:19:18 PM PST 24
Finished Feb 07 02:20:07 PM PST 24
Peak memory 232524 kb
Host smart-035b08c8-4582-47fe-a146-ad5498ac561f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264486523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_tx_ovf.264486523
Directory /workspace/5.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.1316457979
Short name T1513
Test name
Test status
Simulation time 2237168931 ps
CPU time 8.33 seconds
Started Feb 07 02:19:15 PM PST 24
Finished Feb 07 02:19:26 PM PST 24
Peak memory 213592 kb
Host smart-693edec2-9918-43de-a3e9-06e47b36f1ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316457979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.1316457979
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1234795494
Short name T1416
Test name
Test status
Simulation time 67652619 ps
CPU time 0.59 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:19:23 PM PST 24
Peak memory 202384 kb
Host smart-39add24a-144a-458e-806e-923442b8f28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234795494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1234795494
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1761113717
Short name T1466
Test name
Test status
Simulation time 195659725 ps
CPU time 1.52 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:23 PM PST 24
Peak memory 220040 kb
Host smart-738d5ef5-2a07-4411-9d51-cd04249665ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761113717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1761113717
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1847443111
Short name T959
Test name
Test status
Simulation time 600064657 ps
CPU time 31.22 seconds
Started Feb 07 02:19:19 PM PST 24
Finished Feb 07 02:19:52 PM PST 24
Peak memory 316372 kb
Host smart-3067398a-f3d6-490b-b160-0f5f170dd817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847443111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1847443111
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1093117878
Short name T1368
Test name
Test status
Simulation time 15728652578 ps
CPU time 144.38 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:21:49 PM PST 24
Peak memory 1108668 kb
Host smart-9bc228a4-54b7-45bb-91a6-965d21dd4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093117878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1093117878
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3364284558
Short name T738
Test name
Test status
Simulation time 3271173923 ps
CPU time 155.07 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:21:56 PM PST 24
Peak memory 995816 kb
Host smart-47f25bb2-899e-4ef8-98af-3a6398f5a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364284558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3364284558
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3432475009
Short name T736
Test name
Test status
Simulation time 69393402 ps
CPU time 0.81 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:22 PM PST 24
Peak memory 203408 kb
Host smart-3ecd5442-928c-484f-8ce3-8afc250cc516
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432475009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3432475009
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3558296843
Short name T221
Test name
Test status
Simulation time 201711796 ps
CPU time 10.5 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:32 PM PST 24
Peak memory 203632 kb
Host smart-cf48b88d-283a-425b-ae5d-1c03d192c5c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558296843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3558296843
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.578055198
Short name T1235
Test name
Test status
Simulation time 4532265813 ps
CPU time 207.78 seconds
Started Feb 07 02:19:13 PM PST 24
Finished Feb 07 02:22:43 PM PST 24
Peak memory 1324400 kb
Host smart-4ad02777-be22-491e-96f3-f3e275434abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578055198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.578055198
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3134724469
Short name T784
Test name
Test status
Simulation time 4724466409 ps
CPU time 111.29 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:21:14 PM PST 24
Peak memory 233544 kb
Host smart-09580961-c570-46c6-b618-2eb03c8b85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134724469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3134724469
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.1890828540
Short name T862
Test name
Test status
Simulation time 44893455 ps
CPU time 0.64 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:19:25 PM PST 24
Peak memory 203292 kb
Host smart-c8c1542f-b2d6-4c69-832c-7fca3f723803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890828540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1890828540
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.638568980
Short name T587
Test name
Test status
Simulation time 3002803950 ps
CPU time 73.96 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:20:36 PM PST 24
Peak memory 211988 kb
Host smart-6f67911d-bfe5-4541-98c5-9570df1596f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638568980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.638568980
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.1202865777
Short name T447
Test name
Test status
Simulation time 1938319075 ps
CPU time 63.66 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:20:22 PM PST 24
Peak memory 300636 kb
Host smart-d9055ca0-8f31-446b-81ad-0fdcf2983753
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202865777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.
1202865777
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1589905920
Short name T229
Test name
Test status
Simulation time 1789992944 ps
CPU time 89.53 seconds
Started Feb 07 02:19:16 PM PST 24
Finished Feb 07 02:20:48 PM PST 24
Peak memory 220036 kb
Host smart-c9899bc3-c079-4593-a919-09b22a114acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589905920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1589905920
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.311107468
Short name T184
Test name
Test status
Simulation time 15627041834 ps
CPU time 3150.14 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 03:11:56 PM PST 24
Peak memory 3920292 kb
Host smart-d25f2241-dfc5-44ee-9f2f-20f2f0601945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311107468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.311107468
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2031470118
Short name T785
Test name
Test status
Simulation time 3612520877 ps
CPU time 15.13 seconds
Started Feb 07 02:19:19 PM PST 24
Finished Feb 07 02:19:36 PM PST 24
Peak memory 219788 kb
Host smart-9ab89bb6-3e3a-46ce-b941-c58580b0750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031470118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2031470118
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.778492661
Short name T611
Test name
Test status
Simulation time 1678877242 ps
CPU time 3.59 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 203676 kb
Host smart-49563c4d-ea3c-44d0-9152-0e599669ad35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778492661 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.778492661
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2197397583
Short name T61
Test name
Test status
Simulation time 10127692554 ps
CPU time 27.76 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:53 PM PST 24
Peak memory 369776 kb
Host smart-992e8a1f-dcdc-4b14-bece-fecb4c06772e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197397583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2197397583
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.154835070
Short name T776
Test name
Test status
Simulation time 10080688062 ps
CPU time 61.66 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:20:25 PM PST 24
Peak memory 531560 kb
Host smart-14f9aee5-386d-4fbf-9143-3acc3592d645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154835070 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.154835070
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.555829602
Short name T1280
Test name
Test status
Simulation time 1112229804 ps
CPU time 2.67 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:25 PM PST 24
Peak memory 203648 kb
Host smart-1d3e8029-ac46-476f-addc-eb726dd662d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555829602 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_hrst.555829602
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.257744192
Short name T1383
Test name
Test status
Simulation time 1266946619 ps
CPU time 4.68 seconds
Started Feb 07 02:19:18 PM PST 24
Finished Feb 07 02:19:24 PM PST 24
Peak memory 203660 kb
Host smart-fd993687-7c0b-40e4-b9aa-acd9c724252e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257744192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.257744192
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.537224612
Short name T171
Test name
Test status
Simulation time 22793399205 ps
CPU time 972.7 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:35:35 PM PST 24
Peak memory 5504640 kb
Host smart-23701462-035e-46a8-b50b-386890d12655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537224612 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.537224612
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.3005756980
Short name T604
Test name
Test status
Simulation time 1777123933 ps
CPU time 2.71 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:25 PM PST 24
Peak memory 203608 kb
Host smart-41904c8e-eb4b-479b-a618-55982d244f4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005756980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.3005756980
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3482990900
Short name T1394
Test name
Test status
Simulation time 4350442226 ps
CPU time 30.06 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:19:57 PM PST 24
Peak memory 203688 kb
Host smart-33664057-9c13-4c2f-ad62-7d4bcb331dbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482990900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3482990900
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.2083213307
Short name T146
Test name
Test status
Simulation time 18286190251 ps
CPU time 120.29 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:21:22 PM PST 24
Peak memory 425440 kb
Host smart-a804f971-9d36-41f1-b67a-050c37ce0b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083213307 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.2083213307
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.4168190460
Short name T1402
Test name
Test status
Simulation time 5709720253 ps
CPU time 20.17 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:19:44 PM PST 24
Peak memory 208856 kb
Host smart-f01667d5-858d-46c7-9d12-221bbce3d82f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168190460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.4168190460
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2019437425
Short name T717
Test name
Test status
Simulation time 43366002729 ps
CPU time 2192.71 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:55:56 PM PST 24
Peak memory 9405028 kb
Host smart-46d2c3da-fd1e-4b31-b534-ce3f7a2396fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019437425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2019437425
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.4113264095
Short name T1004
Test name
Test status
Simulation time 6885894291 ps
CPU time 35.91 seconds
Started Feb 07 02:19:18 PM PST 24
Finished Feb 07 02:19:55 PM PST 24
Peak memory 551236 kb
Host smart-2d93d709-90e4-48a7-87f5-8438f61aeb49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113264095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.4113264095
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1126313334
Short name T671
Test name
Test status
Simulation time 3421858082 ps
CPU time 7 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 203708 kb
Host smart-cb45bf6d-a61a-42a2-95f7-f9d7f12cf8d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126313334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1126313334
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_ovf.3528930039
Short name T454
Test name
Test status
Simulation time 3924223952 ps
CPU time 184.97 seconds
Started Feb 07 02:19:19 PM PST 24
Finished Feb 07 02:22:26 PM PST 24
Peak memory 459520 kb
Host smart-cb99960c-92d9-4a82-b923-3aa599d12174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528930039 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_tx_ovf.3528930039
Directory /workspace/6.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.3574107723
Short name T169
Test name
Test status
Simulation time 4215500992 ps
CPU time 6.93 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:19:31 PM PST 24
Peak memory 203796 kb
Host smart-a5ec54b0-d139-47a9-ac71-5faa458a0d66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574107723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.3574107723
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.594940919
Short name T1167
Test name
Test status
Simulation time 16041364 ps
CPU time 0.58 seconds
Started Feb 07 02:19:26 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 202404 kb
Host smart-c0a02248-9308-46b3-9b0e-8dd05f5ec5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594940919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.594940919
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1724272051
Short name T961
Test name
Test status
Simulation time 50755818 ps
CPU time 1.4 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:24 PM PST 24
Peak memory 211808 kb
Host smart-4d51491a-c26d-4bd7-a704-1836019a5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724272051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1724272051
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4191454168
Short name T1016
Test name
Test status
Simulation time 571302453 ps
CPU time 10.67 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:36 PM PST 24
Peak memory 322524 kb
Host smart-673fbc34-1086-42a0-aaa7-5b653717ef0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191454168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4191454168
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1064961442
Short name T688
Test name
Test status
Simulation time 7651064986 ps
CPU time 130.48 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:21:33 PM PST 24
Peak memory 635936 kb
Host smart-684a9efb-bc1c-4ef3-9a5a-e416561424d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064961442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1064961442
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1439012167
Short name T1496
Test name
Test status
Simulation time 8263036057 ps
CPU time 220.88 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:23:04 PM PST 24
Peak memory 1172576 kb
Host smart-f7199a30-2476-4c46-b4e0-5c079ec6f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439012167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1439012167
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3810648072
Short name T571
Test name
Test status
Simulation time 494394779 ps
CPU time 1 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:27 PM PST 24
Peak memory 203284 kb
Host smart-4150e81f-818a-4f7c-a92b-b3bd4135d843
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810648072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3810648072
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2737014876
Short name T1355
Test name
Test status
Simulation time 718620576 ps
CPU time 11.49 seconds
Started Feb 07 02:19:29 PM PST 24
Finished Feb 07 02:19:41 PM PST 24
Peak memory 203664 kb
Host smart-2b48d1b5-7dec-4eee-975b-125d57771516
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737014876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2737014876
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1643100194
Short name T1243
Test name
Test status
Simulation time 4112624315 ps
CPU time 357.37 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:25:20 PM PST 24
Peak memory 1142824 kb
Host smart-3ac511c2-3b98-4519-a380-0d4eb0abeed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643100194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1643100194
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3239403950
Short name T499
Test name
Test status
Simulation time 4057459981 ps
CPU time 62.82 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:20:29 PM PST 24
Peak memory 322996 kb
Host smart-43e3b3b2-e5a3-4460-82ff-d33579de7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239403950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3239403950
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.3385524442
Short name T692
Test name
Test status
Simulation time 94197431 ps
CPU time 0.61 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:22 PM PST 24
Peak memory 202600 kb
Host smart-de8e7fc6-e0bd-4576-9412-6d88dd96aa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385524442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3385524442
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3403631944
Short name T1010
Test name
Test status
Simulation time 9579714273 ps
CPU time 383.15 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:25:48 PM PST 24
Peak memory 674428 kb
Host smart-f448c2bf-5a4a-45cf-88a9-8e92745a9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403631944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3403631944
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.2331400809
Short name T1443
Test name
Test status
Simulation time 3752677011 ps
CPU time 60.09 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:20:25 PM PST 24
Peak memory 276488 kb
Host smart-5c6e444a-ed5c-46ae-a14e-1fb54231744b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331400809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.
2331400809
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3077533139
Short name T1036
Test name
Test status
Simulation time 2917371013 ps
CPU time 30.62 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:53 PM PST 24
Peak memory 228260 kb
Host smart-076b97ad-96b8-4346-85dd-d3f1ed2d1199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077533139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3077533139
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.3487376633
Short name T1425
Test name
Test status
Simulation time 51450620092 ps
CPU time 805.26 seconds
Started Feb 07 02:19:18 PM PST 24
Finished Feb 07 02:32:45 PM PST 24
Peak memory 2394532 kb
Host smart-cd2d7e4b-e562-41d6-b198-f9f8f34f3132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487376633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3487376633
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1927823030
Short name T174
Test name
Test status
Simulation time 708093188 ps
CPU time 10.24 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:19:33 PM PST 24
Peak memory 219948 kb
Host smart-95e642dc-b356-469a-bb79-6da178502519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927823030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1927823030
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2013732198
Short name T871
Test name
Test status
Simulation time 1615787251 ps
CPU time 3.36 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:29 PM PST 24
Peak memory 203640 kb
Host smart-3ae8ea90-ff5d-4051-8d9b-a755c0137d03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013732198 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2013732198
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3062783572
Short name T1094
Test name
Test status
Simulation time 10045550919 ps
CPU time 49.68 seconds
Started Feb 07 02:19:26 PM PST 24
Finished Feb 07 02:20:18 PM PST 24
Peak memory 446024 kb
Host smart-67662598-ae89-4b19-b4e4-86c7d1972c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062783572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3062783572
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2014047193
Short name T1229
Test name
Test status
Simulation time 10119967019 ps
CPU time 69.8 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:20:36 PM PST 24
Peak memory 594376 kb
Host smart-6b586049-de20-4cb7-9350-8da7cf224396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014047193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2014047193
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3850766243
Short name T155
Test name
Test status
Simulation time 449093165 ps
CPU time 2.37 seconds
Started Feb 07 02:19:26 PM PST 24
Finished Feb 07 02:19:30 PM PST 24
Peak memory 203644 kb
Host smart-22bdf4c7-8d13-4170-a78c-dc1d540fd3c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850766243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3850766243
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3878113271
Short name T420
Test name
Test status
Simulation time 1150873580 ps
CPU time 4.12 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:19:27 PM PST 24
Peak memory 203632 kb
Host smart-3c22592d-1996-4c55-a8a9-c5e8b843dcae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878113271 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3878113271
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1607109938
Short name T1457
Test name
Test status
Simulation time 20912037195 ps
CPU time 112.87 seconds
Started Feb 07 02:19:21 PM PST 24
Finished Feb 07 02:21:15 PM PST 24
Peak memory 1343876 kb
Host smart-f927163b-d5d8-4e51-a546-97dfcf856b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607109938 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1607109938
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.706968633
Short name T735
Test name
Test status
Simulation time 572527390 ps
CPU time 3.21 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 204088 kb
Host smart-207d05ff-ba32-44d3-b590-70ac96dfb385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706968633 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_perf.706968633
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1799500780
Short name T206
Test name
Test status
Simulation time 3732584620 ps
CPU time 17.29 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:43 PM PST 24
Peak memory 203648 kb
Host smart-b1c79440-5d7d-4425-81f1-0ccdda20a766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799500780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1799500780
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.1536518631
Short name T872
Test name
Test status
Simulation time 52770387125 ps
CPU time 889.5 seconds
Started Feb 07 02:19:26 PM PST 24
Finished Feb 07 02:34:17 PM PST 24
Peak memory 1119176 kb
Host smart-98daf9d1-e68f-4051-b1e2-daac8f231586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536518631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.1536518631
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.1288851066
Short name T695
Test name
Test status
Simulation time 2390133647 ps
CPU time 5.51 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:19:31 PM PST 24
Peak memory 203692 kb
Host smart-64c7aa0d-8038-4e20-8cdf-1c431a47047e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288851066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.1288851066
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.607156109
Short name T755
Test name
Test status
Simulation time 46617345797 ps
CPU time 299.6 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:24:24 PM PST 24
Peak memory 2704408 kb
Host smart-0abe977e-7f8f-46bf-8502-bce878364c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607156109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.607156109
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.299253707
Short name T958
Test name
Test status
Simulation time 17152160686 ps
CPU time 101.57 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:21:08 PM PST 24
Peak memory 1004720 kb
Host smart-845c2d71-48aa-4d22-8be9-41703cff6875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299253707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stretch.299253707
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1289002362
Short name T580
Test name
Test status
Simulation time 1708977896 ps
CPU time 6.87 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:19:33 PM PST 24
Peak memory 203648 kb
Host smart-2ebe5fe1-2218-48db-9c1b-3fb5c53293be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289002362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1289002362
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_ovf.1654554395
Short name T793
Test name
Test status
Simulation time 3167139894 ps
CPU time 123.35 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:21:28 PM PST 24
Peak memory 398520 kb
Host smart-82e15e4b-f0b3-4e7e-b9ff-c2bff340cf46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654554395 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_tx_ovf.1654554395
Directory /workspace/7.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.218843599
Short name T903
Test name
Test status
Simulation time 1623728181 ps
CPU time 6.88 seconds
Started Feb 07 02:19:20 PM PST 24
Finished Feb 07 02:19:28 PM PST 24
Peak memory 203636 kb
Host smart-3ef75db1-f94d-465a-a90b-b145b0bf60d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218843599 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_unexp_stop.218843599
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2660803803
Short name T584
Test name
Test status
Simulation time 43698218 ps
CPU time 0.6 seconds
Started Feb 07 02:19:33 PM PST 24
Finished Feb 07 02:19:34 PM PST 24
Peak memory 203308 kb
Host smart-0fd307eb-bf05-46ec-a106-4ee9f0c65e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660803803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2660803803
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1059725675
Short name T670
Test name
Test status
Simulation time 57992864 ps
CPU time 1.46 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:19:36 PM PST 24
Peak memory 211912 kb
Host smart-8c785c0b-5a0c-4507-9835-bff6bf19e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059725675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1059725675
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3402425864
Short name T1159
Test name
Test status
Simulation time 9501801643 ps
CPU time 26.11 seconds
Started Feb 07 02:19:30 PM PST 24
Finished Feb 07 02:19:57 PM PST 24
Peak memory 307464 kb
Host smart-2b2d6569-4356-4fb5-88de-24c8d33424d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402425864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3402425864
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.4101230035
Short name T1220
Test name
Test status
Simulation time 3458845680 ps
CPU time 281.15 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:24:23 PM PST 24
Peak memory 1029904 kb
Host smart-75c471fb-590b-486a-bee0-d8e70025f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101230035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.4101230035
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1758138562
Short name T1372
Test name
Test status
Simulation time 4049011275 ps
CPU time 361.51 seconds
Started Feb 07 02:19:24 PM PST 24
Finished Feb 07 02:25:27 PM PST 24
Peak memory 1091784 kb
Host smart-0f58b543-a1cc-4d88-b553-a35a37bd83f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758138562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1758138562
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1736240560
Short name T539
Test name
Test status
Simulation time 192072493 ps
CPU time 0.86 seconds
Started Feb 07 02:19:22 PM PST 24
Finished Feb 07 02:19:25 PM PST 24
Peak memory 203408 kb
Host smart-a2038e3e-647d-4fb2-8c60-2cbea38a15b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736240560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1736240560
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2148709960
Short name T304
Test name
Test status
Simulation time 154894647 ps
CPU time 8.03 seconds
Started Feb 07 02:19:29 PM PST 24
Finished Feb 07 02:19:39 PM PST 24
Peak memory 203680 kb
Host smart-850498f8-b408-47c5-b616-20b3bdb2e46c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148709960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2148709960
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2732350319
Short name T907
Test name
Test status
Simulation time 131654490427 ps
CPU time 829.2 seconds
Started Feb 07 02:19:30 PM PST 24
Finished Feb 07 02:33:21 PM PST 24
Peak memory 1876836 kb
Host smart-2447c56f-0c69-410b-a6f6-072bf15b5eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732350319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2732350319
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.514720177
Short name T1216
Test name
Test status
Simulation time 9907297722 ps
CPU time 128.2 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:21:50 PM PST 24
Peak memory 252240 kb
Host smart-94186897-21ba-4b73-904f-8045cc2aa136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514720177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.514720177
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.1192602707
Short name T951
Test name
Test status
Simulation time 17319612 ps
CPU time 0.62 seconds
Started Feb 07 02:19:30 PM PST 24
Finished Feb 07 02:19:32 PM PST 24
Peak memory 202620 kb
Host smart-b21ffa3a-5aba-46b5-934c-a0d32ae25661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192602707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1192602707
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3452593365
Short name T153
Test name
Test status
Simulation time 2565023269 ps
CPU time 3.05 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:19:38 PM PST 24
Peak memory 219704 kb
Host smart-fcd74967-6897-41b0-b2e7-a6d97323fb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452593365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3452593365
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.1765735866
Short name T1201
Test name
Test status
Simulation time 9917658754 ps
CPU time 112.18 seconds
Started Feb 07 02:19:25 PM PST 24
Finished Feb 07 02:21:18 PM PST 24
Peak memory 346396 kb
Host smart-e29c6197-4ecb-4529-9aa9-f7a2eaf3576c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765735866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.
1765735866
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1284959009
Short name T678
Test name
Test status
Simulation time 2326644690 ps
CPU time 114.77 seconds
Started Feb 07 02:19:23 PM PST 24
Finished Feb 07 02:21:19 PM PST 24
Peak memory 245036 kb
Host smart-fc93bdf3-854b-44f8-9e4b-9bb43f175cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284959009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1284959009
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.4278997004
Short name T1351
Test name
Test status
Simulation time 1440153470 ps
CPU time 12.85 seconds
Started Feb 07 02:19:40 PM PST 24
Finished Feb 07 02:19:54 PM PST 24
Peak memory 211852 kb
Host smart-dbd3e616-5f95-4119-9e14-3e5256aaae71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278997004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.4278997004
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1597876444
Short name T805
Test name
Test status
Simulation time 3617122815 ps
CPU time 3.65 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:19:39 PM PST 24
Peak memory 203720 kb
Host smart-cd677ae8-a580-48de-89b5-904cd1a83d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597876444 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1597876444
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.480278142
Short name T1
Test name
Test status
Simulation time 10144068058 ps
CPU time 17.84 seconds
Started Feb 07 02:19:35 PM PST 24
Finished Feb 07 02:19:54 PM PST 24
Peak memory 331820 kb
Host smart-ff5e7cd0-f381-4664-a567-58190d06bb89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480278142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.480278142
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.4051372374
Short name T1386
Test name
Test status
Simulation time 10426747454 ps
CPU time 6.27 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:19:48 PM PST 24
Peak memory 247396 kb
Host smart-670a93b5-775d-443d-bae0-888bc5a98f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051372374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.4051372374
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2441182939
Short name T853
Test name
Test status
Simulation time 2398062652 ps
CPU time 2.32 seconds
Started Feb 07 02:19:37 PM PST 24
Finished Feb 07 02:19:41 PM PST 24
Peak memory 203676 kb
Host smart-cbcfdfa4-6c16-47fa-828c-da5b1e4d75f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441182939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2441182939
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2679557248
Short name T280
Test name
Test status
Simulation time 1020908896 ps
CPU time 4.65 seconds
Started Feb 07 02:19:42 PM PST 24
Finished Feb 07 02:19:48 PM PST 24
Peak memory 203628 kb
Host smart-a4820e5a-5a27-401f-a4cb-c680bb6dfe41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679557248 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2679557248
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3636359067
Short name T552
Test name
Test status
Simulation time 19934696449 ps
CPU time 88.31 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:21:03 PM PST 24
Peak memory 1082976 kb
Host smart-15238e68-4835-4a13-a16e-8086bba99cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636359067 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3636359067
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.3509175753
Short name T1032
Test name
Test status
Simulation time 1544559293 ps
CPU time 4.46 seconds
Started Feb 07 02:19:35 PM PST 24
Finished Feb 07 02:19:40 PM PST 24
Peak memory 203600 kb
Host smart-9bd73f10-b40c-49e1-8c33-4b084ee9fef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509175753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.3509175753
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3615418941
Short name T804
Test name
Test status
Simulation time 973646498 ps
CPU time 9.96 seconds
Started Feb 07 02:19:37 PM PST 24
Finished Feb 07 02:19:48 PM PST 24
Peak memory 203660 kb
Host smart-7dcf42c0-8447-4833-9180-80134a1e588b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615418941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3615418941
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.2516818844
Short name T459
Test name
Test status
Simulation time 64938786465 ps
CPU time 1759.05 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:49:01 PM PST 24
Peak memory 3175120 kb
Host smart-dbb999c6-0375-4303-95b2-50adc63022f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516818844 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.2516818844
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1466909971
Short name T1390
Test name
Test status
Simulation time 5444357590 ps
CPU time 24.21 seconds
Started Feb 07 02:19:31 PM PST 24
Finished Feb 07 02:19:56 PM PST 24
Peak memory 224932 kb
Host smart-0e29d149-94f3-4eed-9995-4e574f48357c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466909971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1466909971
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3382373055
Short name T934
Test name
Test status
Simulation time 45085560269 ps
CPU time 2428.04 seconds
Started Feb 07 02:19:37 PM PST 24
Finished Feb 07 03:00:07 PM PST 24
Peak memory 10341868 kb
Host smart-a3c20d0b-2bf6-4fa4-a771-ac7bff0d5817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382373055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3382373055
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2894596041
Short name T1504
Test name
Test status
Simulation time 30112622999 ps
CPU time 1677.81 seconds
Started Feb 07 02:19:40 PM PST 24
Finished Feb 07 02:47:38 PM PST 24
Peak memory 3112564 kb
Host smart-4fa5a3c0-b8e3-42f5-823c-7eb8b821645d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894596041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2894596041
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.941975366
Short name T949
Test name
Test status
Simulation time 1812614951 ps
CPU time 7.21 seconds
Started Feb 07 02:19:42 PM PST 24
Finished Feb 07 02:19:50 PM PST 24
Peak memory 203620 kb
Host smart-e1df0214-f05c-4c4c-8c90-da0ac13d4738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941975366 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.941975366
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_ovf.2725992684
Short name T1392
Test name
Test status
Simulation time 2406893772 ps
CPU time 38.71 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:20:13 PM PST 24
Peak memory 220052 kb
Host smart-95213192-a4bb-4e53-9397-d253ba33d83d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725992684 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_tx_ovf.2725992684
Directory /workspace/8.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.3399294477
Short name T307
Test name
Test status
Simulation time 1574566382 ps
CPU time 8.44 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:19:44 PM PST 24
Peak memory 203656 kb
Host smart-2cecfcca-3ddb-4d79-bb2f-bd45414e8ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399294477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.3399294477
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1791201391
Short name T1328
Test name
Test status
Simulation time 30753486 ps
CPU time 0.59 seconds
Started Feb 07 02:19:52 PM PST 24
Finished Feb 07 02:19:54 PM PST 24
Peak memory 202216 kb
Host smart-7abb6e8e-9ce4-449d-8e92-538e9b5002c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791201391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1791201391
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3387625915
Short name T45
Test name
Test status
Simulation time 66000367 ps
CPU time 1.76 seconds
Started Feb 07 02:19:45 PM PST 24
Finished Feb 07 02:19:47 PM PST 24
Peak memory 211840 kb
Host smart-7dfc6c73-ef26-4c25-97c3-895931ce436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387625915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3387625915
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1865383027
Short name T1341
Test name
Test status
Simulation time 681476412 ps
CPU time 7.51 seconds
Started Feb 07 02:19:34 PM PST 24
Finished Feb 07 02:19:42 PM PST 24
Peak memory 275584 kb
Host smart-c6dd835f-9569-4972-96c4-f10ecda5e96e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865383027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1865383027
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2133616853
Short name T920
Test name
Test status
Simulation time 7052358992 ps
CPU time 59.98 seconds
Started Feb 07 02:19:44 PM PST 24
Finished Feb 07 02:20:44 PM PST 24
Peak memory 585760 kb
Host smart-418378a6-0176-4cfa-aa1d-2be1881b1c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133616853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2133616853
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3855626880
Short name T11
Test name
Test status
Simulation time 6632169394 ps
CPU time 505.9 seconds
Started Feb 07 02:19:42 PM PST 24
Finished Feb 07 02:28:09 PM PST 24
Peak memory 1815392 kb
Host smart-7f94931b-15e8-47a1-8ff8-54f705098352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855626880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3855626880
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3898251409
Short name T204
Test name
Test status
Simulation time 270474661 ps
CPU time 0.97 seconds
Started Feb 07 02:19:33 PM PST 24
Finished Feb 07 02:19:35 PM PST 24
Peak memory 203652 kb
Host smart-05b028a1-104c-4859-9fca-bc5f339fdead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898251409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3898251409
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1750921623
Short name T1509
Test name
Test status
Simulation time 471218161 ps
CPU time 4.83 seconds
Started Feb 07 02:19:48 PM PST 24
Finished Feb 07 02:19:53 PM PST 24
Peak memory 203588 kb
Host smart-0b467780-cdf8-4ace-a875-c12fb1387ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750921623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1750921623
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1983626080
Short name T654
Test name
Test status
Simulation time 10412389232 ps
CPU time 252.23 seconds
Started Feb 07 02:19:39 PM PST 24
Finished Feb 07 02:23:53 PM PST 24
Peak memory 1534316 kb
Host smart-51971f70-1ed4-4707-ace2-b12b739dc1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983626080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1983626080
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.159649954
Short name T31
Test name
Test status
Simulation time 7998984972 ps
CPU time 112.61 seconds
Started Feb 07 02:19:47 PM PST 24
Finished Feb 07 02:21:41 PM PST 24
Peak memory 252784 kb
Host smart-41d69921-b1b2-448b-abcd-17e51700e4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159649954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.159649954
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1160812685
Short name T1308
Test name
Test status
Simulation time 74108799 ps
CPU time 0.61 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:19:42 PM PST 24
Peak memory 202656 kb
Host smart-724320b5-612b-46d1-937c-c5700bb322a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160812685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1160812685
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2183421977
Short name T1286
Test name
Test status
Simulation time 13479498468 ps
CPU time 781.73 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:32:44 PM PST 24
Peak memory 362424 kb
Host smart-e53b0dd4-3329-41a6-8b17-c7300f8fb5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183421977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2183421977
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.3847882424
Short name T326
Test name
Test status
Simulation time 31874818348 ps
CPU time 176.69 seconds
Started Feb 07 02:19:41 PM PST 24
Finished Feb 07 02:22:38 PM PST 24
Peak memory 361496 kb
Host smart-197770b8-5afc-4512-b70f-7e159b886fb9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847882424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.
3847882424
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3816906996
Short name T1407
Test name
Test status
Simulation time 1789567680 ps
CPU time 42.35 seconds
Started Feb 07 02:19:38 PM PST 24
Finished Feb 07 02:20:21 PM PST 24
Peak memory 276744 kb
Host smart-1636d21a-5419-4bfd-93b6-c82cf0ad392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816906996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3816906996
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.135020061
Short name T183
Test name
Test status
Simulation time 1409813784 ps
CPU time 12.3 seconds
Started Feb 07 02:19:46 PM PST 24
Finished Feb 07 02:19:59 PM PST 24
Peak memory 219960 kb
Host smart-4b834408-5cbd-4d3f-884b-99c2b29bd6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135020061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.135020061
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1858720211
Short name T1089
Test name
Test status
Simulation time 10229723005 ps
CPU time 18.93 seconds
Started Feb 07 02:19:50 PM PST 24
Finished Feb 07 02:20:10 PM PST 24
Peak memory 328944 kb
Host smart-39d7365b-49e2-491c-a572-be6f5e2b92a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858720211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1858720211
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.690708335
Short name T1176
Test name
Test status
Simulation time 10071728961 ps
CPU time 62.4 seconds
Started Feb 07 02:20:00 PM PST 24
Finished Feb 07 02:21:03 PM PST 24
Peak memory 550340 kb
Host smart-cefff76e-1e1b-4b74-bd16-f9435caa3ef2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690708335 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.690708335
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3841116356
Short name T829
Test name
Test status
Simulation time 2165947344 ps
CPU time 2.45 seconds
Started Feb 07 02:19:51 PM PST 24
Finished Feb 07 02:19:55 PM PST 24
Peak memory 203768 kb
Host smart-a7d99f27-3583-46be-bd32-8795039111d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841116356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3841116356
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3251998927
Short name T517
Test name
Test status
Simulation time 4258531240 ps
CPU time 8.33 seconds
Started Feb 07 02:19:46 PM PST 24
Finished Feb 07 02:19:55 PM PST 24
Peak memory 212004 kb
Host smart-cdd010bb-b13c-44e8-96be-87e0a295faa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251998927 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3251998927
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1258829544
Short name T287
Test name
Test status
Simulation time 17644782095 ps
CPU time 615.04 seconds
Started Feb 07 02:19:53 PM PST 24
Finished Feb 07 02:30:09 PM PST 24
Peak memory 4187132 kb
Host smart-e216751b-c325-4b6c-a6f2-07aa40d42b61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258829544 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1258829544
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.2754599078
Short name T414
Test name
Test status
Simulation time 998916994 ps
CPU time 3.25 seconds
Started Feb 07 02:19:46 PM PST 24
Finished Feb 07 02:19:50 PM PST 24
Peak memory 203600 kb
Host smart-83138357-cf2e-4bb1-9c08-61b9af74aba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754599078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.2754599078
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3007618964
Short name T1135
Test name
Test status
Simulation time 465207284 ps
CPU time 13.12 seconds
Started Feb 07 02:19:44 PM PST 24
Finished Feb 07 02:19:57 PM PST 24
Peak memory 203628 kb
Host smart-fd63b5ee-c9cc-48d5-bdd7-e2bab740d086
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007618964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3007618964
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2743784538
Short name T1257
Test name
Test status
Simulation time 15662226977 ps
CPU time 17.13 seconds
Started Feb 07 02:19:45 PM PST 24
Finished Feb 07 02:20:03 PM PST 24
Peak memory 214376 kb
Host smart-55c30607-78d9-4a99-9583-9ce5aa0b767d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743784538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2743784538
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.102532564
Short name T1095
Test name
Test status
Simulation time 22758262841 ps
CPU time 537.26 seconds
Started Feb 07 02:19:43 PM PST 24
Finished Feb 07 02:28:41 PM PST 24
Peak memory 4579272 kb
Host smart-f49048de-0671-4555-b17c-1b206c5a16e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102532564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.102532564
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.337778952
Short name T801
Test name
Test status
Simulation time 39189425309 ps
CPU time 310.48 seconds
Started Feb 07 02:19:45 PM PST 24
Finished Feb 07 02:24:56 PM PST 24
Peak memory 1987452 kb
Host smart-9e16da12-00c2-4881-9aeb-9534a70726b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337778952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.337778952
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.673276370
Short name T904
Test name
Test status
Simulation time 1381879950 ps
CPU time 5.6 seconds
Started Feb 07 02:19:49 PM PST 24
Finished Feb 07 02:19:56 PM PST 24
Peak memory 203524 kb
Host smart-bf2947af-6a60-4d5d-9312-e373457fa4f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673276370 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.673276370
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_ovf.2120838292
Short name T515
Test name
Test status
Simulation time 6142886042 ps
CPU time 42.94 seconds
Started Feb 07 02:19:52 PM PST 24
Finished Feb 07 02:20:35 PM PST 24
Peak memory 220564 kb
Host smart-e57ff03b-1e96-4b5b-9f22-312661193205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120838292 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_tx_ovf.2120838292
Directory /workspace/9.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1653553780
Short name T211
Test name
Test status
Simulation time 1836837358 ps
CPU time 5.59 seconds
Started Feb 07 02:19:54 PM PST 24
Finished Feb 07 02:20:00 PM PST 24
Peak memory 203684 kb
Host smart-fbefef53-7919-4077-8d1a-bd6e45c4714f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653553780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1653553780
Directory /workspace/9.i2c_target_unexp_stop/latest
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