Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

224414

1

T2

640

T10

704

T57

1152

ack

19341

1

T2

20

T9

40

T10

22

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	936	1			T2	3		T10	5		T57	3
high	49832	1			T2	147		T9	5		T10	142
med	90718	1			T2	258		T9	3		T10	281
sml	101324	1			T2	250		T9	32		T10	297
all_zero	945	1			T2	2		T10	1		T57	8

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121526

1

T2

346

T9

20

T10

344

auto[1]

122229

1

T2

314

T9

20

T10

382

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166847

1

T2

427

T9

27

T10

523

auto[1]

76908

1

T2

233

T9

13

T10

203

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232641

1

T2

651

T9

14

T10

716

auto[1]

11114

1

T2

9

T9

26

T10

10

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229804

1

T2

641

T9

26

T10

705

auto[1]

13951

1

T2

19

T9

14

T10

21

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231568

1

T2

642

T9

27

T10

706

auto[1]

12187

1

T2

18

T9

13

T10

20

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121526

1

T2

346

T9

20

T10

344

auto[1]

122229

1

T2

314

T9

20

T10

382

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166847

1

T2

427

T9

27

T10

523

auto[1]

76908

1

T2

233

T9

13

T10

203

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232641

1

T2

651

T9

14

T10

716

auto[1]

11114

1

T2

9

T9

26

T10

10

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229804

1

T2

641

T9

26

T10

705

auto[1]

13951

1

T2

19

T9

14

T10

21

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231568

1

T2

642

T9

27

T10

706

auto[1]

12187

1

T2

18

T9

13

T10

20

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T186

1

T187

1

T188

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T186

1

T189

1

T190

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T138

1

T191

1

T192

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

627

1

T2

2

T10

3

T57

4

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

297

1

T2

1

T11

3

T32

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

318

1

T2

1

T10

1

T68

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1068

1

T2

1

T10

3

T57

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

551

1

T2

1

T10

1

T57

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

603

1

T2

1

T10

2

T31

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1139

1

T2

1

T10

2

T57

7

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

507

1

T2

1

T10

1

T57

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

577

1

T10

1

T57

2

T11

3

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T57

1

T32

1

T13

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T193

1

T194

1

T195

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T196

1

T197

1

T198

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	71046	1			T2	211		T10	217		T57	370
write_address_byte	13951	1			T2	19		T9	14		T10	21
read_with_ack	3950	1			T9	13		T14	16		T11	14
read_with_nack	7164	1			T2	9		T9	13		T10	10
stop_byte	12187	1			T2	18		T9	13		T10	20
write_address_byte_nak	9026	1			T2	16		T10	18		T57	32
data_byte_nack	224414	1			T2	640		T10	704		T57	1152
stop_byte_nack	8736	1			T2	15		T10	17		T57	31
nakok_byte_nack	112609	1			T2	306		T10	367		T57	593
nakok_addr_byte_nack	4550	1			T2	7		T10	10		T57	14