Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
90.43 90.43 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 90.43 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
90.43 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 3 44 93.62
Crosses 68 8 60 88.24


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 0 1 100.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 0 1 100.00 100 1 1 0
bus_state_cp 17 1 16 94.12 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 3 31 91.18 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 27256 1 T7 16 T15 23 T16 32


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 4 1 T47 2 T48 2


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_transmission_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_address_transmission 10 1 T28 1 T51 1 T52 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_read_data 965 1 T7 12 T36 12 T37 5


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 24649 1 T1 39 T3 37 T7 26


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Read_data_ack_before_stop_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Read_data_ack_before_stop 430 1 T7 3 T36 8 T37 3


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 14 1 T47 8 T48 6


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 4 1 T47 2 T48 2


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] 5 1 T159 1 T177 4


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 20216 1 T2 9 T7 5 T15 2


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_ack 430 1 T7 3 T36 8 T37 3


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack 4 1 T178 1 T179 1 T180 2


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 13571 1 T1 2 T2 10 T3 2


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_addr 9 1 T54 1 T181 1 T182 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 8326 1 T1 2 T3 2 T7 11


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_write_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Stop_without_ACK_after_write 8 1 T47 4 T48 4


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 1 16 94.12


User Defined Bins for bus_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_addr_nack 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 242941 1 T1 1 T2 1 T3 1
stop 34856 1 T1 2 T2 19 T3 2
write_data_nack 12887 1 T96 6242 T178 60 T179 6239
write_data_ack 1726376 1 T1 1227 T2 2228 T3 1478
read_data_nack 182242 1 T2 40 T7 68 T15 77
read_data_ack 1904798 1 T2 1976 T7 670 T15 585
write_data 11585686 1 T1 8837 T2 13421 T3 10506
read_data 15786093 1 T2 15566 T7 5900 T15 4546
write_addr_nack 4 1 T47 2 T48 2 - -
write_addr_ack 138452 1 T1 149 T2 35 T3 141
read_addr_ack 173547 1 T2 34 T7 123 T15 90
write 161547 1 T1 168 T2 40 T3 160
read 149431 1 T2 30 T7 111 T15 75
addr 1855901 1 T1 846 T2 360 T3 716
rstart 138775 1 T1 117 T3 99 T7 135
start 91523 1 T1 9 T2 48 T3 9


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 18045405 1 T1 11356 T3 13112 T7 15974
host 16139654 1 T2 33798 T8 12 T9 22092


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 48997 1 T2 40 T9 55 T10 44
high 1783164 1 T2 5518 T62 4 T9 1094
mid 3129199 1 T2 6004 T7 856 T15 292
low 9392162 1 T2 5496 T7 4203 T15 3823
one 1123165 1 T2 278 T7 827 T15 572


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 36122 1 T2 50 T10 55 T57 90
high 1312728 1 T2 4876 T15 256 T16 433
mid 2010863 1 T1 308 T2 5374 T3 834
low 7492615 1 T1 7649 T2 4896 T3 9185
one 983298 1 T1 1078 T2 240 T3 976


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 3 31 91.18 3


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Element holes
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] * -- -- 2


Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[write_addr_nack] [host] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 240481 1 T1 1 T3 1 T7 1
idle host 2460 1 T2 1 T8 12 T9 1
stop device 17290 1 T1 2 T3 2 T7 16
stop host 17566 1 T2 19 T9 39 T10 21
write_data_nack device 4 1 T47 2 T48 2 - -
write_data_nack host 12883 1 T96 6242 T178 60 T179 6239
write_data_ack device 941523 1 T1 1227 T3 1478 T7 877
write_data_ack host 784853 1 T2 2228 T10 2488 T57 4021
read_data_nack device 117454 1 T7 68 T15 77 T16 124
read_data_nack host 64788 1 T2 40 T9 160 T10 44
read_data_ack device 897433 1 T7 670 T15 585 T16 896
read_data_ack host 1007365 1 T2 1976 T9 2033 T10 1948
write_data device 6877227 1 T1 8837 T3 10506 T7 6214
write_data host 4708459 1 T2 13421 T10 14813 T57 24215
read_data device 6774541 1 T7 5900 T15 4546 T16 5984
read_data host 9011552 1 T2 15566 T9 18799 T10 17232
write_addr_nack device 4 1 T47 2 T48 2 - -
write_addr_ack device 112957 1 T1 149 T3 141 T7 121
write_addr_ack host 25495 1 T2 35 T10 40 T57 64
read_addr_ack device 131414 1 T7 123 T15 90 T16 135
read_addr_ack host 42133 1 T2 34 T9 138 T10 39
write device 131590 1 T1 168 T3 160 T7 136
write host 29957 1 T2 40 T10 44 T57 72
read device 112920 1 T7 111 T15 75 T16 117
read host 36511 1 T2 30 T9 120 T10 33
addr device 1510441 1 T1 846 T3 716 T7 1559
addr host 345460 1 T2 360 T9 698 T10 372
rstart device 134941 1 T1 117 T3 99 T7 135
rstart host 3834 1 T31 9 T11 3 T32 82
start device 45185 1 T1 9 T3 9 T7 43
start host 46338 1 T2 48 T9 104 T10 57


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 2626 1 T19 162 T58 166 T59 432
device high 88132 1 T62 4 T17 118 T50 162
device mid 486010 1 T7 856 T15 292 T16 189
device low 5403274 1 T7 4203 T15 3823 T16 5184
device one 808343 1 T7 827 T15 572 T16 819
host sixtyfour 46371 1 T2 40 T9 55 T10 44
host high 1695032 1 T2 5518 T9 1094 T10 5983
host mid 2643189 1 T2 6004 T9 5313 T10 6584
host low 3988888 1 T2 5496 T9 12379 T10 6034
host one 314822 1 T2 278 T9 1015 T10 314


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 1426 1 T19 88 T58 142 T59 52
device high 70912 1 T15 256 T16 433 T164 84
device mid 473715 1 T1 308 T3 834 T7 206
device low 5551194 1 T1 7649 T3 9185 T7 5093
device one 821988 1 T1 1078 T3 976 T7 925
host sixtyfour 34696 1 T2 50 T10 55 T57 90
host high 1241816 1 T2 4876 T10 5358 T57 8780
host mid 1537148 1 T2 5374 T10 5960 T57 9698
host low 1941421 1 T2 4896 T10 5430 T57 8850
host one 161310 1 T2 240 T10 270 T57 442


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 7876 1 T1 2 T3 2 T7 8
Stop_after_write_data_ack host 5695 1 T2 10 T10 11 T57 18


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Element holes
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_ack device 430 1 T7 3 T36 8 T37 3


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack host 4 1 T178 1 T179 1 T180 2


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 8583 1 T7 5 T15 2 T16 7
Stop_after_read_data_Nack host 11633 1 T2 9 T9 39 T10 10


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Element holes
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 14 1 T47 8 T48 6


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Element holes
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 4 1 T47 2 T48 2


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] host 5 1 T159 1 T177 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%