Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49446203	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16333895

1

T1

255

T2

11566

T3

260

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58490050	1			T1	885		T2	47296		T3	1015
values[0x0]	3646835	1			T1	9		T2	409		T3	5
values[0x1]	3643213	1			T1	8		T2	429		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36353687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29426411

1

T1

419

T2

22344

T3

444

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	230193	1			T1	6		T2	200		T3	3
valid_sources[0x01]	471972	1			T1	2		T2	237		T3	5
valid_sources[0x02]	252730	1			T1	1		T2	156		T3	8
valid_sources[0x03]	237238	1			T1	11		T2	266		T3	7
valid_sources[0x04]	233282	1			T2	292		T3	8		T8	2
valid_sources[0x05]	255879	1			T1	14		T2	236		T3	3
valid_sources[0x06]	267165	1			T2	118		T3	10		T8	1
valid_sources[0x07]	481744	1			T2	278		T3	2		T8	2
valid_sources[0x08]	241647	1			T2	157		T3	2		T8	1
valid_sources[0x09]	220870	1			T2	219		T3	4		T8	2
valid_sources[0x0a]	403493	1			T2	222		T3	10		T8	2
valid_sources[0x0b]	230578	1			T1	5		T2	158		T3	5
valid_sources[0x0c]	216637	1			T1	5		T2	163		T3	2
valid_sources[0x0d]	460523	1			T2	107		T3	4		T7	24
valid_sources[0x0e]	221322	1			T1	5		T2	145		T3	4
valid_sources[0x0f]	970157	1			T1	2		T2	178		T3	2
valid_sources[0x10]	260740	1			T1	1		T2	93		T3	4
valid_sources[0x11]	214526	1			T1	2		T2	114		T3	3
valid_sources[0x12]	241484	1			T1	11		T2	205		T3	3
valid_sources[0x13]	227669	1			T2	241		T3	2		T8	3
valid_sources[0x14]	221674	1			T1	14		T2	181		T3	4
valid_sources[0x15]	242219	1			T1	2		T2	164		T3	4
valid_sources[0x16]	257033	1			T2	213		T3	4		T8	3
valid_sources[0x17]	235972	1			T1	2		T2	131		T3	2
valid_sources[0x18]	228665	1			T2	157		T3	4		T8	2
valid_sources[0x19]	237664	1			T1	16		T2	58		T3	1
valid_sources[0x1a]	235281	1			T2	89		T3	4		T7	15
valid_sources[0x1b]	239040	1			T1	2		T2	171		T3	9
valid_sources[0x1c]	245857	1			T1	3		T2	203		T3	5
valid_sources[0x1d]	240700	1			T2	117		T3	4		T8	4
valid_sources[0x1e]	214357	1			T1	1		T2	120		T3	4
valid_sources[0x1f]	220209	1			T2	166		T3	4		T8	6
valid_sources[0x20]	238723	1			T1	10		T2	215		T3	8
valid_sources[0x21]	231676	1			T1	11		T2	174		T3	4
valid_sources[0x22]	260450	1			T2	115		T3	3		T8	3
valid_sources[0x23]	222462	1			T1	9		T2	179		T3	6
valid_sources[0x24]	217166	1			T1	7		T2	342		T3	6
valid_sources[0x25]	233754	1			T2	152		T3	4		T8	4
valid_sources[0x26]	240844	1			T2	174		T3	4		T7	19
valid_sources[0x27]	235655	1			T2	245		T3	6		T8	3
valid_sources[0x28]	280543	1			T1	1		T2	155		T3	4
valid_sources[0x29]	247226	1			T2	130		T3	4		T8	1
valid_sources[0x2a]	221327	1			T2	145		T3	2		T8	2
valid_sources[0x2b]	221685	1			T2	174		T3	3		T8	4
valid_sources[0x2c]	243082	1			T2	97		T3	3		T7	11
valid_sources[0x2d]	228681	1			T1	14		T2	174		T3	8
valid_sources[0x2e]	292937	1			T2	238		T3	3		T8	1
valid_sources[0x2f]	231576	1			T2	206		T7	6		T16	13
valid_sources[0x30]	230803	1			T2	194		T3	5		T8	2
valid_sources[0x31]	217547	1			T2	188		T3	1		T7	8
valid_sources[0x32]	226743	1			T1	12		T2	174		T3	8
valid_sources[0x33]	419137	1			T1	14		T2	155		T3	10
valid_sources[0x34]	420190	1			T1	12		T2	336		T3	6
valid_sources[0x35]	446292	1			T1	4		T2	122		T3	1
valid_sources[0x36]	219444	1			T2	320		T3	5		T8	1
valid_sources[0x37]	224467	1			T2	223		T3	1		T7	26
valid_sources[0x38]	239983	1			T1	1		T2	199		T3	1
valid_sources[0x39]	231783	1			T2	191		T3	1		T8	1
valid_sources[0x3a]	237716	1			T2	240		T3	2		T8	2
valid_sources[0x3b]	227707	1			T1	8		T2	169		T3	8
valid_sources[0x3c]	250110	1			T2	165		T3	7		T7	12
valid_sources[0x3d]	230776	1			T1	4		T2	232		T3	4
valid_sources[0x3e]	259306	1			T2	273		T3	7		T8	1
valid_sources[0x3f]	238933	1			T1	3		T2	161		T3	3
valid_sources[0x40]	234880	1			T1	4		T2	272		T3	8
valid_sources[0x41]	229258	1			T2	134		T3	10		T7	34
valid_sources[0x42]	259613	1			T1	9		T2	111		T3	5
valid_sources[0x43]	225885	1			T2	279		T3	6		T8	2
valid_sources[0x44]	219277	1			T1	14		T2	241		T3	5
valid_sources[0x45]	238795	1			T1	9		T2	233		T3	7
valid_sources[0x46]	259891	1			T2	198		T3	3		T8	3
valid_sources[0x47]	222859	1			T1	1		T2	192		T3	4
valid_sources[0x48]	221339	1			T1	7		T2	274		T3	6
valid_sources[0x49]	244384	1			T1	12		T2	213		T3	3
valid_sources[0x4a]	240744	1			T2	158		T3	2		T7	25
valid_sources[0x4b]	223645	1			T2	351		T3	4		T7	10
valid_sources[0x4c]	217441	1			T2	192		T3	9		T7	15
valid_sources[0x4d]	273885	1			T1	10		T2	137		T3	3
valid_sources[0x4e]	234782	1			T1	2		T2	105		T3	8
valid_sources[0x4f]	241133	1			T2	348		T3	1		T7	23
valid_sources[0x50]	245343	1			T1	15		T2	323		T7	24
valid_sources[0x51]	235721	1			T2	58		T3	3		T8	1
valid_sources[0x52]	219177	1			T1	10		T2	61		T3	5
valid_sources[0x53]	229849	1			T1	2		T2	164		T3	9
valid_sources[0x54]	234033	1			T2	237		T3	11		T7	15
valid_sources[0x55]	234390	1			T1	4		T2	118		T3	8
valid_sources[0x56]	306212	1			T2	93		T3	2		T8	2
valid_sources[0x57]	226923	1			T1	6		T2	196		T3	2
valid_sources[0x58]	231783	1			T1	4		T2	274		T3	2
valid_sources[0x59]	226111	1			T1	21		T2	134		T3	3
valid_sources[0x5a]	282808	1			T1	12		T2	174		T3	7
valid_sources[0x5b]	285106	1			T2	232		T3	5		T8	1
valid_sources[0x5c]	217950	1			T1	1		T2	225		T3	4
valid_sources[0x5d]	243261	1			T1	14		T2	176		T3	3
valid_sources[0x5e]	219283	1			T1	4		T2	72		T3	3
valid_sources[0x5f]	217215	1			T1	12		T2	147		T3	2
valid_sources[0x60]	231144	1			T2	183		T3	2		T7	8
valid_sources[0x61]	248056	1			T2	211		T3	3		T7	56
valid_sources[0x62]	319392	1			T1	6		T2	98		T3	6
valid_sources[0x63]	223740	1			T1	4		T2	252		T3	5
valid_sources[0x64]	224644	1			T2	134		T3	3		T7	6
valid_sources[0x65]	224831	1			T2	336		T3	5		T8	4
valid_sources[0x66]	227150	1			T2	177		T3	4		T7	24
valid_sources[0x67]	240263	1			T2	203		T3	4		T8	2
valid_sources[0x68]	223999	1			T2	220		T3	3		T7	27
valid_sources[0x69]	227665	1			T1	1		T2	262		T3	4
valid_sources[0x6a]	453043	1			T1	3		T2	265		T3	1
valid_sources[0x6b]	227524	1			T2	302		T3	2		T8	5
valid_sources[0x6c]	244342	1			T2	348		T3	3		T8	1
valid_sources[0x6d]	260512	1			T1	5		T2	364		T3	2
valid_sources[0x6e]	239337	1			T2	232		T3	4		T8	2
valid_sources[0x6f]	225340	1			T2	229		T3	2		T8	1
valid_sources[0x70]	254255	1			T2	193		T3	6		T7	8
valid_sources[0x71]	240047	1			T1	2		T2	96		T3	3
valid_sources[0x72]	220989	1			T2	235		T3	3		T8	4
valid_sources[0x73]	440513	1			T2	342		T3	4		T8	1
valid_sources[0x74]	227306	1			T1	2		T2	211		T3	3
valid_sources[0x75]	291259	1			T2	158		T3	2		T8	4
valid_sources[0x76]	223569	1			T2	160		T3	3		T8	1
valid_sources[0x77]	226874	1			T2	129		T3	2		T7	23
valid_sources[0x78]	287398	1			T2	190		T3	5		T8	3
valid_sources[0x79]	376938	1			T1	7		T2	170		T3	6
valid_sources[0x7a]	259585	1			T1	3		T2	212		T3	3
valid_sources[0x7b]	222611	1			T2	223		T3	8		T8	1
valid_sources[0x7c]	469035	1			T1	1		T2	186		T3	5
valid_sources[0x7d]	221905	1			T2	350		T3	2		T7	11
valid_sources[0x7e]	220661	1			T2	222		T3	1		T8	1
valid_sources[0x7f]	234708	1			T1	3		T2	202		T3	11
valid_sources[0x80]	245772	1			T2	100		T3	4		T7	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13575968

1

T1

244

T2

11171

T3

249

values[0x0]

all_enables

biggest_size

1778534

1

T1

6

T2

232

T3

4

values[0x1]

all_enables

biggest_size

979393

1

T1

5

T2

163

T3

7