SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 93.75 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.b2b_txn_target_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.b2b_txn_host_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 1 | 7 | 87.50 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
b2b_read_different_addr | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_same_addr | 1 | 1 | T206 | 1 | - | - | - | - | ||||
write_after_read_different_addr | 19066 | 1 | T7 | 21 | T23 | 18 | T61 | 28 | ||||
write_after_read_same_addr | 335 | 1 | T172 | 13 | T35 | 3 | T173 | 23 | ||||
read_after_write_different_addr | 19058 | 1 | T7 | 21 | T23 | 18 | T61 | 28 | ||||
read_after_write_same_addr | 334 | 1 | T172 | 13 | T35 | 3 | T173 | 23 | ||||
b2b_write_different_addr | 36004 | 1 | T7 | 31 | T15 | 50 | T16 | 78 | ||||
b2b_write_same_addr | 380816 | 1 | T1 | 440 | T3 | 505 | T7 | 356 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 4236 | 1 | T2 | 2 | T9 | 10 | T10 | 3 | ||||
b2b_read_same_addr | 843 | 1 | T57 | 1 | T31 | 3 | T32 | 22 | ||||
write_after_read_different_addr | 4272 | 1 | T2 | 4 | T9 | 10 | T10 | 4 | ||||
write_after_read_same_addr | 63 | 1 | T10 | 1 | T11 | 1 | T32 | 1 | ||||
read_after_write_different_addr | 4283 | 1 | T2 | 4 | T9 | 9 | T10 | 5 | ||||
read_after_write_same_addr | 59 | 1 | T9 | 1 | T57 | 1 | T14 | 1 | ||||
b2b_write_different_addr | 4288 | 1 | T2 | 9 | T9 | 9 | T10 | 8 | ||||
b2b_write_same_addr | 792 | 1 | T11 | 1 | T32 | 12 | T12 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |