Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	551087766	17513	0	0
ctrl_rd_A	551087766	2273	0	0
fifo_ctrl_rd_A	551087766	5821	0	0
host_timeout_ctrl_rd_A	551087766	1704	0	0
intr_enable_rd_A	551087766	5693	0	0
ovrd_rd_A	551087766	2833	0	0
target_id_rd_A	551087766	2744	0	0
timeout_ctrl_rd_A	551087766	1791	0	0
timing0_rd_A	551087766	1853	0	0
timing1_rd_A	551087766	1894	0	0
timing2_rd_A	551087766	2023	0	0
timing3_rd_A	551087766	1749	0	0
timing4_rd_A	551087766	1902	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	17513	0	0
T69	7163	2	0	0
T70	2117	223	0	0
T71	8862	408	0	0
T72	9889	474	0	0
T76	11554	8	0	0
T79	7190	229	0	0
T80	2940	318	0	0
T87	6360	305	0	0
T88	2611	300	0	0
T108	4637	379	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	2273	0	0
T71	8862	24	0	0
T72	9889	7	0	0
T76	11554	145	0	0
T77	18553	157	0	0
T87	6360	34	0	0
T130	2536	14	0	0
T131	6247	111	0	0
T132	7308	19	0	0
T133	18303	58	0	0
T134	6691	15	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	5821	0	0
T11	378660	0	0	0
T21	244817	0	0	0
T25	217006	0	0	0
T27	323673	0	0	0
T32	259001	0	0	0
T39	0	113	0	0
T44	0	190	0	0
T45	16184	0	0	0
T49	333828	0	0	0
T68	342946	85	0	0
T111	142880	0	0	0
T112	212369	0	0	0
T135	0	86	0	0
T136	0	72	0	0
T137	0	132	0	0
T138	0	125	0	0
T139	0	32	0	0
T140	0	118	0	0
T141	0	157	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	1704	0	0
T71	8862	18	0	0
T72	9889	29	0	0
T76	11554	80	0	0
T77	18553	57	0	0
T79	7190	5	0	0
T87	6360	19	0	0
T130	2536	8	0	0
T131	6247	97	0	0
T132	7308	30	0	0
T133	18303	50	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	5693	0	0
T39	0	36	0	0
T44	123273	24	0	0
T71	0	38	0	0
T72	0	20	0	0
T131	0	83	0	0
T140	0	17	0	0
T142	0	16	0	0
T143	0	7	0	0
T144	0	34	0	0
T145	0	9	0	0
T146	181194	0	0	0
T147	358347	0	0	0
T148	148678	0	0	0
T149	308931	0	0	0
T150	2823	0	0	0
T151	118271	0	0	0
T152	242879	0	0	0
T153	66706	0	0	0
T154	14245	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	2833	0	0
T4	1605	69	0	0
T10	351630	0	0	0
T33	80724	0	0	0
T37	111990	0	0	0
T57	557236	0	0	0
T63	108197	0	0	0
T109	96959	0	0	0
T110	116522	0	0	0
T155	0	44	0	0
T156	0	55	0	0
T157	0	48	0	0
T158	0	16	0	0
T159	0	70	0	0
T160	0	33	0	0
T161	0	36	0	0
T162	0	74	0	0
T163	0	36	0	0
T164	227287	0	0	0
T165	63169	0	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	2744	0	0
T71	8862	17	0	0
T72	9889	15	0	0
T76	11554	204	0	0
T77	18553	239	0	0
T79	7190	1	0	0
T87	6360	35	0	0
T130	2536	12	0	0
T131	6247	95	0	0
T132	7308	8	0	0
T133	18303	59	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	1791	0	0
T71	8862	14	0	0
T72	9889	6	0	0
T76	11554	95	0	0
T77	18553	113	0	0
T79	7190	12	0	0
T87	6360	16	0	0
T130	2536	7	0	0
T131	6247	69	0	0
T132	7308	24	0	0
T133	18303	31	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	1853	0	0
T71	8862	31	0	0
T72	9889	6	0	0
T76	11554	118	0	0
T77	18553	102	0	0
T79	7190	13	0	0
T87	6360	14	0	0
T130	2536	3	0	0
T131	6247	106	0	0
T132	7308	4	0	0
T133	18303	71	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	1894	0	0
T71	8862	13	0	0
T72	9889	5	0	0
T76	11554	119	0	0
T77	18553	87	0	0
T79	7190	15	0	0
T87	6360	14	0	0
T130	2536	22	0	0
T131	6247	115	0	0
T132	7308	12	0	0
T133	18303	29	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	2023	0	0
T71	8862	23	0	0
T72	9889	29	0	0
T76	11554	108	0	0
T77	18553	138	0	0
T79	7190	26	0	0
T87	6360	3	0	0
T130	2536	6	0	0
T131	6247	73	0	0
T132	7308	5	0	0
T133	18303	56	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	1749	0	0
T71	8862	23	0	0
T72	9889	7	0	0
T76	11554	87	0	0
T77	18553	101	0	0
T79	7190	5	0	0
T87	6360	16	0	0
T130	2536	24	0	0
T131	6247	106	0	0
T133	18303	34	0	0
T134	6691	9	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551087766	1902	0	0
T71	8862	12	0	0
T72	9889	9	0	0
T76	11554	104	0	0
T77	18553	145	0	0
T79	7190	14	0	0
T87	6360	11	0	0
T131	6247	89	0	0
T132	7308	3	0	0
T133	18303	66	0	0
T134	6691	23	0	0