Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

234628

1

T3

1

T9

1

T26

685

ack

19059

1

T3

39

T9

3

T10

49

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	945	1			T26	2		T33	1		T27	2
high	52047	1			T3	2		T10	2		T26	150
med	94312	1			T3	5		T10	7		T26	292
sml	105378	1			T3	33		T9	3		T10	40
all_zero	1005	1			T9	1		T27	3		T188	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126590

1

T3

21

T9

2

T10

23

auto[1]

127097

1

T3

19

T9

2

T10

26

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173072

1

T3

22

T9

2

T10

32

auto[1]

80615

1

T3

18

T9

2

T10

17

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242713

1

T3

12

T9

1

T10

16

auto[1]

10974

1

T3

28

T9

3

T10

33

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239823

1

T3

29

T9

3

T10

33

auto[1]

13864

1

T3

11

T9

1

T10

16

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241626

1

T3

29

T9

3

T10

33

auto[1]

12061

1

T3

11

T9

1

T10

16

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126590

1

T3

21

T9

2

T10

23

auto[1]

127097

1

T3

19

T9

2

T10

26

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173072

1

T3

22

T9

2

T10

32

auto[1]

80615

1

T3

18

T9

2

T10

17

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242713

1

T3

12

T9

1

T10

16

auto[1]

10974

1

T3

28

T9

3

T10

33

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239823

1

T3

29

T9

3

T10

33

auto[1]

13864

1

T3

11

T9

1

T10

16

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241626

1

T3

29

T9

3

T10

33

auto[1]

12061

1

T3

11

T9

1

T10

16

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T209

1

T210

1

T211

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T209

1

T212

1

T213

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T214

1

T215

1

T212

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

604

1

T56

1

T27

3

T216

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

298

1

T13

2

T14

3

T107

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

313

1

T56

2

T27

1

T12

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1115

1

T26

2

T56

4

T27

11

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

591

1

T27

4

T216

1

T28

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

532

1

T26

2

T56

6

T27

4

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1124

1

T26

1

T56

1

T27

9

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

594

1

T56

1

T27

6

T12

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

572

1

T27

3

T188

1

T216

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

23

1

T27

1

T217

1

T218

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

9

1

T219

1

T137

1

T220

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T221

1

T222

1

T223

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	73909	1			T26	232		T56	40		T27	105
write_address_byte	13864	1			T3	11		T9	1		T10	16
read_with_ack	3967	1			T3	18		T9	2		T10	17
read_with_nack	7007	1			T3	10		T9	1		T10	16
stop_byte	12061	1			T3	11		T9	1		T10	16
write_address_byte_nak	8982	1			T26	14		T56	21		T27	54
data_byte_nack	234628	1			T3	1		T9	1		T26	685
stop_byte_nack	8683	1			T3	1		T26	5		T56	17
nakok_byte_nack	117577	1			T26	336		T56	64		T27	184
nakok_addr_byte_nack	4393	1			T26	7		T56	10		T27	27