Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48529296	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16287495

1

T1

209

T2

3218

T3

36047

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57635534	1			T1	561		T2	19103		T3	83265
values[0x0]	3591970	1			T1	145		T2	5049		T3	11662
values[0x1]	3589287	1			T1	136		T2	4854		T3	11428

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35753782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29063009

1

T1

351

T2

10034

T3

54358

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	223572	1			T3	500		T11	5		T7	4
valid_sources[0x01]	939023	1			T3	396		T11	5		T7	1
valid_sources[0x02]	222873	1			T3	532		T11	7		T7	7
valid_sources[0x03]	208835	1			T3	397		T11	4		T7	2
valid_sources[0x04]	230955	1			T3	525		T11	11		T7	8
valid_sources[0x05]	243949	1			T1	28		T3	476		T11	5
valid_sources[0x06]	266784	1			T1	6		T3	409		T11	5
valid_sources[0x07]	338704	1			T3	290		T11	4		T8	1
valid_sources[0x08]	218157	1			T1	1		T3	262		T11	2
valid_sources[0x09]	237727	1			T3	361		T11	5		T7	13
valid_sources[0x0a]	231854	1			T3	527		T11	9		T7	3
valid_sources[0x0b]	209276	1			T3	607		T11	5		T8	1
valid_sources[0x0c]	225091	1			T3	460		T11	4		T7	8
valid_sources[0x0d]	231494	1			T3	410		T11	4		T7	1
valid_sources[0x0e]	221014	1			T3	389		T11	12		T7	5
valid_sources[0x0f]	213898	1			T1	17		T3	459		T11	10
valid_sources[0x10]	221295	1			T3	373		T11	16		T7	15
valid_sources[0x11]	278619	1			T3	513		T11	12		T7	6
valid_sources[0x12]	221727	1			T3	364		T11	12		T7	10
valid_sources[0x13]	229232	1			T1	31		T3	430		T7	2
valid_sources[0x14]	224197	1			T3	497		T11	14		T7	17
valid_sources[0x15]	258288	1			T3	442		T11	12		T8	2
valid_sources[0x16]	897923	1			T3	372		T11	10		T8	4
valid_sources[0x17]	209688	1			T3	456		T11	7		T8	12
valid_sources[0x18]	229183	1			T3	380		T11	13		T7	4
valid_sources[0x19]	231289	1			T1	10		T3	489		T11	4
valid_sources[0x1a]	248504	1			T3	292		T11	7		T8	2
valid_sources[0x1b]	228322	1			T3	339		T11	7		T7	10
valid_sources[0x1c]	208477	1			T3	382		T11	7		T8	6
valid_sources[0x1d]	218445	1			T3	481		T7	4		T18	8
valid_sources[0x1e]	203981	1			T3	498		T11	5		T7	4
valid_sources[0x1f]	238005	1			T3	364		T11	1		T7	1
valid_sources[0x20]	207983	1			T1	9		T3	423		T11	4
valid_sources[0x21]	449778	1			T1	16		T3	306		T11	9
valid_sources[0x22]	204032	1			T3	471		T11	13		T18	4
valid_sources[0x23]	205524	1			T3	477		T11	8		T7	2
valid_sources[0x24]	281243	1			T3	397		T11	10		T7	7
valid_sources[0x25]	232400	1			T3	432		T11	7		T7	1
valid_sources[0x26]	220554	1			T3	540		T11	6		T7	14
valid_sources[0x27]	277126	1			T1	1		T3	278		T11	11
valid_sources[0x28]	211439	1			T3	367		T11	2		T7	6
valid_sources[0x29]	208868	1			T3	443		T11	12		T7	3
valid_sources[0x2a]	214268	1			T3	459		T11	9		T18	8
valid_sources[0x2b]	246504	1			T1	14		T3	334		T11	5
valid_sources[0x2c]	215596	1			T3	425		T11	5		T7	1
valid_sources[0x2d]	206869	1			T3	392		T11	8		T7	5
valid_sources[0x2e]	260066	1			T3	629		T11	2		T7	3
valid_sources[0x2f]	213786	1			T3	441		T11	1		T18	13
valid_sources[0x30]	205080	1			T3	404		T11	14		T7	3
valid_sources[0x31]	216764	1			T2	3732		T3	346		T11	8
valid_sources[0x32]	224694	1			T3	435		T11	16		T7	5
valid_sources[0x33]	241515	1			T3	434		T11	3		T7	7
valid_sources[0x34]	207279	1			T3	676		T11	6		T7	10
valid_sources[0x35]	201193	1			T3	451		T11	15		T7	16
valid_sources[0x36]	220336	1			T3	457		T11	9		T7	15
valid_sources[0x37]	212573	1			T3	550		T11	7		T7	8
valid_sources[0x38]	512696	1			T3	307		T11	6		T7	11
valid_sources[0x39]	224244	1			T1	6		T3	436		T11	23
valid_sources[0x3a]	218314	1			T3	370		T11	7		T7	7
valid_sources[0x3b]	217658	1			T1	1		T3	431		T11	12
valid_sources[0x3c]	223620	1			T3	308		T11	3		T7	13
valid_sources[0x3d]	249653	1			T3	376		T11	4		T7	16
valid_sources[0x3e]	339902	1			T1	23		T3	357		T11	2
valid_sources[0x3f]	228589	1			T3	276		T11	10		T7	4
valid_sources[0x40]	206427	1			T3	480		T11	18		T18	3
valid_sources[0x41]	661863	1			T3	386		T11	2		T7	11
valid_sources[0x42]	208433	1			T3	302		T11	8		T7	1
valid_sources[0x43]	246056	1			T2	4135		T3	319		T11	12
valid_sources[0x44]	238957	1			T3	394		T11	6		T7	12
valid_sources[0x45]	236841	1			T3	406		T18	4		T19	15
valid_sources[0x46]	1220289	1			T3	401		T11	12		T8	3
valid_sources[0x47]	217091	1			T3	379		T11	20		T7	3
valid_sources[0x48]	502893	1			T3	361		T11	4		T7	2
valid_sources[0x49]	253107	1			T3	434		T11	4		T7	10
valid_sources[0x4a]	215801	1			T3	431		T11	10		T7	10
valid_sources[0x4b]	232666	1			T3	331		T11	1		T7	5
valid_sources[0x4c]	311139	1			T1	22		T3	381		T11	6
valid_sources[0x4d]	226099	1			T3	474		T11	2		T7	12
valid_sources[0x4e]	239404	1			T3	359		T7	3		T18	10
valid_sources[0x4f]	213344	1			T3	365		T11	6		T7	3
valid_sources[0x50]	210080	1			T3	523		T11	13		T7	12
valid_sources[0x51]	228995	1			T3	418		T11	4		T7	7
valid_sources[0x52]	212145	1			T3	400		T11	4		T18	6
valid_sources[0x53]	217902	1			T3	579		T11	4		T8	1
valid_sources[0x54]	220089	1			T1	49		T3	487		T11	8
valid_sources[0x55]	209445	1			T3	468		T11	3		T7	23
valid_sources[0x56]	268056	1			T3	284		T11	6		T8	1
valid_sources[0x57]	228507	1			T3	314		T11	5		T7	15
valid_sources[0x58]	266929	1			T3	450		T11	3		T7	5
valid_sources[0x59]	238473	1			T3	313		T11	8		T7	18
valid_sources[0x5a]	210930	1			T3	400		T11	7		T8	6
valid_sources[0x5b]	211379	1			T3	471		T11	5		T7	9
valid_sources[0x5c]	222734	1			T3	472		T11	13		T7	6
valid_sources[0x5d]	216908	1			T3	562		T11	2		T7	10
valid_sources[0x5e]	375009	1			T1	68		T3	437		T11	3
valid_sources[0x5f]	212676	1			T3	399		T11	12		T7	13
valid_sources[0x60]	228037	1			T1	4		T3	272		T11	6
valid_sources[0x61]	216832	1			T1	2		T3	244		T11	6
valid_sources[0x62]	211722	1			T3	324		T11	8		T7	9
valid_sources[0x63]	206400	1			T3	377		T11	3		T7	33
valid_sources[0x64]	208940	1			T3	334		T11	5		T7	3
valid_sources[0x65]	230064	1			T3	458		T11	7		T7	3
valid_sources[0x66]	240352	1			T3	442		T11	9		T7	5
valid_sources[0x67]	510158	1			T3	560		T11	4		T7	8
valid_sources[0x68]	224355	1			T3	407		T11	8		T7	6
valid_sources[0x69]	211646	1			T3	399		T11	8		T8	10
valid_sources[0x6a]	245571	1			T2	13500		T3	514		T11	9
valid_sources[0x6b]	205319	1			T3	376		T11	7		T7	14
valid_sources[0x6c]	430574	1			T3	529		T11	13		T9	209351
valid_sources[0x6d]	214093	1			T3	427		T11	3		T8	2
valid_sources[0x6e]	210487	1			T3	312		T11	2		T7	4
valid_sources[0x6f]	224422	1			T3	473		T11	5		T7	7
valid_sources[0x70]	253306	1			T1	48		T3	334		T11	5
valid_sources[0x71]	254131	1			T3	306		T11	3		T8	10
valid_sources[0x72]	205779	1			T3	360		T11	10		T7	6
valid_sources[0x73]	219619	1			T3	418		T11	3		T7	13
valid_sources[0x74]	222796	1			T3	503		T11	10		T8	3
valid_sources[0x75]	246146	1			T3	382		T11	10		T8	1
valid_sources[0x76]	212375	1			T3	498		T11	5		T7	15
valid_sources[0x77]	218539	1			T3	312		T11	11		T7	6
valid_sources[0x78]	219465	1			T3	386		T11	14		T7	20
valid_sources[0x79]	216772	1			T3	345		T11	11		T7	1
valid_sources[0x7a]	226849	1			T3	393		T11	5		T18	15
valid_sources[0x7b]	222491	1			T1	26		T3	549		T11	8
valid_sources[0x7c]	229739	1			T3	422		T11	6		T7	3
valid_sources[0x7d]	246368	1			T3	363		T11	12		T7	25
valid_sources[0x7e]	208266	1			T3	432		T11	15		T8	1
valid_sources[0x7f]	212532	1			T3	503		T11	6		T7	6
valid_sources[0x80]	220637	1			T3	410		T11	1		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13564720

1

T1

121

T2

151

T3

26966

values[0x0]

all_enables

biggest_size

1755498

1

T1

59

T2

2059

T3

5975

values[0x1]

all_enables

biggest_size

967277

1

T1

29

T2

1008

T3

3106