Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.79	100.00	87.18			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_rxfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_txfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_fmtfifo	97.12	100.00	88.46			100.00	100.00
tb.dut.i2c_core.u_i2c_acqfifo	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_txfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fmtfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_acqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
97.12	88.46

tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T62,T12

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T3,T10,T26
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T10,T26
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T13,T14
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T41,T57
1	0	1	Covered	T3,T11,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T26,T62,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T62,T12

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T11,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=10,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
97.12	88.46

tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T46,T47
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T63,T64
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T26

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T15,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T26

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T11,T26
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	661752742	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	661752742	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	661752742	0	0
T1	219722	43087	0	0
T2	528598	123271	0	0
T3	892544	228375	0	0
T7	622116	86649	0	0
T8	11756	406	0	0
T9	1020676	264115	0	0
T10	513650	263051	0	0
T11	69044	31735	0	0
T15	0	170761	0	0
T16	0	159018	0	0
T18	1259912	314804	0	0
T19	912280	227922	0	0
T20	3435072	486678	0	0
T21	0	109562	0	0
T26	1165390	605232	0	0
T31	0	57885	0	0
T41	0	265960	0	0
T57	0	200233	0	0
T58	0	1426	0	0
T65	0	36458	0	0
T66	0	19370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	439444	439052	0	0
T2	1057196	1056880	0	0
T3	892544	891956	0	0
T7	622116	621856	0	0
T8	11756	10020	0	0
T9	1020676	1020640	0	0
T11	69044	68680	0	0
T18	1259912	1259884	0	0
T19	912280	912252	0	0
T20	3435072	3434024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	439444	439052	0	0
T2	1057196	1056880	0	0
T3	892544	891956	0	0
T7	622116	621856	0	0
T8	11756	10020	0	0
T9	1020676	1020640	0	0
T11	69044	68680	0	0
T18	1259912	1259884	0	0
T19	912280	912252	0	0
T20	3435072	3434024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	439444	439052	0	0
T2	1057196	1056880	0	0
T3	892544	891956	0	0
T7	622116	621856	0	0
T8	11756	10020	0	0
T9	1020676	1020640	0	0
T11	69044	68680	0	0
T18	1259912	1259884	0	0
T19	912280	912252	0	0
T20	3435072	3434024	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	661752742	0	0
T1	219722	43087	0	0
T2	528598	123271	0	0
T3	892544	228375	0	0
T7	622116	86649	0	0
T8	11756	406	0	0
T9	1020676	264115	0	0
T10	513650	263051	0	0
T11	69044	31735	0	0
T15	0	170761	0	0
T16	0	159018	0	0
T18	1259912	314804	0	0
T19	912280	227922	0	0
T20	3435072	486678	0	0
T21	0	109562	0	0
T26	1165390	605232	0	0
T31	0	57885	0	0
T41	0	265960	0	0
T57	0	200233	0	0
T58	0	1426	0	0
T65	0	36458	0	0
T66	0	19370	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T26,T15

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T3,T9,T10
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T9,T10
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T12,T13
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T11,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T26,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T26,T15

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T11,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T26,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T9,T10

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T9

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539900328	43723058	0	0
DepthKnown_A	539900328	539720526	0	0
RvalidKnown_A	539900328	539720526	0	0
WreadyKnown_A	539900328	539720526	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539900328	43723058	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	43723058	0	0
T3	223136	8919	0	0
T7	155529	0	0	0
T8	2939	0	0	0
T9	255169	9159	0	0
T10	256825	9851	0	0
T11	17261	15601	0	0
T15	0	60217	0	0
T18	314978	0	0	0
T19	228070	0	0	0
T20	858768	0	0	0
T26	582695	32150	0	0
T41	0	15511	0	0
T57	0	32526	0	0
T65	0	1626	0	0
T66	0	19370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	43723058	0	0
T3	223136	8919	0	0
T7	155529	0	0	0
T8	2939	0	0	0
T9	255169	9159	0	0
T10	256825	9851	0	0
T11	17261	15601	0	0
T15	0	60217	0	0
T18	314978	0	0	0
T19	228070	0	0	0
T20	858768	0	0	0
T26	582695	32150	0	0
T41	0	15511	0	0
T57	0	32526	0	0
T65	0	1626	0	0
T66	0	19370	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T16,T17

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T16,T17
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T16,T17

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T17
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539900328	163020349	0	0
DepthKnown_A	539900328	539720526	0	0
RvalidKnown_A	539900328	539720526	0	0
WreadyKnown_A	539900328	539720526	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539900328	163020349	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	163020349	0	0
T1	109861	32203	0	0
T2	264299	263903	0	0
T3	223136	0	0	0
T7	155529	96086	0	0
T8	2939	0	0	0
T9	255169	0	0	0
T11	17261	0	0	0
T16	0	284706	0	0
T17	0	258880	0	0
T18	314978	0	0	0
T19	228070	0	0	0
T20	858768	337965	0	0
T21	0	77212	0	0
T29	0	33864	0	0
T31	0	87815	0	0
T58	0	88123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	163020349	0	0
T1	109861	32203	0	0
T2	264299	263903	0	0
T3	223136	0	0	0
T7	155529	96086	0	0
T8	2939	0	0	0
T9	255169	0	0	0
T11	17261	0	0	0
T16	0	284706	0	0
T17	0	258880	0	0
T18	314978	0	0	0
T19	228070	0	0	0
T20	858768	337965	0	0
T21	0	77212	0	0
T29	0	33864	0	0
T31	0	87815	0	0
T58	0	88123	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T62,T12

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T3,T10,T26
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T10,T26
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T13,T14
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T41,T57
1	0	1	Covered	T3,T11,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T26,T62,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T62,T12

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T11,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T62,T12
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T10,T26

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539900328	181943130	0	0
DepthKnown_A	539900328	539720526	0	0
RvalidKnown_A	539900328	539720526	0	0
WreadyKnown_A	539900328	539720526	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539900328	181943130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	181943130	0	0
T3	223136	219456	0	0
T7	155529	0	0	0
T8	2939	406	0	0
T9	255169	254956	0	0
T10	256825	253200	0	0
T11	17261	16134	0	0
T15	0	110544	0	0
T18	314978	0	0	0
T19	228070	0	0	0
T20	858768	0	0	0
T26	582695	573082	0	0
T41	0	250449	0	0
T57	0	167707	0	0
T65	0	34832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	181943130	0	0
T3	223136	219456	0	0
T7	155529	0	0	0
T8	2939	406	0	0
T9	255169	254956	0	0
T10	256825	253200	0	0
T11	17261	16134	0	0
T15	0	110544	0	0
T18	314978	0	0	0
T19	228070	0	0	0
T20	858768	0	0	0
T26	582695	573082	0	0
T41	0	250449	0	0
T57	0	167707	0	0
T65	0	34832	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T46,T47
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T63,T64
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539900328	273066205	0	0
DepthKnown_A	539900328	539720526	0	0
RvalidKnown_A	539900328	539720526	0	0
WreadyKnown_A	539900328	539720526	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539900328	273066205	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	273066205	0	0
T1	109861	43087	0	0
T2	264299	123271	0	0
T3	223136	0	0	0
T7	155529	86649	0	0
T8	2939	0	0	0
T9	255169	0	0	0
T11	17261	0	0	0
T16	0	159018	0	0
T18	314978	314804	0	0
T19	228070	227922	0	0
T20	858768	486678	0	0
T21	0	109562	0	0
T31	0	57885	0	0
T58	0	1426	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	273066205	0	0
T1	109861	43087	0	0
T2	264299	123271	0	0
T3	223136	0	0	0
T7	155529	86649	0	0
T8	2939	0	0	0
T9	255169	0	0	0
T11	17261	0	0	0
T16	0	159018	0	0
T18	314978	314804	0	0
T19	228070	227922	0	0
T20	858768	486678	0	0
T21	0	109562	0	0
T31	0	57885	0	0
T58	0	1426	0	0