Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

225186

1

T8

1262

T10

892

T21

524

ack

17602

1

T8

38

T9

36

T10

44

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	900	1			T8	7		T10	4		T21	1
high	49748	1			T8	278		T9	4		T10	190
med	90649	1			T8	508		T9	9		T10	364
sml	100506	1			T8	502		T9	23		T10	369
all_zero	985	1			T8	5		T10	9		T21	6

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120829

1

T8

649

T9

23

T10

480

auto[1]

121959

1

T8

651

T9

13

T10

456

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165822

1

T8

895

T9

31

T10

632

auto[1]

76966

1

T8

405

T9

5

T10

304

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232735

1

T8

1286

T9

16

T10

917

auto[1]

10053

1

T8

14

T9

20

T10

19

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229775

1

T8

1271

T9

20

T10

899

auto[1]

13013

1

T8

29

T9

16

T10

37

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231460

1

T8

1272

T9

21

T10

904

auto[1]

11328

1

T8

28

T9

15

T10

32

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120829

1

T8

649

T9

23

T10

480

auto[1]

121959

1

T8

651

T9

13

T10

456

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165822

1

T8

895

T9

31

T10

632

auto[1]

76966

1

T8

405

T9

5

T10

304

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232735

1

T8

1286

T9

16

T10

917

auto[1]

10053

1

T8

14

T9

20

T10

19

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229775

1

T8

1271

T9

20

T10

899

auto[1]

13013

1

T8

29

T9

16

T10

37

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231460

1

T8

1272

T9

21

T10

904

auto[1]

11328

1

T8

28

T9

15

T10

32

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T196

1

T197

2

T198

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T8

1

T169

1

T138

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T169

1

T199

1

T200

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

569

1

T8

3

T10

1

T27

9

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

297

1

T10

1

T27

1

T62

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

309

1

T8

2

T10

2

T21

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1009

1

T8

3

T10

1

T21

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

524

1

T10

1

T27

6

T11

9

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

520

1

T8

2

T10

1

T27

6

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1004

1

T8

3

T27

8

T62

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

504

1

T8

2

T10

2

T27

9

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

520

1

T8

3

T10

1

T21

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

9

1

T178

1

T201

1

T202

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

11

1

T203

1

T204

1

T36

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T205

2

T204

1

T206

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	71015	1			T8	425		T10	288		T21	160
write_address_byte	13013	1			T8	29		T9	16		T10	37
read_with_ack	3528	1			T9	5		T10	4		T53	11
read_with_nack	6525	1			T8	14		T9	15		T10	15
stop_byte	11328	1			T8	28		T9	15		T10	32
write_address_byte_nak	8385	1			T8	28		T10	22		T21	11
data_byte_nack	225186	1			T8	1262		T10	892		T21	524
stop_byte_nack	8186	1			T8	27		T10	23		T21	11
nakok_byte_nack	113210	1			T8	633		T10	442		T21	268
nakok_addr_byte_nack	4242	1			T8	17		T10	9		T21	7