Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46704080	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16464361

1

T1

12

T2

47

T3

238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55757990	1			T1	18		T2	121		T3	807
values[0x0]	3705860	1			T1	12		T2	63		T3	114
values[0x1]	3704591	1			T1	8		T2	51		T3	151

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34373565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28794876

1

T1

16

T2

101

T3

452

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	207209	1			T2	5		T3	3		T8	364
valid_sources[0x01]	327990	1			T2	1		T3	7		T8	342
valid_sources[0x02]	242472	1			T3	2		T8	393		T7	1
valid_sources[0x03]	204524	1			T2	1		T3	4		T8	358
valid_sources[0x04]	205257	1			T2	4		T3	2		T8	479
valid_sources[0x05]	229092	1			T2	1		T3	4		T8	364
valid_sources[0x06]	204262	1			T3	7		T8	303		T6	2
valid_sources[0x07]	222808	1			T2	5		T3	5		T8	367
valid_sources[0x08]	1102613	1			T2	3		T3	8		T8	290
valid_sources[0x09]	218829	1			T2	2		T3	6		T8	342
valid_sources[0x0a]	206892	1			T2	1		T3	1		T8	409
valid_sources[0x0b]	215341	1			T3	9		T8	381		T6	2
valid_sources[0x0c]	216383	1			T3	3		T8	366		T6	1
valid_sources[0x0d]	229172	1			T3	1		T8	367		T7	8
valid_sources[0x0e]	213082	1			T3	3		T8	399		T6	2
valid_sources[0x0f]	223301	1			T2	2		T3	9		T8	415
valid_sources[0x10]	254315	1			T2	7		T3	7		T8	316
valid_sources[0x11]	217777	1			T2	3		T3	9		T8	381
valid_sources[0x12]	211938	1			T3	3		T8	359		T6	2
valid_sources[0x13]	256996	1			T2	2		T3	3		T8	428
valid_sources[0x14]	208459	1			T3	4		T8	301		T6	2
valid_sources[0x15]	207939	1			T2	4		T3	3		T8	340
valid_sources[0x16]	392342	1			T3	4		T8	315		T6	1
valid_sources[0x17]	205866	1			T3	3		T8	285		T6	2
valid_sources[0x18]	205474	1			T3	4		T8	308		T6	1
valid_sources[0x19]	635723	1			T2	2		T3	3		T8	411
valid_sources[0x1a]	231073	1			T3	4		T8	301		T6	4
valid_sources[0x1b]	205634	1			T2	1		T3	5		T8	285
valid_sources[0x1c]	204800	1			T3	6		T8	367		T6	1
valid_sources[0x1d]	209208	1			T3	9		T8	319		T6	1
valid_sources[0x1e]	224024	1			T2	1		T3	5		T8	353
valid_sources[0x1f]	202584	1			T3	4		T8	374		T7	19
valid_sources[0x20]	232176	1			T3	9		T8	316		T6	1
valid_sources[0x21]	234505	1			T3	4		T8	353		T6	1
valid_sources[0x22]	205589	1			T2	1		T3	4		T8	387
valid_sources[0x23]	221351	1			T3	5		T8	421		T9	103
valid_sources[0x24]	325579	1			T2	3		T3	3		T8	360
valid_sources[0x25]	199687	1			T2	1		T3	3		T8	314
valid_sources[0x26]	521570	1			T3	3		T8	391		T7	15
valid_sources[0x27]	209929	1			T2	3		T3	10		T8	341
valid_sources[0x28]	210900	1			T3	6		T8	366		T6	3
valid_sources[0x29]	375529	1			T3	6		T8	327		T7	1
valid_sources[0x2a]	349400	1			T3	1		T8	370		T6	1
valid_sources[0x2b]	207805	1			T3	7		T8	338		T6	2
valid_sources[0x2c]	269597	1			T2	1		T8	397		T6	2
valid_sources[0x2d]	210291	1			T3	3		T8	415		T6	1
valid_sources[0x2e]	203034	1			T3	1		T8	290		T7	1
valid_sources[0x2f]	253081	1			T3	8		T8	377		T6	2
valid_sources[0x30]	231405	1			T2	1		T3	1		T8	379
valid_sources[0x31]	207316	1			T3	5		T8	356		T6	2
valid_sources[0x32]	199356	1			T2	1		T3	5		T8	301
valid_sources[0x33]	249323	1			T3	2		T8	330		T6	3
valid_sources[0x34]	201745	1			T3	5		T8	310		T6	4
valid_sources[0x35]	198799	1			T3	4		T8	380		T6	3
valid_sources[0x36]	199283	1			T3	2		T8	256		T6	2
valid_sources[0x37]	199320	1			T3	4		T8	366		T6	3
valid_sources[0x38]	225638	1			T2	2		T3	3		T8	387
valid_sources[0x39]	309586	1			T3	6		T8	417		T6	3
valid_sources[0x3a]	208565	1			T3	5		T8	324		T6	2
valid_sources[0x3b]	210542	1			T3	2		T8	346		T6	1
valid_sources[0x3c]	202613	1			T2	3		T3	6		T8	342
valid_sources[0x3d]	227310	1			T3	3		T8	392		T7	3
valid_sources[0x3e]	217288	1			T3	5		T8	322		T6	2
valid_sources[0x3f]	211490	1			T2	1		T3	3		T8	322
valid_sources[0x40]	200282	1			T3	5		T8	330		T6	3
valid_sources[0x41]	233463	1			T3	6		T8	369		T6	5
valid_sources[0x42]	198715	1			T3	7		T8	346		T6	3
valid_sources[0x43]	197807	1			T3	6		T8	451		T7	9
valid_sources[0x44]	202103	1			T3	3		T8	224		T6	1
valid_sources[0x45]	229644	1			T3	3		T8	338		T6	6
valid_sources[0x46]	239103	1			T2	4		T3	6		T8	387
valid_sources[0x47]	203639	1			T2	2		T8	291		T6	3
valid_sources[0x48]	220285	1			T3	4		T8	380		T9	111
valid_sources[0x49]	201470	1			T3	4		T8	384		T6	1
valid_sources[0x4a]	207568	1			T2	1		T3	3		T8	333
valid_sources[0x4b]	213625	1			T2	3		T3	6		T8	400
valid_sources[0x4c]	203614	1			T3	3		T8	362		T6	2
valid_sources[0x4d]	205514	1			T3	3		T8	410		T7	6
valid_sources[0x4e]	200250	1			T2	1		T3	3		T8	347
valid_sources[0x4f]	209143	1			T3	1		T8	371		T6	1
valid_sources[0x50]	228426	1			T3	4		T8	303		T6	3
valid_sources[0x51]	213386	1			T3	2		T8	401		T6	1
valid_sources[0x52]	200482	1			T3	6		T8	320		T6	2
valid_sources[0x53]	224506	1			T2	1		T3	4		T8	315
valid_sources[0x54]	212938	1			T3	7		T8	261		T6	1
valid_sources[0x55]	205268	1			T2	7		T3	5		T8	367
valid_sources[0x56]	573404	1			T3	6		T8	338		T6	349175
valid_sources[0x57]	218289	1			T2	1		T3	3		T8	362
valid_sources[0x58]	276602	1			T3	7		T8	389		T6	2
valid_sources[0x59]	207039	1			T3	3		T8	305		T6	1
valid_sources[0x5a]	217332	1			T3	2		T8	358		T7	2
valid_sources[0x5b]	298203	1			T3	3		T8	393		T6	1
valid_sources[0x5c]	201647	1			T3	5		T8	245		T9	76
valid_sources[0x5d]	213750	1			T2	1		T8	316		T6	2
valid_sources[0x5e]	208402	1			T3	4		T8	370		T6	1
valid_sources[0x5f]	232476	1			T2	1		T3	4		T8	339
valid_sources[0x60]	403491	1			T3	6		T8	387		T6	1
valid_sources[0x61]	199154	1			T3	2		T8	273		T6	1
valid_sources[0x62]	219157	1			T3	4		T8	424		T6	3
valid_sources[0x63]	312525	1			T3	7		T8	360		T6	1
valid_sources[0x64]	207770	1			T3	2		T8	363		T6	3
valid_sources[0x65]	234698	1			T2	1		T3	3		T8	342
valid_sources[0x66]	199729	1			T3	2		T8	408		T6	3
valid_sources[0x67]	235981	1			T3	5		T8	297		T6	1
valid_sources[0x68]	205217	1			T3	5		T8	327		T6	1
valid_sources[0x69]	226281	1			T2	2		T3	4		T8	400
valid_sources[0x6a]	196315	1			T3	6		T8	335		T6	1
valid_sources[0x6b]	257586	1			T3	2		T8	356		T7	5
valid_sources[0x6c]	202036	1			T3	5		T8	370		T6	2
valid_sources[0x6d]	204866	1			T2	2		T3	1		T8	423
valid_sources[0x6e]	202590	1			T3	4		T8	343		T7	7
valid_sources[0x6f]	201085	1			T3	3		T8	311		T6	1
valid_sources[0x70]	330706	1			T2	1		T3	8		T8	400
valid_sources[0x71]	203872	1			T3	2		T8	386		T7	4
valid_sources[0x72]	239241	1			T2	1		T3	4		T8	372
valid_sources[0x73]	243367	1			T3	7		T8	387		T6	1
valid_sources[0x74]	421277	1			T3	5		T8	298		T7	3
valid_sources[0x75]	216557	1			T3	1		T8	432		T6	1
valid_sources[0x76]	624886	1			T3	2		T8	363		T6	1
valid_sources[0x77]	367043	1			T2	1		T3	4		T8	306
valid_sources[0x78]	198380	1			T2	1		T3	2		T8	348
valid_sources[0x79]	263356	1			T3	3		T8	288		T6	6
valid_sources[0x7a]	235766	1			T2	1		T3	5		T8	331
valid_sources[0x7b]	224199	1			T2	2		T3	4		T8	309
valid_sources[0x7c]	224958	1			T3	5		T8	361		T6	2
valid_sources[0x7d]	199370	1			T3	4		T8	364		T6	2
valid_sources[0x7e]	239960	1			T3	3		T8	354		T6	3
valid_sources[0x7f]	793926	1			T2	5		T3	3		T8	377
valid_sources[0x80]	264648	1			T2	3		T3	1		T8	323

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13655874

1

T1

8

T2

3

T3

163

values[0x0]

all_enables

biggest_size

1814586

1

T1

4

T2

32

T3

41

values[0x1]

all_enables

biggest_size

993901

1

T2

12

T3

34

T8

406