Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	525440842	8479	0	0
ctrl_rd_A	525440842	1743	0	0
fifo_ctrl_rd_A	525440842	3877	0	0
host_timeout_ctrl_rd_A	525440842	1251	0	0
intr_enable_rd_A	525440842	4111	0	0
ovrd_rd_A	525440842	2416	0	0
target_id_rd_A	525440842	2052	0	0
timeout_ctrl_rd_A	525440842	1593	0	0
timing0_rd_A	525440842	1511	0	0
timing1_rd_A	525440842	1667	0	0
timing2_rd_A	525440842	1646	0	0
timing3_rd_A	525440842	1521	0	0
timing4_rd_A	525440842	1551	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	8479	0	0
T64	7982	1	0	0
T65	7413	212	0	0
T66	5328	5	0	0
T67	8159	355	0	0
T68	3388	253	0	0
T69	6202	2	0	0
T73	2722	315	0	0
T85	5617	3	0	0
T88	5806	1	0	0
T102	2677	23	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1743	0	0
T65	7413	6	0	0
T67	8159	21	0	0
T69	6202	78	0	0
T79	9538	10	0	0
T89	6278	10	0	0
T102	2677	6	0	0
T110	18523	117	0	0
T126	4759	60	0	0
T127	19068	114	0	0
T128	2254	14	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	3877	0	0
T4	1541	0	0	0
T20	692629	0	0	0
T42	158249	0	0	0
T52	4077	0	0	0
T129	421594	92	0	0
T130	0	106	0	0
T131	0	55	0	0
T132	0	117	0	0
T133	0	91	0	0
T134	0	70	0	0
T135	0	53	0	0
T136	0	89	0	0
T137	0	45	0	0
T138	0	92	0	0
T139	166965	0	0	0
T140	117643	0	0	0
T141	246627	0	0	0
T142	10340	0	0	0
T143	663365	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1251	0	0
T65	7413	1	0	0
T67	8159	2	0	0
T69	6202	33	0	0
T79	9538	22	0	0
T89	6278	10	0	0
T102	2677	5	0	0
T109	1263	2	0	0
T110	18523	160	0	0
T126	4759	30	0	0
T127	19068	130	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	4111	0	0
T22	306813	27	0	0
T65	0	12	0	0
T67	0	11	0	0
T69	0	338	0	0
T109	0	44	0	0
T127	0	127	0	0
T137	0	8	0	0
T144	0	32	0	0
T145	0	7	0	0
T146	0	14	0	0
T147	145462	0	0	0
T148	218691	0	0	0
T149	969658	0	0	0
T150	990649	0	0	0
T151	7821	0	0	0
T152	19119	0	0	0
T153	257761	0	0	0
T154	139441	0	0	0
T155	189694	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	2416	0	0
T76	1572	0	0	0
T156	1291	41	0	0
T157	0	36	0	0
T158	0	55	0	0
T159	0	67	0	0
T160	0	29	0	0
T161	0	36	0	0
T162	0	48	0	0
T163	0	69	0	0
T164	0	51	0	0
T165	0	23	0	0
T166	82660	0	0	0
T167	10733	0	0	0
T168	299253	0	0	0
T169	539868	0	0	0
T170	720696	0	0	0
T171	115386	0	0	0
T172	56293	0	0	0
T173	186123	0	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	2052	0	0
T65	7413	26	0	0
T67	8159	15	0	0
T69	6202	77	0	0
T79	9538	47	0	0
T89	6278	5	0	0
T102	2677	2	0	0
T109	1263	10	0	0
T110	18523	117	0	0
T126	4759	34	0	0
T127	19068	140	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1593	0	0
T65	7413	27	0	0
T67	8159	13	0	0
T69	6202	63	0	0
T79	9538	2	0	0
T89	6278	10	0	0
T102	2677	6	0	0
T109	1263	3	0	0
T110	18523	123	0	0
T126	4759	33	0	0
T127	19068	111	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1511	0	0
T65	7413	23	0	0
T67	8159	11	0	0
T69	6202	74	0	0
T79	9538	22	0	0
T102	2677	6	0	0
T110	18523	128	0	0
T126	4759	24	0	0
T127	19068	124	0	0
T128	2254	11	0	0
T174	10150	77	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1667	0	0
T65	7413	30	0	0
T67	8159	6	0	0
T69	6202	74	0	0
T79	9538	14	0	0
T89	6278	11	0	0
T102	2677	9	0	0
T110	18523	147	0	0
T126	4759	56	0	0
T127	19068	177	0	0
T128	2254	13	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1646	0	0
T65	7413	19	0	0
T67	8159	4	0	0
T69	6202	65	0	0
T79	9538	2	0	0
T89	6278	7	0	0
T102	2677	7	0	0
T109	1263	5	0	0
T110	18523	147	0	0
T126	4759	42	0	0
T127	19068	162	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1521	0	0
T65	7413	15	0	0
T67	8159	6	0	0
T69	6202	65	0	0
T79	9538	6	0	0
T89	6278	27	0	0
T102	2677	4	0	0
T110	18523	106	0	0
T126	4759	42	0	0
T127	19068	181	0	0
T128	2254	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525440842	1551	0	0
T65	7413	4	0	0
T67	8159	22	0	0
T69	6202	84	0	0
T79	9538	22	0	0
T102	2677	19	0	0
T110	18523	141	0	0
T126	4759	32	0	0
T127	19068	135	0	0
T128	2254	6	0	0
T174	10150	64	0	0