Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.17	96.63	73.13			90.91	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	90.17	96.63	73.13			90.91	100.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.17	96.63	73.13			90.91	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.70	98.84	89.74		93.04	96.88	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	97.22	100.00	88.89			100.00	100.00
intr_hw_acq_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_cmd_complete	100.00	100.00	100.00			100.00	100.00
intr_hw_fmt_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_host_timeout	97.92	100.00	91.67			100.00	100.00
intr_hw_nak	97.92	100.00	91.67			100.00	100.00
intr_hw_rx_overflow	93.75	100.00	75.00			100.00	100.00
intr_hw_rx_threshold	97.22	100.00	88.89			100.00	100.00
intr_hw_scl_interference	95.83	100.00	83.33			100.00	100.00
intr_hw_sda_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_unstable	100.00	100.00	100.00			100.00	100.00
intr_hw_stretch_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_stretch	91.67	100.00	66.67			100.00	100.00
intr_hw_tx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_unexp_stop	100.00	100.00	100.00			100.00	100.00
u_i2c_acqfifo	97.12	100.00	88.46			100.00	100.00
u_i2c_fmtfifo	96.15	100.00	84.62			100.00	100.00
u_i2c_fsm	96.39	98.56	94.63		93.04	95.74	100.00
u_i2c_rxfifo	96.15	100.00	84.62			100.00	100.00
u_i2c_sync_scl	100.00	100.00				100.00
u_i2c_sync_sda	100.00	100.00				100.00
u_i2c_txfifo	95.19	100.00	80.77			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		89	86	96.63
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	203	5	5	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	276	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	354	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
183	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
194	1	1
196	1	1
197	1	1
198	1	1
199	1	1
203	1	1
204	1	1
205	1	1
207	1	1
208	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
227	1	1
228	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
237	1	1
239	1	1
241	1	1
243	1	1
245	1	1
250	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	0	1
276	0	1
277	0	1
278	1	1
279	1	1
300	1	1
324	1	1
326	1	1
329	1	1
330	1	1
354	1	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	67	49	73.13
Logical	67	49	73.13
Non-Logical	0	0
Event	0	0

 LINE       185
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       186
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       194
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Not Covered

 LINE       226
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       227
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       232
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T11,T15
1	1	Covered	T14,T16,T17

 LINE       250
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Covered	T1,T14,T11

 LINE       263
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T11

 LINE       264
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T11

 LINE       265
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T11

 LINE       266
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T11

 LINE       267
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T11

 LINE       268
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T11

 LINE       326
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       326
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       329
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       329
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       354
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T7

 LINE       354
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T7

 LINE       354
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       354
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T18
1	0	Covered	T1,T2,T3

 LINE       354
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		22	20	90.91
TERNARY	185	2	2	100.00
TERNARY	186	2	2	100.00
TERNARY	263	2	2	100.00
TERNARY	264	2	2	100.00
TERNARY	265	2	2	100.00
TERNARY	266	2	2	100.00
TERNARY	267	2	2	100.00
TERNARY	268	2	2	100.00
TERNARY	329	2	1	50.00
TERNARY	330	2	1	50.00
IF	203	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	264	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FifoDepthValid_A	1289	1289	0	0

FifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0