Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	100.00	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.40	98.70	95.33	100.00	93.04	97.32	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	95.70	98.84	89.74		93.04	96.88	100.00
i2c_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	99.02	98.57	98.89	100.00		97.64	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
67	1	1
126	1	1
127	1	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       67
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T81,T82,T83

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	45	45	100.00
Total Bits	370	370	100.00
Total Bits 0->1	185	185	100.00
Total Bits 1->0	185	185	100.00

Ports	45	45	100.00
Port Bits	370	370	100.00
Port Bits 0->1	185	185	100.00
Port Bits 1->0	185	185	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T19,T11	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T14	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T4,T23	Yes	T14,T4,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T73,T81	Yes	T72,T73,T81	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T73,T81	Yes	T72,T73,T81	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T1,T19,T11	Yes	T1,T2,T3	OUTPUT
intr_rx_threshold_o	Yes	Yes	T14,T11,T15	Yes	T14,T11,T15	OUTPUT
intr_acq_threshold_o	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
intr_nak_o	Yes	Yes	T34,T57,T36	Yes	T34,T57,T36	OUTPUT
intr_scl_interference_o	Yes	Yes	T57,T59,T60	Yes	T57,T59,T60	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T14,T11	Yes	T1,T14,T11	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T1,T14,T11	Yes	T1,T14,T11	OUTPUT
intr_sda_unstable_o	Yes	Yes	T1,T14,T11	Yes	T1,T14,T11	OUTPUT
intr_cmd_complete_o	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
intr_tx_stretch_o	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
intr_tx_threshold_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_acq_full_o	Yes	Yes	T3,T19,T96	Yes	T3,T19,T96	OUTPUT
intr_unexp_stop_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
intr_host_timeout_o	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	483555163	483396952	0	0
CioSclEnKnownO_A	483555163	483396952	0	0
CioSclKnownO_A	483555163	483396952	0	0
CioSdaEnKnownO_A	483555163	483396952	0	0
CioSdaKnownO_A	483555163	483396952	0	0
FpvSecCmRegWeOnehotCheck_A	483555163	70	0	0
IntrAcqFulllwKnownO_A	483555163	483396952	0	0
IntrAcqWtmkKnownO_A	483555163	483396952	0	0
IntrCommandCompleteKnownO_A	483555163	483396952	0	0
IntrFmtWtmkKnownO_A	483555163	483396952	0	0
IntrHostTimeoutKnownO_A	483555163	483396952	0	0
IntrNakKnownO_A	483555163	483396952	0	0
IntrRxOflwKnownO_A	483555163	483396952	0	0
IntrRxWtmkKnownO_A	483555163	483396952	0	0
IntrSclInterfKnownO_A	483555163	483396952	0	0
IntrSdaInterfKnownO_A	483555163	483396952	0	0
IntrSdaUnstableKnownO_A	483555163	483396952	0	0
IntrStretchTimeoutKnownO_A	483555163	483396952	0	0
IntrTxStretchKnownO_A	483555163	483396952	0	0
IntrTxWtmkKnownO_A	483555163	483396952	0	0
IntrUnexpStopKnownO_A	483555163	483396952	0	0
TlAReadyKnownO_A	483555163	483396952	0	0
TlDValidKnownO_A	483555163	483396952	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	70	0	0
T5	1188	0	0	0
T17	254559	0	0	0
T25	160617	0	0	0
T43	392998	0	0	0
T51	62202	0	0	0
T61	383654	0	0	0
T66	43036	0	0	0
T72	3682	10	0	0
T73	0	10	0	0
T74	0	20	0	0
T97	0	10	0	0
T98	0	20	0	0
T99	74675	0	0	0
T100	111769	0	0	0

IntrAcqFulllwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrAcqWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrNakKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrTxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483555163	483396952	0	0
T1	3216	2554	0	0
T2	66191	66113	0	0
T3	149263	149187	0	0
T7	123892	123796	0	0
T8	255381	255330	0	0
T11	170108	169978	0	0
T14	232678	232610	0	0
T15	981773	981679	0	0
T19	138632	138608	0	0
T20	332394	332339	0	0