Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	484140951	10706	0	0
ctrl_rd_A	484140951	1556	0	0
host_fifo_config_rd_A	484140951	3331	0	0
host_timeout_ctrl_rd_A	484140951	1328	0	0
intr_enable_rd_A	484140951	3015	0	0
ovrd_rd_A	484140951	1940	0	0
target_fifo_config_rd_A	484140951	1325	0	0
target_id_rd_A	484140951	1470	0	0
timeout_ctrl_rd_A	484140951	1322	0	0
timing0_rd_A	484140951	1351	0	0
timing1_rd_A	484140951	1345	0	0
timing2_rd_A	484140951	1406	0	0
timing3_rd_A	484140951	1403	0	0
timing4_rd_A	484140951	1421	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	10706	0	0
T67	9858	670	0	0
T68	11164	5	0	0
T69	7916	7	0	0
T70	10427	531	0	0
T71	3041	170	0	0
T75	3978	6	0	0
T91	6242	3	0	0
T93	10920	4	0	0
T101	2690	23	0	0
T102	4161	30	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1556	0	0
T68	11164	98	0	0
T78	5375	15	0	0
T91	6242	70	0	0
T102	4161	31	0	0
T111	4913	80	0	0
T112	1261	1	0	0
T124	2240	20	0	0
T125	6069	62	0	0
T126	12050	25	0	0
T127	1500	15	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	3331	0	0
T9	18155	0	0	0
T13	202800	0	0	0
T34	0	121	0	0
T52	169934	185	0	0
T128	0	149	0	0
T129	0	187	0	0
T130	0	198	0	0
T131	0	151	0	0
T132	0	120	0	0
T133	0	108	0	0
T134	0	171	0	0
T135	0	92	0	0
T136	144616	0	0	0
T137	69531	0	0	0
T138	161807	0	0	0
T139	82459	0	0	0
T140	59799	0	0	0
T141	172680	0	0	0
T142	231699	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1328	0	0
T68	11164	56	0	0
T78	5375	15	0	0
T91	6242	62	0	0
T102	4161	19	0	0
T111	4913	102	0	0
T112	1261	6	0	0
T124	2240	12	0	0
T125	6069	30	0	0
T126	12050	7	0	0
T127	1500	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	3015	0	0
T68	11164	226	0	0
T78	5375	9	0	0
T91	6242	240	0	0
T102	4161	135	0	0
T111	4913	64	0	0
T112	1261	7	0	0
T124	2240	68	0	0
T125	6069	5	0	0
T126	12050	17	0	0
T127	1500	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1940	0	0
T6	1127	38	0	0
T143	0	54	0	0
T144	0	47	0	0
T145	0	25	0	0
T146	0	18	0	0
T147	0	43	0	0
T148	0	55	0	0
T149	0	72	0	0
T150	0	64	0	0
T151	0	48	0	0
T152	34453	0	0	0
T153	71854	0	0	0
T154	561640	0	0	0
T155	357157	0	0	0
T156	123320	0	0	0
T157	152171	0	0	0
T158	75386	0	0	0
T159	932400	0	0	0
T160	188201	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1325	0	0
T68	11164	45	0	0
T78	5375	27	0	0
T91	6242	66	0	0
T102	4161	24	0	0
T111	4913	88	0	0
T112	1261	4	0	0
T124	2240	3	0	0
T125	6069	31	0	0
T126	12050	34	0	0
T127	1500	7	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1470	0	0
T68	11164	73	0	0
T91	6242	82	0	0
T92	7492	69	0	0
T102	4161	21	0	0
T111	4913	59	0	0
T112	1261	1	0	0
T124	2240	2	0	0
T125	6069	86	0	0
T127	1500	19	0	0
T161	20802	161	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1322	0	0
T68	11164	73	0	0
T78	5375	8	0	0
T91	6242	62	0	0
T102	4161	14	0	0
T111	4913	68	0	0
T112	1261	1	0	0
T124	2240	1	0	0
T125	6069	59	0	0
T126	12050	20	0	0
T127	1500	5	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1351	0	0
T68	11164	44	0	0
T78	5375	4	0	0
T91	6242	52	0	0
T102	4161	25	0	0
T111	4913	77	0	0
T112	1261	2	0	0
T124	2240	10	0	0
T125	6069	60	0	0
T126	12050	28	0	0
T127	1500	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1345	0	0
T68	11164	47	0	0
T78	5375	25	0	0
T91	6242	52	0	0
T102	4161	5	0	0
T111	4913	55	0	0
T112	1261	4	0	0
T124	2240	6	0	0
T125	6069	61	0	0
T126	12050	2	0	0
T127	1500	1	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1406	0	0
T68	11164	74	0	0
T78	5375	9	0	0
T91	6242	69	0	0
T102	4161	20	0	0
T111	4913	74	0	0
T112	1261	7	0	0
T124	2240	7	0	0
T125	6069	34	0	0
T126	12050	22	0	0
T127	1500	12	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1403	0	0
T68	11164	77	0	0
T78	5375	11	0	0
T91	6242	64	0	0
T92	7492	51	0	0
T102	4161	19	0	0
T111	4913	94	0	0
T112	1261	7	0	0
T125	6069	26	0	0
T126	12050	25	0	0
T127	1500	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484140951	1421	0	0
T68	11164	18	0	0
T78	5375	9	0	0
T91	6242	61	0	0
T92	7492	73	0	0
T102	4161	29	0	0
T111	4913	91	0	0
T112	1261	5	0	0
T124	2240	1	0	0
T125	6069	66	0	0
T127	1500	4	0	0