Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

143166

1

T16

196

T11

717

T36

118

ack

16719

1

T3

28

T16

16

T11

144

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	613	1			T16	1		T11	1		T14	1
high	32299	1			T3	1		T16	61		T11	146
med	58165	1			T3	4		T16	80		T11	294
sml	68226	1			T3	23		T16	70		T11	418
all_zero	582	1			T11	2		T12	1		T63	3

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79432

1

T3

14

T16

102

T11

441

auto[1]

80453

1

T3

14

T16

110

T11

420

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110243

1

T3

14

T16

149

T11

581

auto[1]

49642

1

T3

14

T16

63

T11

280

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149826

1

T3

8

T16

212

T11

751

auto[1]

10059

1

T3

20

T11

110

T12

9

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147985

1

T3

20

T16

196

T11

735

auto[1]

11900

1

T3

8

T16

16

T11

126

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149605

1

T3

22

T16

196

T11

765

auto[1]

10280

1

T3

6

T16

16

T11

96

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79432

1

T3

14

T16

102

T11

441

auto[1]

80453

1

T3

14

T16

110

T11

420

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110243

1

T3

14

T16

149

T11

581

auto[1]

49642

1

T3

14

T16

63

T11

280

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149826

1

T3

8

T16

212

T11

751

auto[1]

10059

1

T3

20

T11

110

T12

9

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147985

1

T3

20

T16

196

T11

735

auto[1]

11900

1

T3

8

T16

16

T11

126

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149605

1

T3

22

T16

196

T11

765

auto[1]

10280

1

T3

6

T16

16

T11

96

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

16

1

T206

1

T207

1

T208

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T209

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T210

1

T211

1

T212

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

454

1

T11

4

T12

1

T213

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

229

1

T11

6

T213

3

T214

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

238

1

T11

4

T214

3

T215

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

841

1

T11

13

T63

4

T15

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

403

1

T11

9

T14

1

T63

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

378

1

T11

6

T14

2

T63

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

795

1

T11

8

T12

1

T14

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

399

1

T11

10

T14

1

T63

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

408

1

T11

6

T12

1

T14

3

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

12

1

T206

1

T92

1

T144

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T216

1

T184

1

T217

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T214

1

T215

1

T218

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	44354	1			T16	58		T11	187		T36	37
write_address_byte	11900	1			T3	8		T16	16		T11	126
read_with_ack	3732	1			T3	14		T11	48		T14	17
read_with_nack	6327	1			T3	6		T11	62		T12	9
stop_byte	10280	1			T3	6		T16	16		T11	96
write_address_byte_nak	6915	1			T11	101		T12	11		T14	17
data_byte_nack	143166	1			T16	196		T11	717		T36	118
stop_byte_nack	6721	1			T16	16		T11	82		T36	15
nakok_byte_nack	72026	1			T16	103		T11	355		T36	58
nakok_addr_byte_nack	3480	1			T11	47		T12	8		T14	7