Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

163405

1

T2

704

T3

1280

T16

112

ack

18719

1

T2

135

T3

40

T16

13

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	685	1			T2	5		T3	5		T16	1
high	37190	1			T2	189		T3	287		T16	33
med	66007	1			T2	266		T3	517		T16	46
sml	77547	1			T2	377		T3	504		T16	45
all_zero	695	1			T2	2		T3	7		T12	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90358

1

T2

404

T3

657

T16

61

auto[1]

91766

1

T2

435

T3

663

T16

64

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125331

1

T2

589

T3

892

T16

84

auto[1]

56793

1

T2

250

T3

428

T16

41

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170897

1

T2

754

T3

1301

T16

125

auto[1]

11227

1

T2

85

T3

19

T12

87

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168710

1

T2

780

T3

1281

T16

112

auto[1]

13414

1

T2

59

T3

39

T16

13

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170461

1

T2

784

T3

1282

T16

112

auto[1]

11663

1

T2

55

T3

38

T16

13

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90358

1

T2

404

T3

657

T16

61

auto[1]

91766

1

T2

435

T3

663

T16

64

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125331

1

T2

589

T3

892

T16

84

auto[1]

56793

1

T2

250

T3

428

T16

41

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170897

1

T2

754

T3

1301

T16

125

auto[1]

11227

1

T2

85

T3

19

T12

87

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168710

1

T2

780

T3

1281

T16

112

auto[1]

13414

1

T2

59

T3

39

T16

13

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170461

1

T2

784

T3

1282

T16

112

auto[1]

11663

1

T2

55

T3

38

T16

13

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

9

1

T210

1

T211

1

T212

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T178

1

T211

1

T213

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T214

1

T215

1

T216

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

464

1

T2

2

T3

2

T12

7

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

241

1

T12

1

T21

1

T24

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

249

1

T12

3

T24

2

T110

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

915

1

T2

2

T3

2

T12

12

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

432

1

T2

2

T3

1

T12

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

463

1

T3

2

T12

4

T21

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

899

1

T2

4

T3

3

T12

6

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

438

1

T2

2

T3

6

T12

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

436

1

T3

2

T12

5

T64

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

13

1

T217

1

T182

1

T218

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

7

1

T12

1

T219

1

T199

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T220

1

T141

1

T221

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50473	1			T2	235		T3	405		T16	33
write_address_byte	13414	1			T2	59		T3	39		T16	13
read_with_ack	3963	1			T2	40		T12	46		T21	1
read_with_nack	7264	1			T2	45		T3	19		T12	41
stop_byte	11663	1			T2	55		T3	38		T16	13
write_address_byte_nak	7768	1			T2	18		T3	36		T12	66
data_byte_nack	163405	1			T2	704		T3	1280		T16	112
stop_byte_nack	7506	1			T2	17		T3	35		T16	13
nakok_byte_nack	82272	1			T2	360		T3	649		T16	57
nakok_addr_byte_nack	3927	1			T2	10		T3	18		T12	34