Unified Coverage Report :: Module :: i2c_fsm

Module : i2c_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.55	98.56	94.21		74.65	95.35	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_fsm	96.06	98.56	94.21		92.17	95.35	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.06	98.56	94.21		92.17	95.35	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.06	98.56	94.21		92.17	95.35	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		554	546	98.56
ALWAYS	155	17	17	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	182	3	3	100.00
ALWAYS	195	9	9	100.00
ALWAYS	211	7	7	100.00
ALWAYS	224	6	6	100.00
ALWAYS	235	5	5	100.00
ALWAYS	242	7	7	100.00
ALWAYS	255	5	5	100.00
ALWAYS	269	8	8	100.00
ALWAYS	281	8	7	87.50
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	303	9	9	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	7	7	100.00
ALWAYS	335	5	5	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
ALWAYS	412	6	6	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	435	4	4	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
ALWAYS	460	180	174	96.67
CONT_ASSIGN	806	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	820	1	1	100.00
ALWAYS	824	239	238	99.58
ALWAYS	1324	3	3	100.00
ALWAYS	1333	5	5	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
171	1	1
172	1	1
174	1	1
179	1	1
182	1	1
183	1	1
185	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
201	1	1
202	1	1
203	1	1
205	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
235	2	2
236	2	2
237	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
249	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	0	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
293	1	1
296	1	1
299	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
310	2	2
311	1	1
313	1	1
318	1	1
319	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	2	2
			MISSING_ELSE
			MISSING_ELSE
335	1	1
336	1	1
337	1	1
338	2	2
			MISSING_ELSE
			MISSING_ELSE
348	1	1
349	1	1
407	1	1
412	1	1
413	1	1
414	1	1
418	1	1
419	1	1
420	1	1
			MISSING_ELSE
430	1	1
435	1	1
436	1	1
437	1	1
438	1	1
			MISSING_ELSE
452	1	1
456	1	1
460	1	1
461	1	1
462	1	1
463	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
482	1	1
483	1	1
484	0	1
485	0	1
487	1	1
488	1	1
493	1	1
494	1	1
495	1	1
496	2	2
			MISSING_ELSE
500	1	1
501	1	1
502	1	1
506	1	1
507	1	1
508	1	1
511	1	1
512	1	1
513	1	1
515	1	1
517	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	2
			MISSING_ELSE
526	2	2
			MISSING_ELSE
530	1	1
531	1	1
532	1	1
536	1	1
537	1	1
538	1	1
542	1	1
543	1	1
544	1	1
545	2	2
			MISSING_ELSE
546	1	1
547	1	2
			MISSING_ELSE
548	2	2
			MISSING_ELSE
552	1	1
553	1	1
554	1	1
558	1	1
559	1	1
560	1	1
564	1	1
565	1	1
566	1	1
567	1	2
			MISSING_ELSE
568	2	2
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
575	1	1
576	1	1
			MISSING_ELSE
581	1	1
582	1	1
586	2	2
587	2	2
588	1	1
592	1	1
593	2	2
594	2	2
595	1	1
596	1	1
597	1	1
598	1	2
			MISSING_ELSE
599	2	2
			MISSING_ELSE
603	1	1
604	2	2
605	2	2
606	1	1
607	1	1
611	1	1
612	1	1
613	1	1
617	1	1
618	1	1
619	1	1
623	1	1
624	1	1
625	1	1
626	1	1
630	1	1
636	1	1
640	1	1
641	2	2
642	1	1
643	1	1
647	1	1
651	1	1
652	1	1
656	1	1
660	1	1
661	1	1
665	1	1
666	1	1
670	1	1
671	1	1
674	1	1
676	1	1
677	1	1
			MISSING_ELSE
682	1	1
686	1	1
687	1	1
691	1	1
694	1	1
698	1	1
701	1	1
705	1	1
708	1	1
709	1	1
711	1	1
			MISSING_ELSE
716	1	1
717	1	1
718	1	1
722	1	1
726	1	1
730	1	1
731	1	1
735	1	1
736	1	1
740	1	1
741	1	1
743	1	1
744	1	1
745	1	1
			MISSING_ELSE
751	1	1
752	1	1
754	1	1
755	1	1
759	1	1
760	1	1
764	1	1
765	1	1
766	1	1
770	1	1
771	1	1
774	1	1
775	1	1
797	1	1
799	1	1
800	1	1
802	1	1
			MISSING_ELSE
806	1	1
815	1	1
820	1	1
824	1	1
825	1	1
826	1	1
827	1	1
828	1	1
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
834	1	1
835	1	1
836	1	1
837	1	1
838	1	1
840	1	1
843	2	2
844	1	1
845	2	2
			MISSING_ELSE
			MISSING_ELSE
851	1	1
852	1	1
853	1	1
854	1	1
855	1	1
			MISSING_ELSE
860	1	1
861	1	1
862	1	1
863	1	1
			MISSING_ELSE
868	1	1
869	1	1
870	1	1
871	1	1
			MISSING_ELSE
876	1	1
877	1	1
878	1	1
879	1	1
880	1	1
881	1	1
883	1	1
884	1	1
			MISSING_ELSE
891	1	1
892	1	1
893	1	1
894	1	1
895	1	1
			MISSING_ELSE
900	1	1
901	1	1
902	1	1
903	1	1
904	1	1
905	1	1
906	1	1
907	1	1
909	1	1
910	1	1
			MISSING_ELSE
917	1	1
918	1	1
919	1	1
920	1	1
			MISSING_ELSE
925	1	1
926	1	1
927	1	1
928	1	1
			MISSING_ELSE
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
939	1	1
940	1	1
941	1	1
			MISSING_ELSE
947	1	1
948	1	1
949	1	1
950	1	1
			MISSING_ELSE
955	1	1
956	1	1
957	1	1
958	1	1
959	1	1
			MISSING_ELSE
964	1	1
965	1	1
966	1	1
967	1	1
968	1	1
969	1	1
970	1	1
972	1	1
973	1	1
			MISSING_ELSE
980	1	1
981	1	1
982	1	1
983	1	1
984	1	1
			MISSING_ELSE
989	1	1
990	1	1
991	1	1
992	1	1
993	1	1
			MISSING_ELSE
998	1	1
999	1	1
1000	1	1
1001	1	1
1002	1	1
1003	1	1
1004	1	1
1005	1	1
1007	1	1
1008	1	1
1009	1	1
1012	1	1
1013	1	1
1014	1	1
1015	1	1
			MISSING_ELSE
1022	1	1
1023	1	1
1024	1	1
1025	1	1
			MISSING_ELSE
1030	1	1
1031	1	1
1032	1	1
1033	1	1
1034	1	1
			MISSING_ELSE
1039	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1044	1	1
1045	1	1
1047	1	1
1048	1	1
1049	1	1
			MISSING_ELSE
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1063	1	1
1064	1	1
1066	1	1
1067	1	1
1068	1	1
1069	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1084	1	1
1085	1	1
1086	1	1
1092	1	1
1094	1	1
1095	1	1
			MISSING_ELSE
1101	1	1
1102	1	1
1103	1	1
1104	1	1
1105	1	1
1106	1	1
			MISSING_ELSE
1112	1	1
1113	1	1
			MISSING_ELSE
1118	2	2
			MISSING_ELSE
1122	1	1
1123	1	1
1124	1	1
1125	1	1
			MISSING_ELSE
1130	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
1138	1	1
1139	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1145	1	1
1146	1	1
1148	1	1
1149	1	1
1150	1	1
1155	2	2
			MISSING_ELSE
1159	1	1
1160	1	1
1161	1	1
1162	1	1
			MISSING_ELSE
1167	1	1
1168	1	1
1169	1	1
1171	1	1
1172	1	1
1173	1	1
			MISSING_ELSE
1180	1	1
1181	1	1
			MISSING_ELSE
1188	1	1
1190	1	1
1191	1	1
1194	1	1
			MISSING_ELSE
1203	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
			MISSING_ELSE
1217	1	1
1218	1	1
			MISSING_ELSE
1223	2	2
			MISSING_ELSE
1227	1	1
1228	1	1
1229	1	1
1230	1	1
			MISSING_ELSE
1235	1	1
1238	1	1
			MISSING_ELSE
1244	1	1
1250	1	1
			MISSING_ELSE
1256	1	1
1257	1	1
1264	1	1
1265	1	1
1266	1	1
1269	1	1
			MISSING_ELSE
1273	1	1
1274	1	1
			MISSING_ELSE
1281	2	2
			MISSING_ELSE
1305	1	1
1314	0	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
			MISSING_ELSE
1324	1	1
1325	1	1
1327	1	1
1333	1	1
1334	1	1
1335	1	1
1337	1	1
1338	1	1
1342	1	1
1343	1	1
1346	1	1
1349	1	1
1353	1	1

---

Cond Coverage for Module : i2c_fsm

	Total	Covered	Percent
Conditions	242	228	94.21
Logical	242	228	94.21
Non-Logical	0	0
Event	0	0

 LINE       171
 EXPRESSION ((stretch_idle_cnt == '0) || target_enable_i)
             ------------1-----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T16
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3

 LINE       171
 SUB-EXPRESSION (stretch_idle_cnt == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION (stretch_en && scl_d && ((!scl_i)))
             -----1----    --2--    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

 LINE       199
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T22,T23

 LINE       202
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       236
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T24,T25,T26

 LINE       271
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T11,T27,T28

 LINE       283
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T21,T24
1	1	Not Covered

 LINE       293
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       293
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       296
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       299
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       310
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8

 LINE       318
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       319
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       320
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       328
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       419
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       430
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T16

 LINE       430
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T16
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

 LINE       430
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T16
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

 LINE       430
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       437
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       456
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T29,T30,T31
1	0	1	1	Covered	T1,T7,T8
1	1	0	1	Covered	T1,T7,T8
1	1	1	0	Covered	T1,T7,T8
1	1	1	1	Covered	T1,T32,T33

 LINE       483
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Not Covered

 LINE       525
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T16
1	1	Not Covered

 LINE       526
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       545
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T24,T34,T35
1	0	1	1	Covered	T2,T3,T16
1	1	0	1	Covered	T2,T3,T16
1	1	1	0	Covered	T36,T37,T38
1	1	1	1	Covered	T24,T39,T34

 LINE       547
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T16
1	1	Not Covered

 LINE       548
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       567
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Not Covered

 LINE       568
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       574
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T3,T12

 LINE       574
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       574
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       587
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       594
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       598
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Not Covered

 LINE       599
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       605
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       636
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T9,T40,T41
1	0	Covered	T12,T21,T24
1	1	Covered	T2,T3,T16

 LINE       674
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       743
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       797
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       800
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       815
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3

 LINE       843
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       851
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       860
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       868
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       877
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       892
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       901
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       905
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       917
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       925
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       933
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       947
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       955
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       964
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       967
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       981
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       990
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       999
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       1001
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       1022
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1030
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1040
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1061
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T9,T40,T41
1	0	Covered	T12,T21,T24
1	1	Covered	T2,T3,T16

 LINE       1079
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1092
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T42
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       1101
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T29,T43,T30
1	1	Covered	T1,T7,T8

 LINE       1105
 EXPRESSION (bit_ack && ((!address_match)))
             ---1---    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Not Covered
1	1	Covered	T29,T43,T30

 LINE       1112
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       1112
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1130
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1167
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1217
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       1217
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1235
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1238
 EXPRESSION (acq_fifo_wready ? AcquireByte : StretchAcqFull)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T44,T45
1	Covered	T1,T7,T8

 LINE       1250
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T1,T44,T45
1	Not Covered

 LINE       1273
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1305
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Not Covered

 LINE       1346
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T22,T23

 LINE       1349
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T46
1	0	1	Covered	T2,T3,T16
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

---

FSM Coverage for Module : i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	43	43	100.00	(Not included in score)
Transitions	142	106	74.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1228	Covered	T1,T7,T8
AcquireAckPulse	1223	Covered	T1,T7,T8
AcquireAckSetup	1218	Covered	T1,T7,T8
AcquireAckWait	1209	Covered	T1,T7,T8
AcquireByte	1139	Covered	T1,T7,T8
AcquireStart	1316	Covered	T1,T7,T8
Active	845	Covered	T2,T3,T16
AddrAckHold	1123	Covered	T1,T7,T8
AddrAckPulse	1118	Covered	T1,T7,T8
AddrAckSetup	1113	Covered	T1,T7,T8
AddrAckWait	1102	Covered	T1,T7,T8
AddrRead	1094	Covered	T1,T7,T8
ClockLow	869	Covered	T2,T3,T16
ClockLowAck	906	Covered	T2,T3,T16
ClockPulse	883	Covered	T2,T3,T16
ClockPulseAck	918	Covered	T2,T3,T16
ClockStart	861	Covered	T2,T3,T16
ClockStop	935	Covered	T2,T3,T16
HoldBit	893	Covered	T2,T3,T16
HoldDevAck	926	Covered	T2,T3,T16
HoldStart	852	Covered	T2,T3,T16
HoldStop	1031	Covered	T2,T3,T16
HostClockLowAck	968	Covered	T2,T3,T12
HostClockPulseAck	982	Covered	T2,T3,T12
HostHoldBitAck	991	Covered	T2,T3,T12
Idle	843	Covered	T1,T2,T3
PopFmtFifo	939	Covered	T2,T3,T16
ReadClockLow	972	Covered	T2,T3,T12
ReadClockPulse	948	Covered	T2,T3,T12
ReadHoldBit	956	Covered	T2,T3,T12
SetupStart	880	Covered	T2,T3,T16
SetupStop	1023	Covered	T2,T3,T16
StretchAcqFull	1238	Covered	T1,T44,T45
StretchAddr	1135	Covered	T1,T44,T45
StretchTx	1146	Covered	T1,T7,T8
StretchTxSetup	1264	Covered	T1,T7,T8
TransmitAck	1169	Covered	T1,T7,T8
TransmitAckPulse	1181	Covered	T1,T7,T8
TransmitHold	1160	Covered	T1,T7,T8
TransmitPulse	1155	Covered	T1,T7,T8
TransmitSetup	1148	Covered	T1,T7,T8
TransmitWait	1137	Covered	T1,T7,T8
WaitForStop	1194	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1238	Covered	T1,T7,T8
AcquireAckHold->AcquireStart	1316	Covered	T31,T42
AcquireAckHold->Idle	1314	Covered	T31,T42
AcquireAckHold->StretchAcqFull	1238	Covered	T1,T44,T45
AcquireAckPulse->AcquireAckHold	1228	Covered	T1,T7,T8
AcquireAckPulse->AcquireStart	1316	Covered	T31,T42
AcquireAckPulse->Idle	1314	Covered	T31,T42
AcquireAckSetup->AcquireAckPulse	1223	Covered	T1,T7,T8
AcquireAckSetup->AcquireStart	1316	Covered	T31,T42
AcquireAckSetup->Idle	1314	Covered	T31,T42
AcquireAckWait->AcquireAckSetup	1218	Covered	T1,T7,T8
AcquireAckWait->AcquireStart	1316	Covered	T31,T42
AcquireAckWait->Idle	1314	Covered	T31,T42
AcquireByte->AcquireAckWait	1209	Covered	T1,T7,T8
AcquireByte->AcquireStart	1316	Covered	T1,T7,T8
AcquireByte->Idle	1314	Covered	T1,T7,T8
AcquireStart->AddrRead	1094	Covered	T1,T7,T8
AcquireStart->Idle	1314	Covered	T31,T42
Active->AcquireStart	1316	Not Covered
Active->ClockLow	1066	Covered	T2,T3,T16
Active->Idle	1314	Not Covered
Active->ReadClockLow	1058	Covered	T2,T3,T12
Active->SetupStart	1062	Covered	T2,T3,T16
AddrAckHold->AcquireByte	1139	Covered	T1,T7,T8
AddrAckHold->AcquireStart	1316	Covered	T31,T42
AddrAckHold->Idle	1314	Covered	T31,T42
AddrAckHold->StretchAddr	1135	Covered	T1,T44,T45
AddrAckHold->TransmitWait	1137	Covered	T1,T7,T8
AddrAckPulse->AcquireStart	1316	Covered	T31,T42
AddrAckPulse->AddrAckHold	1123	Covered	T1,T7,T8
AddrAckPulse->Idle	1314	Covered	T31,T42
AddrAckSetup->AcquireStart	1316	Covered	T31,T42
AddrAckSetup->AddrAckPulse	1118	Covered	T1,T7,T8
AddrAckSetup->Idle	1314	Covered	T31,T42
AddrAckWait->AcquireStart	1316	Covered	T31,T42
AddrAckWait->AddrAckSetup	1113	Covered	T1,T7,T8
AddrAckWait->Idle	1314	Covered	T31,T42
AddrRead->AcquireStart	1316	Covered	T47,T48,T49
AddrRead->AddrAckWait	1102	Covered	T1,T7,T8
AddrRead->Idle	1106	Covered	T29,T43,T50
ClockLow->AcquireStart	1316	Not Covered
ClockLow->ClockPulse	883	Covered	T2,T3,T16
ClockLow->Idle	1314	Covered	T19,T24,T51
ClockLow->SetupStart	880	Covered	T12,T21,T24
ClockLowAck->AcquireStart	1316	Not Covered
ClockLowAck->ClockPulseAck	918	Covered	T2,T3,T16
ClockLowAck->Idle	1314	Not Covered
ClockPulse->AcquireStart	1316	Not Covered
ClockPulse->HoldBit	893	Covered	T2,T3,T16
ClockPulse->Idle	1314	Covered	T19,T24,T51
ClockPulseAck->AcquireStart	1316	Not Covered
ClockPulseAck->HoldDevAck	926	Covered	T2,T3,T16
ClockPulseAck->Idle	1314	Covered	T19,T24,T51
ClockStart->AcquireStart	1316	Not Covered
ClockStart->ClockLow	869	Covered	T2,T3,T16
ClockStart->Idle	1314	Not Covered
ClockStop->AcquireStart	1316	Not Covered
ClockStop->Idle	1314	Not Covered
ClockStop->SetupStop	1023	Covered	T2,T3,T16
HoldBit->AcquireStart	1316	Not Covered
HoldBit->ClockLow	909	Covered	T2,T3,T16
HoldBit->ClockLowAck	906	Covered	T2,T3,T16
HoldBit->Idle	1314	Not Covered
HoldDevAck->AcquireStart	1316	Not Covered
HoldDevAck->ClockStop	935	Covered	T2,T3,T16
HoldDevAck->Idle	1314	Not Covered
HoldDevAck->PopFmtFifo	939	Covered	T2,T3,T16
HoldStart->AcquireStart	1316	Not Covered
HoldStart->ClockStart	861	Covered	T2,T3,T16
HoldStart->Idle	1314	Not Covered
HoldStop->AcquireStart	1316	Not Covered
HoldStop->Idle	1043	Covered	T11,T27,T15
HoldStop->PopFmtFifo	1047	Covered	T2,T3,T16
HostClockLowAck->AcquireStart	1316	Not Covered
HostClockLowAck->HostClockPulseAck	982	Covered	T2,T3,T12
HostClockLowAck->Idle	1314	Not Covered
HostClockPulseAck->AcquireStart	1316	Not Covered
HostClockPulseAck->HostHoldBitAck	991	Covered	T2,T3,T12
HostClockPulseAck->Idle	1314	Not Covered
HostHoldBitAck->AcquireStart	1316	Not Covered
HostHoldBitAck->ClockStop	1003	Covered	T2,T3,T12
HostHoldBitAck->Idle	1314	Not Covered
HostHoldBitAck->PopFmtFifo	1007	Covered	T2,T12,T21
HostHoldBitAck->ReadClockLow	1012	Covered	T2,T3,T12
Idle->AcquireStart	1316	Covered	T1,T7,T8
Idle->Active	845	Covered	T2,T3,T16
PopFmtFifo->AcquireStart	1316	Not Covered
PopFmtFifo->Active	1084	Covered	T2,T3,T16
PopFmtFifo->ClockStop	1076	Covered	T11,T27,T15
PopFmtFifo->Idle	1080	Covered	T2,T3,T16
ReadClockLow->AcquireStart	1316	Not Covered
ReadClockLow->Idle	1314	Not Covered
ReadClockLow->ReadClockPulse	948	Covered	T2,T3,T12
ReadClockPulse->AcquireStart	1316	Not Covered
ReadClockPulse->Idle	1314	Not Covered
ReadClockPulse->ReadHoldBit	956	Covered	T2,T3,T12
ReadHoldBit->AcquireStart	1316	Not Covered
ReadHoldBit->HostClockLowAck	968	Covered	T2,T3,T12
ReadHoldBit->Idle	1314	Not Covered
ReadHoldBit->ReadClockLow	972	Covered	T2,T3,T12
SetupStart->AcquireStart	1316	Not Covered
SetupStart->HoldStart	852	Covered	T2,T3,T16
SetupStart->Idle	1314	Not Covered
SetupStop->AcquireStart	1316	Not Covered
SetupStop->HoldStop	1031	Covered	T2,T3,T16
SetupStop->Idle	1314	Not Covered
StretchAcqFull->AcquireByte	1281	Covered	T1,T44,T45
StretchAcqFull->AcquireStart	1316	Covered	T31,T42
StretchAcqFull->Idle	1314	Covered	T31,T42
StretchAddr->AcquireByte	1250	Covered	T1,T44,T45
StretchAddr->AcquireStart	1316	Covered	T31,T42
StretchAddr->Idle	1314	Covered	T31,T42
StretchAddr->StretchTx	1250	Not Covered
StretchTx->AcquireStart	1316	Covered	T31,T42
StretchTx->Idle	1314	Covered	T31,T42
StretchTx->StretchTxSetup	1264	Covered	T1,T7,T8
StretchTxSetup->AcquireStart	1316	Covered	T31,T42
StretchTxSetup->Idle	1314	Covered	T31,T42
StretchTxSetup->TransmitSetup	1274	Covered	T1,T7,T8
TransmitAck->AcquireStart	1316	Covered	T31,T42
TransmitAck->Idle	1314	Covered	T31,T42
TransmitAck->TransmitAckPulse	1181	Covered	T1,T7,T8
TransmitAckPulse->AcquireStart	1316	Covered	T33,T52,T31
TransmitAckPulse->Idle	1314	Covered	T31,T42
TransmitAckPulse->TransmitWait	1191	Covered	T1,T7,T8
TransmitAckPulse->WaitForStop	1194	Covered	T1,T7,T8
TransmitHold->AcquireStart	1316	Covered	T31,T42
TransmitHold->Idle	1314	Covered	T31,T42
TransmitHold->TransmitAck	1169	Covered	T1,T7,T8
TransmitHold->TransmitSetup	1173	Covered	T1,T7,T8
TransmitPulse->AcquireStart	1316	Covered	T1,T32,T33
TransmitPulse->Idle	1314	Covered	T1,T32,T33
TransmitPulse->TransmitHold	1160	Covered	T1,T7,T8
TransmitSetup->AcquireStart	1316	Covered	T31,T42
TransmitSetup->Idle	1314	Covered	T31,T42
TransmitSetup->TransmitPulse	1155	Covered	T1,T7,T8
TransmitWait->AcquireStart	1316	Covered	T31,T42
TransmitWait->Idle	1314	Covered	T31,T42
TransmitWait->StretchTx	1146	Covered	T1,T7,T8
TransmitWait->TransmitSetup	1148	Covered	T1,T7,T8
WaitForStop->AcquireStart	1316	Covered	T1,T7,T8
WaitForStop->Idle	1314	Covered	T1,T7,T8

---

Branch Coverage for Module : i2c_fsm

	Line No.	Total	Covered	Percent
Branches		258	246	95.35
IF	156	14	13	92.86
IF	182	2	2	100.00
IF	195	5	5	100.00
IF	211	4	4	100.00
IF	224	4	4	100.00
IF	235	3	3	100.00
IF	242	4	4	100.00
IF	255	2	2	100.00
IF	269	5	5	100.00
IF	281	5	4	80.00
IF	303	5	5	100.00
IF	324	5	5	100.00
IF	335	4	4	100.00
IF	412	4	4	100.00
IF	435	3	3	100.00
CASE	477	73	67	91.78
IF	797	3	3	100.00
CASE	840	105	102	97.14
IF	1305	4	3	75.00
IF	1324	2	2	100.00
IF	1333	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	156	if (load_tcount)
-2-:	157	case (tcount_sel)
-3-:	171	if (((stretch_idle_cnt == '0) || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T2,T3,T16
1	tHoldStart	-	Covered	T2,T3,T16
1	tSetupData	-	Covered	T1,T7,T8
1	tClockStart	-	Covered	T1,T2,T3
1	tClockLow	-	Covered	T2,T3,T16
1	tClockPulse	-	Covered	T2,T3,T16
1	tHoldBit	-	Covered	T2,T3,T16
1	tClockStop	-	Covered	T2,T3,T16
1	tSetupStop	-	Covered	T2,T3,T16
1	tHoldStop	-	Covered	T2,T3,T16
1	tNoDelay	-	Covered	T2,T3,T16
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	182	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	195	if ((!rst_ni))
-2-:	197	if (((stretch_en && scl_d) && (!scl_i)))
-3-:	199	if (((!target_idle_o) && event_host_timeout_o))
-4-:	202	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T16
0	0	1	-	Covered	T1,T22,T23
0	0	0	1	Covered	T1,T7,T8
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_ni))
-2-:	213	if (bit_clr)
-3-:	215	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if ((!rst_ni))
-2-:	226	if (read_byte_clr)
-3-:	228	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T12
0	0	1	Covered	T2,T3,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!fmt_flag_read_bytes_i))
-2-:	236	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
0	0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	242	if ((!rst_ni))
-2-:	244	if (byte_clr)
-3-:	246	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T12
0	0	1	Covered	T2,T3,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	if ((!rst_ni))
-2-:	271	if ((trans_started && (!host_enable_i)))
-3-:	273	if (log_start)
-4-:	275	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T11,T27,T28
0	0	1	-	Covered	T2,T3,T16
0	0	0	1	Covered	T2,T3,T16
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if ((!rst_ni))
-2-:	283	if ((pend_restart && (!host_enable_i)))
-3-:	285	if (req_restart)
-4-:	287	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T12,T21,T24
0	0	0	1	Covered	T2,T3,T16
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))
-2-:	305	if (start_det)
-3-:	307	if ((scl_i_q && (!scl_i)))
-4-:	310	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T7,T8
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	if ((!rst_ni))
-2-:	326	if (input_byte_clr)
-3-:	328	if (((!scl_i_q) && scl_i))
-4-:	329	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T7,T8
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	if ((!rst_ni))
-2-:	337	if (((!scl_i_q) && scl_i))
-3-:	338	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	412	if ((!rst_ni))
-2-:	414	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	419	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	435	if ((!rst_ni))
-2-:	437	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	case (state_q)
-2-:	483	if ((host_enable_i && trans_started))
-3-:	496	if (log_start)
-4-:	512	if (pend_restart)
-5-:	525	if ((scl_i_q && (!scl_i)))
-6-:	526	if ((sda_i_q != sda_i))
-7-:	545	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	547	if ((scl_i_q && (!scl_i)))
-9-:	548	if ((sda_i_q != sda_i))
-10-:	567	if ((scl_i_q && (!scl_i)))
-11-:	568	if ((sda_i_q != sda_i))
-12-:	574	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	586	if (fmt_flag_read_continue_i)
-14-:	587	if ((byte_index == 9'b1))
-15-:	593	if (fmt_flag_read_continue_i)
-16-:	594	if ((byte_index == 9'b1))
-17-:	598	if ((scl_i_q && (!scl_i)))
-18-:	599	if ((sda_i_q != sda_i))
-19-:	604	if (fmt_flag_read_continue_i)
-20-:	605	if ((byte_index == 9'b1))
-21-:	641	if (fmt_flag_stop_after_i)
-22-:	674	if ((tcount_q == 20'b1))
-23-:	709	if ((!scl_i))
-24-:	743	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T21,T24
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T39,T34
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T21
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T21
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T12
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T12,T21
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T12
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T12
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T16
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T2,T3,T16
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T7,T8
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T7,T8
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T8
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T44,T45
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T44,T45
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	797	if ((start_det || stop_det))
-2-:	800	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	840	case (state_q)
-2-:	843	if (((!host_enable_i) && (!target_enable_i)))
-3-:	844	if (host_enable_i)
-4-:	845	if (fmt_fifo_rvalid_i)
-5-:	851	if ((tcount_q == 20'b1))
-6-:	860	if ((tcount_q == 20'b1))
-7-:	868	if ((tcount_q == 20'b1))
-8-:	877	if ((tcount_q == 20'b1))
-9-:	879	if (pend_restart)
-10-:	892	if ((tcount_q == 20'b1))
-11-:	901	if ((tcount_q == 20'b1))
-12-:	905	if ((bit_index == '0))
-13-:	917	if ((tcount_q == 20'b1))
-14-:	925	if ((tcount_q == 20'b1))
-15-:	933	if ((tcount_q == 20'b1))
-16-:	934	if (fmt_flag_stop_after_i)
-17-:	947	if ((tcount_q == 20'b1))
-18-:	955	if ((tcount_q == 20'b1))
-19-:	964	if ((tcount_q == 20'b1))
-20-:	967	if ((bit_index == '0))
-21-:	981	if ((tcount_q == 20'b1))
-22-:	990	if ((tcount_q == 20'b1))
-23-:	999	if ((tcount_q == 20'b1))
-24-:	1001	if ((byte_index == 9'b1))
-25-:	1002	if (fmt_flag_stop_after_i)
-26-:	1022	if ((tcount_q == 20'b1))
-27-:	1030	if ((tcount_q == 20'b1))
-28-:	1040	if ((tcount_q == 20'b1))
-29-:	1042	if ((!host_enable_i))
-30-:	1056	if (fmt_flag_read_bytes_i)
-31-:	1061	if ((fmt_flag_start_before_i && (!trans_started)))
-32-:	1075	if ((!host_enable_i))
-33-:	1079	if ((fmt_fifo_depth_i == 7'b1))
-34-:	1092	if ((scl_i_q && (!scl_i)))
-35-:	1101	if ((bit_ack && address_match))
-36-:	1105	if ((bit_ack && (!address_match)))
-37-:	1112	if (((tcount_q == 20'b1) && (!scl_i)))
-38-:	1118	if (scl_i)
-39-:	1122	if ((!scl_i))
-40-:	1130	if ((tcount_q == 20'b1))
-41-:	1134	if (stretch_addr)
-42-:	1136	if (rw_bit_q)
-43-:	1138	if ((!rw_bit_q))
-44-:	1145	if (stretch_tx)
-45-:	1155	if (scl_i)
-46-:	1159	if ((!scl_i))
-47-:	1167	if ((tcount_q == 20'b1))
-48-:	1168	if (bit_ack)
-49-:	1180	if (scl_i)
-50-:	1188	if ((!scl_i))
-51-:	1190	if (host_ack)
-52-:	1208	if (bit_ack)
-53-:	1217	if (((tcount_q == 20'b1) && (!scl_i)))
-54-:	1223	if (scl_i)
-55-:	1227	if ((!scl_i))
-56-:	1235	if ((tcount_q == 20'b1))
-57-:	1238	(acq_fifo_wready) ? 
-58-:	1244	if ((!stretch_addr))
-59-:	1250	(rw_bit_q) ? 
-60-:	1257	if ((!stretch_tx))
-61-:	1273	if ((tcount_q == 20'b1))
-62-:	1281	if (acq_fifo_wready)

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T2,T3,T16
(1.Idle )->(!2)->(3)->(!4)	Covered	T2,T3,T16
(1.Idle )->(!2)->(!3)	Covered	T1,T7,T8
(1.SetupStart )->(5)	Covered	T2,T3,T16
(1.SetupStart )->(!5)	Covered	T2,T3,T16
(1.HoldStart )->(6)	Covered	T2,T3,T16
(1.HoldStart )->(!6)	Covered	T2,T3,T16
(1.ClockStart )->(7)	Covered	T2,T3,T16
(1.ClockStart )->(!7)	Covered	T2,T3,T16
(1.ClockLow )->(8)->(9)	Covered	T12,T21,T24
(1.ClockLow )->(8)->(!9)	Covered	T2,T3,T16
(1.ClockLow )->(!8)	Covered	T2,T3,T16
(1.ClockPulse )->(10)	Covered	T2,T3,T16
(1.ClockPulse )->(!10)	Covered	T2,T3,T16
(1.HoldBit )->(11)->(12)	Covered	T2,T3,T16
(1.HoldBit )->(11)->(!12)	Covered	T2,T3,T16
(1.HoldBit )->(!11)	Covered	T2,T3,T16
(1.ClockLowAck )->(13)	Covered	T2,T3,T16
(1.ClockLowAck )->(!13)	Covered	T2,T3,T16
(1.ClockPulseAck )->(14)	Covered	T2,T3,T16
(1.ClockPulseAck )->(!14)	Covered	T2,T3,T16
(1.HoldDevAck )->(15)->(16)	Covered	T2,T3,T16
(1.HoldDevAck )->(15)->(!16)	Covered	T2,T3,T16
(1.HoldDevAck )->(!15)	Covered	T2,T3,T16
(1.ReadClockLow )->(17)	Covered	T2,T3,T12
(1.ReadClockLow )->(!17)	Covered	T2,T3,T12
(1.ReadClockPulse )->(18)	Covered	T2,T3,T12
(1.ReadClockPulse )->(!18)	Covered	T2,T3,T12
(1.ReadHoldBit )->(19)->(20)	Covered	T2,T3,T12
(1.ReadHoldBit )->(19)->(!20)	Covered	T2,T3,T12
(1.ReadHoldBit )->(!19)	Covered	T2,T3,T12
(1.HostClockLowAck )->(21)	Covered	T2,T3,T12
(1.HostClockLowAck )->(!21)	Covered	T2,T3,T12
(1.HostClockPulseAck )->(22)	Covered	T2,T3,T12
(1.HostClockPulseAck )->(!22)	Covered	T2,T3,T12
(1.HostHoldBitAck )->(23)->(24)->(25)	Covered	T2,T3,T12
(1.HostHoldBitAck )->(23)->(24)->(!25)	Covered	T2,T12,T21
(1.HostHoldBitAck )->(23)->(!24)	Covered	T2,T3,T12
(1.HostHoldBitAck )->(!23)	Covered	T2,T3,T12
(1.ClockStop )->(26)	Covered	T2,T3,T16
(1.ClockStop )->(!26)	Covered	T2,T3,T16
(1.SetupStop )->(27)	Covered	T2,T3,T16
(1.SetupStop )->(!27)	Covered	T2,T3,T16
(1.HoldStop )->(28)->(29)	Covered	T11,T27,T15
(1.HoldStop )->(28)->(!29)	Covered	T2,T3,T16
(1.HoldStop )->(!28)	Covered	T2,T3,T16
(1.Active )->(30)	Covered	T2,T3,T12
(1.Active )->(!30)->(31)	Covered	T2,T3,T16
(1.Active )->(!30)->(!31)	Covered	T2,T3,T16
(1.PopFmtFifo )->(32)	Covered	T11,T27,T15
(1.PopFmtFifo )->(!32)->(33)	Covered	T2,T3,T16
(1.PopFmtFifo )->(!32)->(!33)	Covered	T2,T3,T16
(1.AcquireStart )->(34)	Covered	T1,T7,T8
(1.AcquireStart )->(!34)	Covered	T1,T7,T8
(1.AddrRead )->(35)	Covered	T1,T7,T8
(1.AddrRead )->(!35)->(36)	Covered	T29,T43,T30
(1.AddrRead )->(!35)->(!36)	Covered	T1,T7,T8
(1.AddrAckWait )->(37)	Covered	T1,T7,T8
(1.AddrAckWait )->(!37)	Covered	T1,T7,T8
(1.AddrAckSetup )->(38)	Covered	T1,T7,T8
(1.AddrAckSetup )->(!38)	Covered	T1,T7,T8
(1.AddrAckPulse )->(39)	Covered	T1,T7,T8
(1.AddrAckPulse )->(!39)	Covered	T1,T7,T8
(1.AddrAckHold )->(40)->(41)	Covered	T1,T44,T45
(1.AddrAckHold )->(40)->(!41)->(42)	Covered	T1,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(43)	Covered	T1,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(!43)	Not Covered
(1.AddrAckHold )->(!40)	Covered	T1,T7,T8
(1.TransmitWait )->(44)	Covered	T1,T7,T8
(1.TransmitWait )->(!44)	Covered	T1,T7,T8
(1.TransmitSetup )->(45)	Covered	T1,T7,T8
(1.TransmitSetup )->(!45)	Covered	T1,T7,T8
(1.TransmitPulse )->(46)	Covered	T1,T7,T8
(1.TransmitPulse )->(!46)	Covered	T1,T7,T8
(1.TransmitHold )->(47)->(48)	Covered	T1,T7,T8
(1.TransmitHold )->(47)->(!48)	Covered	T1,T7,T8
(1.TransmitHold )->(!47)	Covered	T1,T7,T8
(1.TransmitAck )->(49)	Covered	T1,T7,T8
(1.TransmitAck )->(!49)	Covered	T1,T7,T8
(1.TransmitAckPulse )->(50)->(51)	Covered	T1,T7,T8
(1.TransmitAckPulse )->(50)->(!51)	Covered	T1,T7,T8
(1.TransmitAckPulse )->(!50)	Covered	T1,T7,T8
(1.WaitForStop )	Covered	T1,T7,T8
(1.AcquireByte )->(52)	Covered	T1,T7,T8
(1.AcquireByte )->(!52)	Covered	T1,T7,T8
(1.AcquireAckWait )->(53)	Covered	T1,T7,T8
(1.AcquireAckWait )->(!53)	Covered	T1,T7,T8
(1.AcquireAckSetup )->(54)	Covered	T1,T7,T8
(1.AcquireAckSetup )->(!54)	Covered	T1,T7,T8
(1.AcquireAckPulse )->(55)	Covered	T1,T7,T8
(1.AcquireAckPulse )->(!55)	Covered	T1,T7,T8
(1.AcquireAckHold )->(56)->(57)	Covered	T1,T7,T8
(1.AcquireAckHold )->(56)->(!57)	Covered	T1,T44,T45
(1.AcquireAckHold )->(!56)	Covered	T1,T7,T8
(1.StretchAddr )->(58)->(59)	Not Covered
(1.StretchAddr )->(58)->(!59)	Covered	T1,T44,T45
(1.StretchAddr )->(!58)	Covered	T1,T44,T45
(1.StretchTx )->(60)	Covered	T1,T7,T8
(1.StretchTx )->(!60)	Covered	T1,T7,T8
(1.StretchTxSetup )->(61)	Covered	T1,T7,T8
(1.StretchTxSetup )->(!61)	Covered	T1,T7,T8
(1.StretchAcqFull )->(62)	Covered	T1,T44,T45
(1.StretchAcqFull )->(!62)	Covered	T1,T44,T45
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1305	if (((!target_idle) && (!target_enable_i)))
-2-:	1315	if (start_det)
-3-:	1317	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T7,T8
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1324	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1333	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	503572374	2850694	0	0
SclInputGlitch_A	479484633	9892920	0	0
SclOutputGlitch_A	503572374	5333297	0	0
SclSdaChangeNotSimultaneous_A	503572374	503380120	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	2850694	0	0
T1	108038	8392	0	0
T2	906588	0	0	0
T3	642665	0	0	0
T4	1707	0	0	0
T7	464090	10671	0	0
T8	0	15889	0	0
T12	216536	0	0	0
T16	36458	0	0	0
T17	0	6153	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	0	0	0
T32	0	2451	0	0
T46	0	211	0	0
T53	0	76	0	0
T54	0	1518	0	0
T55	0	366	0	0
T56	0	4465	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479484633	9892920	0	0
T1	108038	29306	0	0
T2	906588	33390	0	0
T3	642665	23440	0	0
T4	1707	2	0	0
T7	464090	3320	0	0
T12	216536	14467	0	0
T16	36458	1138	0	0
T19	99	0	0	0
T20	26512	856	0	0
T21	297098	10444	0	0
T57	0	9270	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	5333297	0	0
T1	108038	495	0	0
T2	906588	33390	0	0
T3	642665	23440	0	0
T4	1707	0	0	0
T7	464090	87	0	0
T12	216536	14467	0	0
T16	36458	1138	0	0
T19	4284	40	0	0
T20	26512	856	0	0
T21	297098	10444	0	0
T57	0	9270	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Line No.	Total	Covered	Percent
TOTAL		554	546	98.56
ALWAYS	155	17	17	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	182	3	3	100.00
ALWAYS	195	9	9	100.00
ALWAYS	211	7	7	100.00
ALWAYS	224	6	6	100.00
ALWAYS	235	5	5	100.00
ALWAYS	242	7	7	100.00
ALWAYS	255	5	5	100.00
ALWAYS	269	8	8	100.00
ALWAYS	281	8	7	87.50
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	303	9	9	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	7	7	100.00
ALWAYS	335	5	5	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
ALWAYS	412	6	6	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	435	4	4	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
ALWAYS	460	180	174	96.67
CONT_ASSIGN	806	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	820	1	1	100.00
ALWAYS	824	239	238	99.58
ALWAYS	1324	3	3	100.00
ALWAYS	1333	5	5	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1353	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
171	1	1
172	1	1
174	1	1
179	1	1
182	1	1
183	1	1
185	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
201	1	1
202	1	1
203	1	1
205	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
235	2	2
236	2	2
237	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
249	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	0	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
293	1	1
296	1	1
299	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
310	2	2
311	1	1
313	1	1
318	1	1
319	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	2	2
			MISSING_ELSE
			MISSING_ELSE
335	1	1
336	1	1
337	1	1
338	2	2
			MISSING_ELSE
			MISSING_ELSE
348	1	1
349	1	1
407	1	1
412	1	1
413	1	1
414	1	1
418	1	1
419	1	1
420	1	1
			MISSING_ELSE
430	1	1
435	1	1
436	1	1
437	1	1
438	1	1
			MISSING_ELSE
452	1	1
456	1	1
460	1	1
461	1	1
462	1	1
463	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
482	1	1
483	1	1
484	0	1
485	0	1
487	1	1
488	1	1
493	1	1
494	1	1
495	1	1
496	2	2
			MISSING_ELSE
500	1	1
501	1	1
502	1	1
506	1	1
507	1	1
508	1	1
511	1	1
512	1	1
513	1	1
515	1	1
517	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	2
			MISSING_ELSE
526	2	2
			MISSING_ELSE
530	1	1
531	1	1
532	1	1
536	1	1
537	1	1
538	1	1
542	1	1
543	1	1
544	1	1
545	2	2
			MISSING_ELSE
546	1	1
547	1	2
			MISSING_ELSE
548	2	2
			MISSING_ELSE
552	1	1
553	1	1
554	1	1
558	1	1
559	1	1
560	1	1
564	1	1
565	1	1
566	1	1
567	1	2
			MISSING_ELSE
568	2	2
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
575	1	1
576	1	1
			MISSING_ELSE
581	1	1
582	1	1
586	2	2
587	2	2
588	1	1
592	1	1
593	2	2
594	2	2
595	1	1
596	1	1
597	1	1
598	1	2
			MISSING_ELSE
599	2	2
			MISSING_ELSE
603	1	1
604	2	2
605	2	2
606	1	1
607	1	1
611	1	1
612	1	1
613	1	1
617	1	1
618	1	1
619	1	1
623	1	1
624	1	1
625	1	1
626	1	1
630	1	1
636	1	1
640	1	1
641	2	2
642	1	1
643	1	1
647	1	1
651	1	1
652	1	1
656	1	1
660	1	1
661	1	1
665	1	1
666	1	1
670	1	1
671	1	1
674	1	1
676	1	1
677	1	1
			MISSING_ELSE
682	1	1
686	1	1
687	1	1
691	1	1
694	1	1
698	1	1
701	1	1
705	1	1
708	1	1
709	1	1
711	1	1
			MISSING_ELSE
716	1	1
717	1	1
718	1	1
722	1	1
726	1	1
730	1	1
731	1	1
735	1	1
736	1	1
740	1	1
741	1	1
743	1	1
744	1	1
745	1	1
			MISSING_ELSE
751	1	1
752	1	1
754	1	1
755	1	1
759	1	1
760	1	1
764	1	1
765	1	1
766	1	1
770	1	1
771	1	1
774	1	1
775	1	1
797	1	1
799	1	1
800	1	1
802	1	1
			MISSING_ELSE
806	1	1
815	1	1
820	1	1
824	1	1
825	1	1
826	1	1
827	1	1
828	1	1
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
834	1	1
835	1	1
836	1	1
837	1	1
838	1	1
840	1	1
843	2	2
844	1	1
845	2	2
			MISSING_ELSE
			MISSING_ELSE
851	1	1
852	1	1
853	1	1
854	1	1
855	1	1
			MISSING_ELSE
860	1	1
861	1	1
862	1	1
863	1	1
			MISSING_ELSE
868	1	1
869	1	1
870	1	1
871	1	1
			MISSING_ELSE
876	1	1
877	1	1
878	1	1
879	1	1
880	1	1
881	1	1
883	1	1
884	1	1
			MISSING_ELSE
891	1	1
892	1	1
893	1	1
894	1	1
895	1	1
			MISSING_ELSE
900	1	1
901	1	1
902	1	1
903	1	1
904	1	1
905	1	1
906	1	1
907	1	1
909	1	1
910	1	1
			MISSING_ELSE
917	1	1
918	1	1
919	1	1
920	1	1
			MISSING_ELSE
925	1	1
926	1	1
927	1	1
928	1	1
			MISSING_ELSE
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
939	1	1
940	1	1
941	1	1
			MISSING_ELSE
947	1	1
948	1	1
949	1	1
950	1	1
			MISSING_ELSE
955	1	1
956	1	1
957	1	1
958	1	1
959	1	1
			MISSING_ELSE
964	1	1
965	1	1
966	1	1
967	1	1
968	1	1
969	1	1
970	1	1
972	1	1
973	1	1
			MISSING_ELSE
980	1	1
981	1	1
982	1	1
983	1	1
984	1	1
			MISSING_ELSE
989	1	1
990	1	1
991	1	1
992	1	1
993	1	1
			MISSING_ELSE
998	1	1
999	1	1
1000	1	1
1001	1	1
1002	1	1
1003	1	1
1004	1	1
1005	1	1
1007	1	1
1008	1	1
1009	1	1
1012	1	1
1013	1	1
1014	1	1
1015	1	1
			MISSING_ELSE
1022	1	1
1023	1	1
1024	1	1
1025	1	1
			MISSING_ELSE
1030	1	1
1031	1	1
1032	1	1
1033	1	1
1034	1	1
			MISSING_ELSE
1039	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1044	1	1
1045	1	1
1047	1	1
1048	1	1
1049	1	1
			MISSING_ELSE
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1060	1	1
1061	1	1
1062	1	1
1063	1	1
1064	1	1
1066	1	1
1067	1	1
1068	1	1
1069	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1084	1	1
1085	1	1
1086	1	1
1092	1	1
1094	1	1
1095	1	1
			MISSING_ELSE
1101	1	1
1102	1	1
1103	1	1
1104	1	1
1105	1	1
1106	1	1
			MISSING_ELSE
1112	1	1
1113	1	1
			MISSING_ELSE
1118	2	2
			MISSING_ELSE
1122	1	1
1123	1	1
1124	1	1
1125	1	1
			MISSING_ELSE
1130	1	1
1134	1	1
1135	1	1
1136	1	1
1137	1	1
1138	1	1
1139	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1145	1	1
1146	1	1
1148	1	1
1149	1	1
1150	1	1
1155	2	2
			MISSING_ELSE
1159	1	1
1160	1	1
1161	1	1
1162	1	1
			MISSING_ELSE
1167	1	1
1168	1	1
1169	1	1
1171	1	1
1172	1	1
1173	1	1
			MISSING_ELSE
1180	1	1
1181	1	1
			MISSING_ELSE
1188	1	1
1190	1	1
1191	1	1
1194	1	1
			MISSING_ELSE
1203	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
			MISSING_ELSE
1217	1	1
1218	1	1
			MISSING_ELSE
1223	2	2
			MISSING_ELSE
1227	1	1
1228	1	1
1229	1	1
1230	1	1
			MISSING_ELSE
1235	1	1
1238	1	1
			MISSING_ELSE
1244	1	1
1250	1	1
			MISSING_ELSE
1256	1	1
1257	1	1
1264	1	1
1265	1	1
1266	1	1
1269	1	1
			MISSING_ELSE
1273	1	1
1274	1	1
			MISSING_ELSE
1281	2	2
			MISSING_ELSE
1305	1	1
1314	0	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
			MISSING_ELSE
1324	1	1
1325	1	1
1327	1	1
1333	1	1
1334	1	1
1335	1	1
1337	1	1
1338	1	1
1342	1	1
1343	1	1
1346	1	1
1349	1	1
1353	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Total	Covered	Percent
Conditions	242	228	94.21
Logical	242	228	94.21
Non-Logical	0	0
Event	0	0

 LINE       171
 EXPRESSION ((stretch_idle_cnt == '0) || target_enable_i)
             ------------1-----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T16
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3

 LINE       171
 SUB-EXPRESSION (stretch_idle_cnt == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION (stretch_en && scl_d && ((!scl_i)))
             -----1----    --2--    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

 LINE       199
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T22,T23

 LINE       202
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       236
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T24,T25,T26

 LINE       271
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T11,T27,T28

 LINE       283
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T21,T24
1	1	Not Covered

 LINE       293
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       293
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       296
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       299
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       310
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8

 LINE       318
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       319
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       320
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       328
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       419
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T16

 LINE       430
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T16

 LINE       430
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T16
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

 LINE       430
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T16
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

 LINE       430
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       437
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       456
 EXPRESSION (((!target_idle)) & rw_bit_q & stop_det & ((!expect_stop)))
             --------1-------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T29,T30,T31
1	0	1	1	Covered	T1,T7,T8
1	1	0	1	Covered	T1,T7,T8
1	1	1	0	Covered	T1,T7,T8
1	1	1	1	Covered	T1,T32,T33

 LINE       483
 EXPRESSION (host_enable_i && trans_started)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Not Covered

 LINE       525
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T16
1	1	Not Covered

 LINE       526
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       545
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T24,T34,T35
1	0	1	1	Covered	T2,T3,T16
1	1	0	1	Covered	T2,T3,T16
1	1	1	0	Covered	T36,T37,T38
1	1	1	1	Covered	T24,T39,T34

 LINE       547
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T16
1	1	Not Covered

 LINE       548
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       567
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Not Covered

 LINE       568
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       574
 EXPRESSION ((bit_index == '0) && (tcount_q == 20'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T3,T12

 LINE       574
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       574
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       587
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       594
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       598
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Not Covered

 LINE       599
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       605
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       636
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T9,T40,T41
1	0	Covered	T12,T21,T24
1	1	Covered	T2,T3,T16

 LINE       674
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       743
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       797
 EXPRESSION (start_det || stop_det)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       800
 EXPRESSION (start_det ? ({AcqRestart, input_byte}) : ({AcqStop, input_byte}))
             ----1----

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       815
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3

 LINE       843
 EXPRESSION (((!host_enable_i)) && ((!target_enable_i)))
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       851
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       860
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       868
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       877
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       892
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       901
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       905
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       917
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       925
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       933
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       947
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       955
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       964
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       967
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       981
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       990
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       999
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       1001
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T2,T3,T12

 LINE       1022
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1030
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1040
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1061
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T9,T40,T41
1	0	Covered	T12,T21,T24
1	1	Covered	T2,T3,T16

 LINE       1079
 EXPRESSION (fmt_fifo_depth_i == 7'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T16

 LINE       1092
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T42
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       1101
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T29,T43,T30
1	1	Covered	T1,T7,T8

 LINE       1105
 EXPRESSION (bit_ack && ((!address_match)))
             ---1---    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Not Covered
1	1	Covered	T29,T43,T30

 LINE       1112
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       1112
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1130
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1167
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1217
 EXPRESSION ((tcount_q == 20'b1) && ((!scl_i)))
             ---------1---------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       1217
 SUB-EXPRESSION (tcount_q == 20'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1235
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1238
 EXPRESSION (acq_fifo_wready ? AcquireByte : StretchAcqFull)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T44,T45
1	Covered	T1,T7,T8

 LINE       1250
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T1,T44,T45
1	Not Covered

 LINE       1273
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T8

 LINE       1305
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Not Covered

 LINE       1346
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T22,T23

 LINE       1349
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T46
1	0	1	Covered	T2,T3,T16
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T2,T3,T16

---

FSM Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	43	43	100.00	(Not included in score)
Transitions	115	106	92.17
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	1228	Covered	T1,T7,T8
AcquireAckPulse	1223	Covered	T1,T7,T8
AcquireAckSetup	1218	Covered	T1,T7,T8
AcquireAckWait	1209	Covered	T1,T7,T8
AcquireByte	1139	Covered	T1,T7,T8
AcquireStart	1316	Covered	T1,T7,T8
Active	845	Covered	T2,T3,T16
AddrAckHold	1123	Covered	T1,T7,T8
AddrAckPulse	1118	Covered	T1,T7,T8
AddrAckSetup	1113	Covered	T1,T7,T8
AddrAckWait	1102	Covered	T1,T7,T8
AddrRead	1094	Covered	T1,T7,T8
ClockLow	869	Covered	T2,T3,T16
ClockLowAck	906	Covered	T2,T3,T16
ClockPulse	883	Covered	T2,T3,T16
ClockPulseAck	918	Covered	T2,T3,T16
ClockStart	861	Covered	T2,T3,T16
ClockStop	935	Covered	T2,T3,T16
HoldBit	893	Covered	T2,T3,T16
HoldDevAck	926	Covered	T2,T3,T16
HoldStart	852	Covered	T2,T3,T16
HoldStop	1031	Covered	T2,T3,T16
HostClockLowAck	968	Covered	T2,T3,T12
HostClockPulseAck	982	Covered	T2,T3,T12
HostHoldBitAck	991	Covered	T2,T3,T12
Idle	843	Covered	T1,T2,T3
PopFmtFifo	939	Covered	T2,T3,T16
ReadClockLow	972	Covered	T2,T3,T12
ReadClockPulse	948	Covered	T2,T3,T12
ReadHoldBit	956	Covered	T2,T3,T12
SetupStart	880	Covered	T2,T3,T16
SetupStop	1023	Covered	T2,T3,T16
StretchAcqFull	1238	Covered	T1,T44,T45
StretchAddr	1135	Covered	T1,T44,T45
StretchTx	1146	Covered	T1,T7,T8
StretchTxSetup	1264	Covered	T1,T7,T8
TransmitAck	1169	Covered	T1,T7,T8
TransmitAckPulse	1181	Covered	T1,T7,T8
TransmitHold	1160	Covered	T1,T7,T8
TransmitPulse	1155	Covered	T1,T7,T8
TransmitSetup	1148	Covered	T1,T7,T8
TransmitWait	1137	Covered	T1,T7,T8
WaitForStop	1194	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	1238	Covered	T1,T7,T8
AcquireAckHold->AcquireStart	1316	Covered	T31,T42
AcquireAckHold->Idle	1314	Covered	T31,T42
AcquireAckHold->StretchAcqFull	1238	Covered	T1,T44,T45
AcquireAckPulse->AcquireAckHold	1228	Covered	T1,T7,T8
AcquireAckPulse->AcquireStart	1316	Covered	T31,T42
AcquireAckPulse->Idle	1314	Covered	T31,T42
AcquireAckSetup->AcquireAckPulse	1223	Covered	T1,T7,T8
AcquireAckSetup->AcquireStart	1316	Covered	T31,T42
AcquireAckSetup->Idle	1314	Covered	T31,T42
AcquireAckWait->AcquireAckSetup	1218	Covered	T1,T7,T8
AcquireAckWait->AcquireStart	1316	Covered	T31,T42
AcquireAckWait->Idle	1314	Covered	T31,T42
AcquireByte->AcquireAckWait	1209	Covered	T1,T7,T8
AcquireByte->AcquireStart	1316	Covered	T1,T7,T8
AcquireByte->Idle	1314	Covered	T1,T7,T8
AcquireStart->AddrRead	1094	Covered	T1,T7,T8
AcquireStart->Idle	1314	Covered	T31,T42
Active->AcquireStart	1316	Excluded
Active->ClockLow	1066	Covered	T2,T3,T16
Active->Idle	1314	Excluded
Active->ReadClockLow	1058	Covered	T2,T3,T12
Active->SetupStart	1062	Covered	T2,T3,T16
AddrAckHold->AcquireByte	1139	Covered	T1,T7,T8
AddrAckHold->AcquireStart	1316	Covered	T31,T42
AddrAckHold->Idle	1314	Covered	T31,T42
AddrAckHold->StretchAddr	1135	Covered	T1,T44,T45
AddrAckHold->TransmitWait	1137	Covered	T1,T7,T8
AddrAckPulse->AcquireStart	1316	Covered	T31,T42
AddrAckPulse->AddrAckHold	1123	Covered	T1,T7,T8
AddrAckPulse->Idle	1314	Covered	T31,T42
AddrAckSetup->AcquireStart	1316	Covered	T31,T42
AddrAckSetup->AddrAckPulse	1118	Covered	T1,T7,T8
AddrAckSetup->Idle	1314	Covered	T31,T42
AddrAckWait->AcquireStart	1316	Covered	T31,T42
AddrAckWait->AddrAckSetup	1113	Covered	T1,T7,T8
AddrAckWait->Idle	1314	Covered	T31,T42
AddrRead->AcquireStart	1316	Covered	T47,T48,T49
AddrRead->AddrAckWait	1102	Covered	T1,T7,T8
AddrRead->Idle	1106	Covered	T29,T43,T50
ClockLow->AcquireStart	1316	Excluded
ClockLow->ClockPulse	883	Covered	T2,T3,T16
ClockLow->Idle	1314	Covered	T19,T24,T51
ClockLow->SetupStart	880	Covered	T12,T21,T24
ClockLowAck->AcquireStart	1316	Excluded
ClockLowAck->ClockPulseAck	918	Covered	T2,T3,T16
ClockLowAck->Idle	1314	Not Covered
ClockPulse->AcquireStart	1316	Excluded
ClockPulse->HoldBit	893	Covered	T2,T3,T16
ClockPulse->Idle	1314	Covered	T19,T24,T51
ClockPulseAck->AcquireStart	1316	Excluded
ClockPulseAck->HoldDevAck	926	Covered	T2,T3,T16
ClockPulseAck->Idle	1314	Covered	T19,T24,T51
ClockStart->AcquireStart	1316	Excluded
ClockStart->ClockLow	869	Covered	T2,T3,T16
ClockStart->Idle	1314	Excluded
ClockStop->AcquireStart	1316	Excluded
ClockStop->Idle	1314	Excluded
ClockStop->SetupStop	1023	Covered	T2,T3,T16
HoldBit->AcquireStart	1316	Excluded
HoldBit->ClockLow	909	Covered	T2,T3,T16
HoldBit->ClockLowAck	906	Covered	T2,T3,T16
HoldBit->Idle	1314	Not Covered
HoldDevAck->AcquireStart	1316	Excluded
HoldDevAck->ClockStop	935	Covered	T2,T3,T16
HoldDevAck->Idle	1314	Not Covered
HoldDevAck->PopFmtFifo	939	Covered	T2,T3,T16
HoldStart->AcquireStart	1316	Excluded
HoldStart->ClockStart	861	Covered	T2,T3,T16
HoldStart->Idle	1314	Excluded
HoldStop->AcquireStart	1316	Excluded
HoldStop->Idle	1043	Covered	T11,T27,T15
HoldStop->PopFmtFifo	1047	Covered	T2,T3,T16
HostClockLowAck->AcquireStart	1316	Excluded
HostClockLowAck->HostClockPulseAck	982	Covered	T2,T3,T12
HostClockLowAck->Idle	1314	Excluded
HostClockPulseAck->AcquireStart	1316	Excluded
HostClockPulseAck->HostHoldBitAck	991	Covered	T2,T3,T12
HostClockPulseAck->Idle	1314	Not Covered
HostHoldBitAck->AcquireStart	1316	Excluded
HostHoldBitAck->ClockStop	1003	Covered	T2,T3,T12
HostHoldBitAck->Idle	1314	Not Covered
HostHoldBitAck->PopFmtFifo	1007	Covered	T2,T12,T21
HostHoldBitAck->ReadClockLow	1012	Covered	T2,T3,T12
Idle->AcquireStart	1316	Covered	T1,T7,T8
Idle->Active	845	Covered	T2,T3,T16
PopFmtFifo->AcquireStart	1316	Excluded
PopFmtFifo->Active	1084	Covered	T2,T3,T16
PopFmtFifo->ClockStop	1076	Covered	T11,T27,T15
PopFmtFifo->Idle	1080	Covered	T2,T3,T16
ReadClockLow->AcquireStart	1316	Excluded
ReadClockLow->Idle	1314	Not Covered
ReadClockLow->ReadClockPulse	948	Covered	T2,T3,T12
ReadClockPulse->AcquireStart	1316	Excluded
ReadClockPulse->Idle	1314	Not Covered
ReadClockPulse->ReadHoldBit	956	Covered	T2,T3,T12
ReadHoldBit->AcquireStart	1316	Excluded
ReadHoldBit->HostClockLowAck	968	Covered	T2,T3,T12
ReadHoldBit->Idle	1314	Not Covered
ReadHoldBit->ReadClockLow	972	Covered	T2,T3,T12
SetupStart->AcquireStart	1316	Excluded
SetupStart->HoldStart	852	Covered	T2,T3,T16
SetupStart->Idle	1314	Excluded
SetupStop->AcquireStart	1316	Excluded
SetupStop->HoldStop	1031	Covered	T2,T3,T16
SetupStop->Idle	1314	Excluded
StretchAcqFull->AcquireByte	1281	Covered	T1,T44,T45
StretchAcqFull->AcquireStart	1316	Covered	T31,T42
StretchAcqFull->Idle	1314	Covered	T31,T42
StretchAddr->AcquireByte	1250	Covered	T1,T44,T45
StretchAddr->AcquireStart	1316	Covered	T31,T42
StretchAddr->Idle	1314	Covered	T31,T42
StretchAddr->StretchTx	1250	Not Covered
StretchTx->AcquireStart	1316	Covered	T31,T42
StretchTx->Idle	1314	Covered	T31,T42
StretchTx->StretchTxSetup	1264	Covered	T1,T7,T8
StretchTxSetup->AcquireStart	1316	Covered	T31,T42
StretchTxSetup->Idle	1314	Covered	T31,T42
StretchTxSetup->TransmitSetup	1274	Covered	T1,T7,T8
TransmitAck->AcquireStart	1316	Covered	T31,T42
TransmitAck->Idle	1314	Covered	T31,T42
TransmitAck->TransmitAckPulse	1181	Covered	T1,T7,T8
TransmitAckPulse->AcquireStart	1316	Covered	T33,T52,T31
TransmitAckPulse->Idle	1314	Covered	T31,T42
TransmitAckPulse->TransmitWait	1191	Covered	T1,T7,T8
TransmitAckPulse->WaitForStop	1194	Covered	T1,T7,T8
TransmitHold->AcquireStart	1316	Covered	T31,T42
TransmitHold->Idle	1314	Covered	T31,T42
TransmitHold->TransmitAck	1169	Covered	T1,T7,T8
TransmitHold->TransmitSetup	1173	Covered	T1,T7,T8
TransmitPulse->AcquireStart	1316	Covered	T1,T32,T33
TransmitPulse->Idle	1314	Covered	T1,T32,T33
TransmitPulse->TransmitHold	1160	Covered	T1,T7,T8
TransmitSetup->AcquireStart	1316	Covered	T31,T42
TransmitSetup->Idle	1314	Covered	T31,T42
TransmitSetup->TransmitPulse	1155	Covered	T1,T7,T8
TransmitWait->AcquireStart	1316	Covered	T31,T42
TransmitWait->Idle	1314	Covered	T31,T42
TransmitWait->StretchTx	1146	Covered	T1,T7,T8
TransmitWait->TransmitSetup	1148	Covered	T1,T7,T8
WaitForStop->AcquireStart	1316	Covered	T1,T7,T8
WaitForStop->Idle	1314	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Line No.	Total	Covered	Percent
Branches		258	246	95.35
IF	156	14	13	92.86
IF	182	2	2	100.00
IF	195	5	5	100.00
IF	211	4	4	100.00
IF	224	4	4	100.00
IF	235	3	3	100.00
IF	242	4	4	100.00
IF	255	2	2	100.00
IF	269	5	5	100.00
IF	281	5	4	80.00
IF	303	5	5	100.00
IF	324	5	5	100.00
IF	335	4	4	100.00
IF	412	4	4	100.00
IF	435	3	3	100.00
CASE	477	73	67	91.78
IF	797	3	3	100.00
CASE	840	105	102	97.14
IF	1305	4	3	75.00
IF	1324	2	2	100.00
IF	1333	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	156	if (load_tcount)
-2-:	157	case (tcount_sel)
-3-:	171	if (((stretch_idle_cnt == '0) || target_enable_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T2,T3,T16
1	tHoldStart	-	Covered	T2,T3,T16
1	tSetupData	-	Covered	T1,T7,T8
1	tClockStart	-	Covered	T1,T2,T3
1	tClockLow	-	Covered	T2,T3,T16
1	tClockPulse	-	Covered	T2,T3,T16
1	tHoldBit	-	Covered	T2,T3,T16
1	tClockStop	-	Covered	T2,T3,T16
1	tSetupStop	-	Covered	T2,T3,T16
1	tHoldStop	-	Covered	T2,T3,T16
1	tNoDelay	-	Covered	T2,T3,T16
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	182	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	195	if ((!rst_ni))
-2-:	197	if (((stretch_en && scl_d) && (!scl_i)))
-3-:	199	if (((!target_idle_o) && event_host_timeout_o))
-4-:	202	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T3,T16
0	0	1	-	Covered	T1,T22,T23
0	0	0	1	Covered	T1,T7,T8
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_ni))
-2-:	213	if (bit_clr)
-3-:	215	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if ((!rst_ni))
-2-:	226	if (read_byte_clr)
-3-:	228	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T12
0	0	1	Covered	T2,T3,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!fmt_flag_read_bytes_i))
-2-:	236	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
0	0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	242	if ((!rst_ni))
-2-:	244	if (byte_clr)
-3-:	246	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T12
0	0	1	Covered	T2,T3,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	if ((!rst_ni))
-2-:	271	if ((trans_started && (!host_enable_i)))
-3-:	273	if (log_start)
-4-:	275	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T11,T27,T28
0	0	1	-	Covered	T2,T3,T16
0	0	0	1	Covered	T2,T3,T16
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if ((!rst_ni))
-2-:	283	if ((pend_restart && (!host_enable_i)))
-3-:	285	if (req_restart)
-4-:	287	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T12,T21,T24
0	0	0	1	Covered	T2,T3,T16
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))
-2-:	305	if (start_det)
-3-:	307	if ((scl_i_q && (!scl_i)))
-4-:	310	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T7,T8
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	if ((!rst_ni))
-2-:	326	if (input_byte_clr)
-3-:	328	if (((!scl_i_q) && scl_i))
-4-:	329	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T7,T8
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	if ((!rst_ni))
-2-:	337	if (((!scl_i_q) && scl_i))
-3-:	338	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	412	if ((!rst_ni))
-2-:	414	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	419	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T16
0	0	1	Covered	T2,T3,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	435	if ((!rst_ni))
-2-:	437	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	case (state_q)
-2-:	483	if ((host_enable_i && trans_started))
-3-:	496	if (log_start)
-4-:	512	if (pend_restart)
-5-:	525	if ((scl_i_q && (!scl_i)))
-6-:	526	if ((sda_i_q != sda_i))
-7-:	545	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	547	if ((scl_i_q && (!scl_i)))
-9-:	548	if ((sda_i_q != sda_i))
-10-:	567	if ((scl_i_q && (!scl_i)))
-11-:	568	if ((sda_i_q != sda_i))
-12-:	574	if (((bit_index == '0) && (tcount_q == 20'b1)))
-13-:	586	if (fmt_flag_read_continue_i)
-14-:	587	if ((byte_index == 9'b1))
-15-:	593	if (fmt_flag_read_continue_i)
-16-:	594	if ((byte_index == 9'b1))
-17-:	598	if ((scl_i_q && (!scl_i)))
-18-:	599	if ((sda_i_q != sda_i))
-19-:	604	if (fmt_flag_read_continue_i)
-20-:	605	if ((byte_index == 9'b1))
-21-:	641	if (fmt_flag_stop_after_i)
-22-:	674	if ((tcount_q == 20'b1))
-23-:	709	if ((!scl_i))
-24-:	743	if ((tcount_q == 20'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T21,T24
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T39,T34
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T21
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T21
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T12
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T12
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T12,T21
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T12
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T12
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T16
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T16
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T2,T3,T16
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T7,T8
AddrAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T7,T8
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T8
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T7,T8
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T7,T8
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T8
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T44,T45
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T44,T45
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	797	if ((start_det || stop_det))
-2-:	800	(start_det) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	840	case (state_q)
-2-:	843	if (((!host_enable_i) && (!target_enable_i)))
-3-:	844	if (host_enable_i)
-4-:	845	if (fmt_fifo_rvalid_i)
-5-:	851	if ((tcount_q == 20'b1))
-6-:	860	if ((tcount_q == 20'b1))
-7-:	868	if ((tcount_q == 20'b1))
-8-:	877	if ((tcount_q == 20'b1))
-9-:	879	if (pend_restart)
-10-:	892	if ((tcount_q == 20'b1))
-11-:	901	if ((tcount_q == 20'b1))
-12-:	905	if ((bit_index == '0))
-13-:	917	if ((tcount_q == 20'b1))
-14-:	925	if ((tcount_q == 20'b1))
-15-:	933	if ((tcount_q == 20'b1))
-16-:	934	if (fmt_flag_stop_after_i)
-17-:	947	if ((tcount_q == 20'b1))
-18-:	955	if ((tcount_q == 20'b1))
-19-:	964	if ((tcount_q == 20'b1))
-20-:	967	if ((bit_index == '0))
-21-:	981	if ((tcount_q == 20'b1))
-22-:	990	if ((tcount_q == 20'b1))
-23-:	999	if ((tcount_q == 20'b1))
-24-:	1001	if ((byte_index == 9'b1))
-25-:	1002	if (fmt_flag_stop_after_i)
-26-:	1022	if ((tcount_q == 20'b1))
-27-:	1030	if ((tcount_q == 20'b1))
-28-:	1040	if ((tcount_q == 20'b1))
-29-:	1042	if ((!host_enable_i))
-30-:	1056	if (fmt_flag_read_bytes_i)
-31-:	1061	if ((fmt_flag_start_before_i && (!trans_started)))
-32-:	1075	if ((!host_enable_i))
-33-:	1079	if ((fmt_fifo_depth_i == 7'b1))
-34-:	1092	if ((scl_i_q && (!scl_i)))
-35-:	1101	if ((bit_ack && address_match))
-36-:	1105	if ((bit_ack && (!address_match)))
-37-:	1112	if (((tcount_q == 20'b1) && (!scl_i)))
-38-:	1118	if (scl_i)
-39-:	1122	if ((!scl_i))
-40-:	1130	if ((tcount_q == 20'b1))
-41-:	1134	if (stretch_addr)
-42-:	1136	if (rw_bit_q)
-43-:	1138	if ((!rw_bit_q))
-44-:	1145	if (stretch_tx)
-45-:	1155	if (scl_i)
-46-:	1159	if ((!scl_i))
-47-:	1167	if ((tcount_q == 20'b1))
-48-:	1168	if (bit_ack)
-49-:	1180	if (scl_i)
-50-:	1188	if ((!scl_i))
-51-:	1190	if (host_ack)
-52-:	1208	if (bit_ack)
-53-:	1217	if (((tcount_q == 20'b1) && (!scl_i)))
-54-:	1223	if (scl_i)
-55-:	1227	if ((!scl_i))
-56-:	1235	if ((tcount_q == 20'b1))
-57-:	1238	(acq_fifo_wready) ? 
-58-:	1244	if ((!stretch_addr))
-59-:	1250	(rw_bit_q) ? 
-60-:	1257	if ((!stretch_tx))
-61-:	1273	if ((tcount_q == 20'b1))
-62-:	1281	if (acq_fifo_wready)

Branches:

Branch	Status	Tests
(1.Idle )->(2)	Covered	T1,T2,T3
(1.Idle )->(!2)->(3)->(4)	Covered	T2,T3,T16
(1.Idle )->(!2)->(3)->(!4)	Covered	T2,T3,T16
(1.Idle )->(!2)->(!3)	Covered	T1,T7,T8
(1.SetupStart )->(5)	Covered	T2,T3,T16
(1.SetupStart )->(!5)	Covered	T2,T3,T16
(1.HoldStart )->(6)	Covered	T2,T3,T16
(1.HoldStart )->(!6)	Covered	T2,T3,T16
(1.ClockStart )->(7)	Covered	T2,T3,T16
(1.ClockStart )->(!7)	Covered	T2,T3,T16
(1.ClockLow )->(8)->(9)	Covered	T12,T21,T24
(1.ClockLow )->(8)->(!9)	Covered	T2,T3,T16
(1.ClockLow )->(!8)	Covered	T2,T3,T16
(1.ClockPulse )->(10)	Covered	T2,T3,T16
(1.ClockPulse )->(!10)	Covered	T2,T3,T16
(1.HoldBit )->(11)->(12)	Covered	T2,T3,T16
(1.HoldBit )->(11)->(!12)	Covered	T2,T3,T16
(1.HoldBit )->(!11)	Covered	T2,T3,T16
(1.ClockLowAck )->(13)	Covered	T2,T3,T16
(1.ClockLowAck )->(!13)	Covered	T2,T3,T16
(1.ClockPulseAck )->(14)	Covered	T2,T3,T16
(1.ClockPulseAck )->(!14)	Covered	T2,T3,T16
(1.HoldDevAck )->(15)->(16)	Covered	T2,T3,T16
(1.HoldDevAck )->(15)->(!16)	Covered	T2,T3,T16
(1.HoldDevAck )->(!15)	Covered	T2,T3,T16
(1.ReadClockLow )->(17)	Covered	T2,T3,T12
(1.ReadClockLow )->(!17)	Covered	T2,T3,T12
(1.ReadClockPulse )->(18)	Covered	T2,T3,T12
(1.ReadClockPulse )->(!18)	Covered	T2,T3,T12
(1.ReadHoldBit )->(19)->(20)	Covered	T2,T3,T12
(1.ReadHoldBit )->(19)->(!20)	Covered	T2,T3,T12
(1.ReadHoldBit )->(!19)	Covered	T2,T3,T12
(1.HostClockLowAck )->(21)	Covered	T2,T3,T12
(1.HostClockLowAck )->(!21)	Covered	T2,T3,T12
(1.HostClockPulseAck )->(22)	Covered	T2,T3,T12
(1.HostClockPulseAck )->(!22)	Covered	T2,T3,T12
(1.HostHoldBitAck )->(23)->(24)->(25)	Covered	T2,T3,T12
(1.HostHoldBitAck )->(23)->(24)->(!25)	Covered	T2,T12,T21
(1.HostHoldBitAck )->(23)->(!24)	Covered	T2,T3,T12
(1.HostHoldBitAck )->(!23)	Covered	T2,T3,T12
(1.ClockStop )->(26)	Covered	T2,T3,T16
(1.ClockStop )->(!26)	Covered	T2,T3,T16
(1.SetupStop )->(27)	Covered	T2,T3,T16
(1.SetupStop )->(!27)	Covered	T2,T3,T16
(1.HoldStop )->(28)->(29)	Covered	T11,T27,T15
(1.HoldStop )->(28)->(!29)	Covered	T2,T3,T16
(1.HoldStop )->(!28)	Covered	T2,T3,T16
(1.Active )->(30)	Covered	T2,T3,T12
(1.Active )->(!30)->(31)	Covered	T2,T3,T16
(1.Active )->(!30)->(!31)	Covered	T2,T3,T16
(1.PopFmtFifo )->(32)	Covered	T11,T27,T15
(1.PopFmtFifo )->(!32)->(33)	Covered	T2,T3,T16
(1.PopFmtFifo )->(!32)->(!33)	Covered	T2,T3,T16
(1.AcquireStart )->(34)	Covered	T1,T7,T8
(1.AcquireStart )->(!34)	Covered	T1,T7,T8
(1.AddrRead )->(35)	Covered	T1,T7,T8
(1.AddrRead )->(!35)->(36)	Covered	T29,T43,T30
(1.AddrRead )->(!35)->(!36)	Covered	T1,T7,T8
(1.AddrAckWait )->(37)	Covered	T1,T7,T8
(1.AddrAckWait )->(!37)	Covered	T1,T7,T8
(1.AddrAckSetup )->(38)	Covered	T1,T7,T8
(1.AddrAckSetup )->(!38)	Covered	T1,T7,T8
(1.AddrAckPulse )->(39)	Covered	T1,T7,T8
(1.AddrAckPulse )->(!39)	Covered	T1,T7,T8
(1.AddrAckHold )->(40)->(41)	Covered	T1,T44,T45
(1.AddrAckHold )->(40)->(!41)->(42)	Covered	T1,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(43)	Covered	T1,T7,T8
(1.AddrAckHold )->(40)->(!41)->(!42)->(!43)	Not Covered
(1.AddrAckHold )->(!40)	Covered	T1,T7,T8
(1.TransmitWait )->(44)	Covered	T1,T7,T8
(1.TransmitWait )->(!44)	Covered	T1,T7,T8
(1.TransmitSetup )->(45)	Covered	T1,T7,T8
(1.TransmitSetup )->(!45)	Covered	T1,T7,T8
(1.TransmitPulse )->(46)	Covered	T1,T7,T8
(1.TransmitPulse )->(!46)	Covered	T1,T7,T8
(1.TransmitHold )->(47)->(48)	Covered	T1,T7,T8
(1.TransmitHold )->(47)->(!48)	Covered	T1,T7,T8
(1.TransmitHold )->(!47)	Covered	T1,T7,T8
(1.TransmitAck )->(49)	Covered	T1,T7,T8
(1.TransmitAck )->(!49)	Covered	T1,T7,T8
(1.TransmitAckPulse )->(50)->(51)	Covered	T1,T7,T8
(1.TransmitAckPulse )->(50)->(!51)	Covered	T1,T7,T8
(1.TransmitAckPulse )->(!50)	Covered	T1,T7,T8
(1.WaitForStop )	Covered	T1,T7,T8
(1.AcquireByte )->(52)	Covered	T1,T7,T8
(1.AcquireByte )->(!52)	Covered	T1,T7,T8
(1.AcquireAckWait )->(53)	Covered	T1,T7,T8
(1.AcquireAckWait )->(!53)	Covered	T1,T7,T8
(1.AcquireAckSetup )->(54)	Covered	T1,T7,T8
(1.AcquireAckSetup )->(!54)	Covered	T1,T7,T8
(1.AcquireAckPulse )->(55)	Covered	T1,T7,T8
(1.AcquireAckPulse )->(!55)	Covered	T1,T7,T8
(1.AcquireAckHold )->(56)->(57)	Covered	T1,T7,T8
(1.AcquireAckHold )->(56)->(!57)	Covered	T1,T44,T45
(1.AcquireAckHold )->(!56)	Covered	T1,T7,T8
(1.StretchAddr )->(58)->(59)	Not Covered
(1.StretchAddr )->(58)->(!59)	Covered	T1,T44,T45
(1.StretchAddr )->(!58)	Covered	T1,T44,T45
(1.StretchTx )->(60)	Covered	T1,T7,T8
(1.StretchTx )->(!60)	Covered	T1,T7,T8
(1.StretchTxSetup )->(61)	Covered	T1,T7,T8
(1.StretchTxSetup )->(!61)	Covered	T1,T7,T8
(1.StretchAcqFull )->(62)	Covered	T1,T44,T45
(1.StretchAcqFull )->(!62)	Covered	T1,T44,T45
(1.default)	Not Covered

	LineNo.	Expression
-1-:	1305	if (((!target_idle) && (!target_enable_i)))
-2-:	1315	if (start_det)
-3-:	1317	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T7,T8
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1324	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1333	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	503572374	2850694	0	0
SclInputGlitch_A	479484633	9892920	0	0
SclOutputGlitch_A	503572374	5333297	0	0
SclSdaChangeNotSimultaneous_A	503572374	503380120	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	2850694	0	0
T1	108038	8392	0	0
T2	906588	0	0	0
T3	642665	0	0	0
T4	1707	0	0	0
T7	464090	10671	0	0
T8	0	15889	0	0
T12	216536	0	0	0
T16	36458	0	0	0
T17	0	6153	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	0	0	0
T32	0	2451	0	0
T46	0	211	0	0
T53	0	76	0	0
T54	0	1518	0	0
T55	0	366	0	0
T56	0	4465	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479484633	9892920	0	0
T1	108038	29306	0	0
T2	906588	33390	0	0
T3	642665	23440	0	0
T4	1707	2	0	0
T7	464090	3320	0	0
T12	216536	14467	0	0
T16	36458	1138	0	0
T19	99	0	0	0
T20	26512	856	0	0
T21	297098	10444	0	0
T57	0	9270	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	5333297	0	0
T1	108038	495	0	0
T2	906588	33390	0	0
T3	642665	23440	0	0
T4	1707	0	0	0
T7	464090	87	0	0
T12	216536	14467	0	0
T16	36458	1138	0	0
T19	4284	40	0	0
T20	26512	856	0	0
T21	297098	10444	0	0
T57	0	9270	0	0

SclSdaChangeNotSimultaneous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0