Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.47	100.00	85.90			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_txfifo	95.19	100.00	80.77			100.00	100.00
tb.dut.i2c_core.u_i2c_fmtfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_rxfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_acqfifo	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_txfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fmtfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_acqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.17	96.63	73.13			90.91	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 + Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.i2c_core.u_i2c_fmtfifo

SCORE	LINE
96.15	100.00

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	LINE
95.19	100.00

tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=10,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.12	100.00

tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T27,T15
1	0	1	Covered	T2,T3,T16
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=10,Pass=0,Depth=268,OutputZeroIfEmpty=1,Secure=0,DepthW=9,gen_normal_fifo.PTRV_W=9,gen_normal_fifo.PTR_WIDTH=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.12	88.46

tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (9'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T44,T45

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T8,T46
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T8,T46
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T42
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T61,T62,T63
1	0	1	Covered	T1,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T44,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T44,T45

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	COND
95.19	80.77

tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T21

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T21

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2014289496	617004338	0	0
DepthKnown_A	2014289496	2013520480	0	0
RvalidKnown_A	2014289496	2013520480	0	0
WreadyKnown_A	2014289496	2013520480	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2014289496	617004338	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2014289496	617004338	0	0
T1	216076	793455	0	0
T2	3626352	1080149	0	0
T3	2570660	930638	0	0
T4	6828	0	0	0
T7	1856360	448778	0	0
T8	0	452194	0	0
T12	866144	221009	0	0
T13	0	433533	0	0
T16	145832	33937	0	0
T19	17136	1126	0	0
T20	106048	25531	0	0
T21	1188392	310848	0	0
T32	0	52000	0	0
T44	0	971609	0	0
T46	0	37466	0	0
T53	0	829	0	0
T54	0	69194	0	0
T55	0	1088	0	0
T56	0	100792	0	0
T57	470870	276596	0	0
T64	0	59400	0	0
T65	0	2242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2014289496	2013520480	0	0
T1	432152	432040	0	0
T2	3626352	3625548	0	0
T3	2570660	2570384	0	0
T4	6828	6596	0	0
T7	1856360	1856040	0	0
T12	866144	865768	0	0
T16	145832	145620	0	0
T19	17136	14184	0	0
T20	106048	105672	0	0
T21	1188392	1188180	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2014289496	2013520480	0	0
T1	432152	432040	0	0
T2	3626352	3625548	0	0
T3	2570660	2570384	0	0
T4	6828	6596	0	0
T7	1856360	1856040	0	0
T12	866144	865768	0	0
T16	145832	145620	0	0
T19	17136	14184	0	0
T20	106048	105672	0	0
T21	1188392	1188180	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2014289496	2013520480	0	0
T1	432152	432040	0	0
T2	3626352	3625548	0	0
T3	2570660	2570384	0	0
T4	6828	6596	0	0
T7	1856360	1856040	0	0
T12	866144	865768	0	0
T16	145832	145620	0	0
T19	17136	14184	0	0
T20	106048	105672	0	0
T21	1188392	1188180	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2014289496	617004338	0	0
T1	216076	793455	0	0
T2	3626352	1080149	0	0
T3	2570660	930638	0	0
T4	6828	0	0	0
T7	1856360	448778	0	0
T8	0	452194	0	0
T12	866144	221009	0	0
T13	0	433533	0	0
T16	145832	33937	0	0
T19	17136	1126	0	0
T20	106048	25531	0	0
T21	1188392	310848	0	0
T32	0	52000	0	0
T44	0	971609	0	0
T46	0	37466	0	0
T53	0	829	0	0
T54	0	69194	0	0
T55	0	1088	0	0
T56	0	100792	0	0
T57	470870	276596	0	0
T64	0	59400	0	0
T65	0	2242	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T17,T18

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T17,T18

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T17,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503572374	130614451	0	0
DepthKnown_A	503572374	503380120	0	0
RvalidKnown_A	503572374	503380120	0	0
WreadyKnown_A	503572374	503380120	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	503572374	130614451	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	130614451	0	0
T1	108038	305873	0	0
T2	906588	0	0	0
T3	642665	0	0	0
T4	1707	0	0	0
T7	464090	369116	0	0
T8	0	750940	0	0
T12	216536	0	0	0
T16	36458	0	0	0
T17	0	242163	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	0	0	0
T32	0	77276	0	0
T46	0	26486	0	0
T53	0	70735	0	0
T54	0	68192	0	0
T55	0	30378	0	0
T56	0	943781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	130614451	0	0
T1	108038	305873	0	0
T2	906588	0	0	0
T3	642665	0	0	0
T4	1707	0	0	0
T7	464090	369116	0	0
T8	0	750940	0	0
T12	216536	0	0	0
T16	36458	0	0	0
T17	0	242163	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	0	0	0
T32	0	77276	0	0
T46	0	26486	0	0
T53	0	70735	0	0
T54	0	68192	0	0
T55	0	30378	0	0
T56	0	943781	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T27,T15
1	0	1	Covered	T2,T3,T16
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503572374	167175242	0	0
DepthKnown_A	503572374	503380120	0	0
RvalidKnown_A	503572374	503380120	0	0
WreadyKnown_A	503572374	503380120	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	503572374	167175242	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	167175242	0	0
T2	906588	889665	0	0
T3	642665	632771	0	0
T4	1707	0	0	0
T7	464090	0	0	0
T12	216536	211189	0	0
T13	0	211222	0	0
T16	36458	33937	0	0
T19	4284	1126	0	0
T20	26512	25531	0	0
T21	297098	295208	0	0
T57	235435	232118	0	0
T64	0	58088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	167175242	0	0
T2	906588	889665	0	0
T3	642665	632771	0	0
T4	1707	0	0	0
T7	464090	0	0	0
T12	216536	211189	0	0
T13	0	211222	0	0
T16	36458	33937	0	0
T19	4284	1126	0	0
T20	26512	25531	0	0
T21	297098	295208	0	0
T57	235435	232118	0	0
T64	0	58088	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T21

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T14,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T12

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T21

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T21
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503572374	46746491	0	0
DepthKnown_A	503572374	503380120	0	0
RvalidKnown_A	503572374	503380120	0	0
WreadyKnown_A	503572374	503380120	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	503572374	46746491	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	46746491	0	0
T2	906588	190484	0	0
T3	642665	297867	0	0
T4	1707	0	0	0
T7	464090	0	0	0
T11	0	5981	0	0
T12	216536	9820	0	0
T13	0	222311	0	0
T16	36458	0	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	15640	0	0
T24	0	27241	0	0
T57	235435	44478	0	0
T64	0	1312	0	0
T65	0	2242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	46746491	0	0
T2	906588	190484	0	0
T3	642665	297867	0	0
T4	1707	0	0	0
T7	464090	0	0	0
T11	0	5981	0	0
T12	216536	9820	0	0
T13	0	222311	0	0
T16	36458	0	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	15640	0	0
T24	0	27241	0	0
T57	235435	44478	0	0
T64	0	1312	0	0
T65	0	2242	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (9'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T44,T45

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((9'(gen_normal_fifo.wptr_value) - 9'(gen_normal_fifo.rptr_value))) : (((9'(Depth) - 9'(gen_normal_fifo.rptr_value)) + 9'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T8,T46
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T8,T46
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T42
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T61,T62,T63
1	0	1	Covered	T1,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T44,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T44,T45

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T44,T45
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T8,T46

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503572374	272468154	0	0
DepthKnown_A	503572374	503380120	0	0
RvalidKnown_A	503572374	503380120	0	0
WreadyKnown_A	503572374	503380120	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	503572374	272468154	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	272468154	0	0
T1	108038	793455	0	0
T2	906588	0	0	0
T3	642665	0	0	0
T4	1707	0	0	0
T7	464090	448778	0	0
T8	0	452194	0	0
T12	216536	0	0	0
T16	36458	0	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	0	0	0
T32	0	52000	0	0
T44	0	971609	0	0
T46	0	37466	0	0
T53	0	829	0	0
T54	0	69194	0	0
T55	0	1088	0	0
T56	0	100792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	503380120	0	0
T1	108038	108010	0	0
T2	906588	906387	0	0
T3	642665	642596	0	0
T4	1707	1649	0	0
T7	464090	464010	0	0
T12	216536	216442	0	0
T16	36458	36405	0	0
T19	4284	3546	0	0
T20	26512	26418	0	0
T21	297098	297045	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	503572374	272468154	0	0
T1	108038	793455	0	0
T2	906588	0	0	0
T3	642665	0	0	0
T4	1707	0	0	0
T7	464090	448778	0	0
T8	0	452194	0	0
T12	216536	0	0	0
T16	36458	0	0	0
T19	4284	0	0	0
T20	26512	0	0	0
T21	297098	0	0	0
T32	0	52000	0	0
T44	0	971609	0	0
T46	0	37466	0	0
T53	0	829	0	0
T54	0	69194	0	0
T55	0	1088	0	0
T56	0	100792	0	0