Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	504237123	8381	0	0
ctrl_rd_A	504237123	978	0	0
host_fifo_config_rd_A	504237123	4115	0	0
host_timeout_ctrl_rd_A	504237123	931	0	0
intr_enable_rd_A	504237123	3122	0	0
ovrd_rd_A	504237123	1500	0	0
target_fifo_config_rd_A	504237123	874	0	0
target_id_rd_A	504237123	1190	0	0
timeout_ctrl_rd_A	504237123	924	0	0
timing0_rd_A	504237123	973	0	0
timing1_rd_A	504237123	909	0	0
timing2_rd_A	504237123	933	0	0
timing3_rd_A	504237123	908	0	0
timing4_rd_A	504237123	951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	8381	0	0
T66	3232	19	0	0
T67	6052	296	0	0
T68	12519	446	0	0
T69	5686	1	0	0
T70	4114	638	0	0
T74	6869	1	0	0
T75	7179	2	0	0
T76	3108	32	0	0
T78	3162	125	0	0
T80	9695	558	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	978	0	0
T66	3232	10	0	0
T67	6052	14	0	0
T68	12519	8	0	0
T76	3108	10	0	0
T90	12368	67	0	0
T113	1988	6	0	0
T131	5337	78	0	0
T132	6517	30	0	0
T133	2526	11	0	0
T134	2584	9	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	4115	0	0
T10	17580	0	0	0
T14	181151	0	0	0
T15	274292	0	0	0
T27	186665	0	0	0
T105	0	93	0	0
T135	354972	71	0	0
T136	527917	182	0	0
T137	0	91	0	0
T138	0	228	0	0
T139	0	107	0	0
T140	0	197	0	0
T141	0	178	0	0
T142	0	192	0	0
T143	0	150	0	0
T144	24389	0	0	0
T145	18485	0	0	0
T146	83027	0	0	0
T147	37302	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	931	0	0
T66	3232	8	0	0
T67	6052	21	0	0
T68	12519	32	0	0
T76	3108	4	0	0
T90	12368	22	0	0
T92	5365	5	0	0
T113	1988	1	0	0
T131	5337	62	0	0
T132	6517	14	0	0
T133	2526	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	3122	0	0
T28	285897	0	0	0
T29	91294	0	0	0
T35	0	8	0	0
T58	110518	15	0	0
T66	0	44	0	0
T97	0	6	0	0
T105	0	54	0	0
T140	0	56	0	0
T148	0	19	0	0
T149	0	24	0	0
T150	0	23	0	0
T151	0	19	0	0
T152	67872	0	0	0
T153	226001	0	0	0
T154	190707	0	0	0
T155	281336	0	0	0
T156	202001	0	0	0
T157	340488	0	0	0
T158	188245	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	1500	0	0
T31	176289	0	0	0
T159	1427	21	0	0
T160	1445	45	0	0
T161	0	79	0	0
T162	0	38	0	0
T163	0	42	0	0
T164	0	62	0	0
T165	0	54	0	0
T166	0	27	0	0
T167	0	10	0	0
T168	0	27	0	0
T169	172600	0	0	0
T170	331223	0	0	0
T171	16410	0	0	0
T172	175151	0	0	0
T173	266201	0	0	0
T174	252851	0	0	0
T175	261315	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	874	0	0
T66	3232	16	0	0
T67	6052	10	0	0
T68	12519	30	0	0
T76	3108	15	0	0
T90	12368	56	0	0
T92	5365	9	0	0
T113	1988	7	0	0
T131	5337	40	0	0
T132	6517	23	0	0
T133	2526	14	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	1190	0	0
T66	3232	25	0	0
T67	6052	11	0	0
T68	12519	14	0	0
T76	3108	41	0	0
T90	12368	110	0	0
T92	5365	15	0	0
T113	1988	1	0	0
T131	5337	17	0	0
T132	6517	98	0	0
T133	2526	21	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	924	0	0
T66	3232	13	0	0
T68	12519	10	0	0
T76	3108	24	0	0
T90	12368	54	0	0
T92	5365	9	0	0
T113	1988	17	0	0
T131	5337	4	0	0
T132	6517	49	0	0
T133	2526	19	0	0
T134	2584	13	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	973	0	0
T66	3232	10	0	0
T67	6052	20	0	0
T68	12519	20	0	0
T76	3108	21	0	0
T90	12368	69	0	0
T92	5365	15	0	0
T113	1988	11	0	0
T131	5337	50	0	0
T132	6517	28	0	0
T133	2526	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	909	0	0
T66	3232	7	0	0
T67	6052	16	0	0
T76	3108	19	0	0
T90	12368	67	0	0
T92	5365	14	0	0
T131	5337	68	0	0
T132	6517	17	0	0
T133	2526	9	0	0
T134	2584	2	0	0
T176	5249	55	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	933	0	0
T66	3232	6	0	0
T67	6052	5	0	0
T68	12519	21	0	0
T76	3108	23	0	0
T90	12368	79	0	0
T92	5365	1	0	0
T113	1988	3	0	0
T131	5337	40	0	0
T132	6517	33	0	0
T133	2526	16	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	908	0	0
T66	3232	17	0	0
T68	12519	23	0	0
T76	3108	15	0	0
T90	12368	64	0	0
T113	1988	5	0	0
T131	5337	36	0	0
T132	6517	12	0	0
T133	2526	9	0	0
T134	2584	12	0	0
T176	5249	53	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504237123	951	0	0
T66	3232	3	0	0
T67	6052	14	0	0
T68	12519	29	0	0
T76	3108	18	0	0
T90	12368	59	0	0
T92	5365	4	0	0
T113	1988	6	0	0
T131	5337	20	0	0
T132	6517	32	0	0
T133	2526	2	0	0