Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

169901

1

T11

33

T12

1526

T16

547

ack

19597

1

T1

38

T11

5

T12

148

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	721	1			T12	10		T16	3		T22	2
high	38368	1			T1	2		T11	4		T12	321
med	69085	1			T1	4		T11	14		T12	633
sml	80665	1			T1	32		T11	20		T12	707
all_zero	659	1			T12	3		T16	2		T22	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94611

1

T1

13

T11

17

T12

779

auto[1]

94887

1

T1

25

T11

21

T12

895

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130567

1

T1

26

T11

23

T12

1141

auto[1]

58931

1

T1

12

T11

15

T12

533

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177768

1

T1

14

T11

36

T12

1604

auto[1]

11730

1

T1

24

T11

2

T12

70

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175455

1

T1

24

T11

33

T12

1569

auto[1]

14043

1

T1

14

T11

5

T12

105

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177281

1

T1

26

T11

35

T12

1576

auto[1]

12217

1

T1

12

T11

3

T12

98

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94611

1

T1

13

T11

17

T12

779

auto[1]

94887

1

T1

25

T11

21

T12

895

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130567

1

T1

26

T11

23

T12

1141

auto[1]

58931

1

T1

12

T11

15

T12

533

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177768

1

T1

14

T11

36

T12

1604

auto[1]

11730

1

T1

24

T11

2

T12

70

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175455

1

T1

24

T11

33

T12

1569

auto[1]

14043

1

T1

14

T11

5

T12

105

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177281

1

T1

26

T11

35

T12

1576

auto[1]

12217

1

T1

12

T11

3

T12

98

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T212

1

T213

1

T143

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T166

1

T214

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T215

1

T216

1

T217

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

523

1

T12

3

T22

1

T27

7

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

252

1

T12

2

T27

1

T14

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

238

1

T12

2

T14

3

T218

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

919

1

T12

9

T22

2

T27

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

529

1

T12

5

T22

1

T27

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

485

1

T12

2

T16

1

T22

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

973

1

T11

1

T12

8

T27

7

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

465

1

T12

5

T14

4

T35

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

483

1

T11

1

T12

6

T22

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

13

1

T219

1

T220

1

T221

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

16

1

T12

1

T22

1

T222

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T223

1

T215

1

T213

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	52716	1			T11	6		T12	441		T16	175
write_address_byte	14043	1			T1	14		T11	5		T12	105
read_with_ack	4124	1			T1	12		T12	9		T14	2
read_with_nack	7606	1			T1	12		T11	2		T12	61
stop_byte	12217	1			T1	12		T11	3		T12	98
write_address_byte_nak	8315	1			T11	3		T12	62		T16	3
data_byte_nack	169901	1			T11	33		T12	1526		T16	547
stop_byte_nack	7984	1			T11	2		T12	61		T16	1
nakok_byte_nack	85110	1			T11	16		T12	815		T16	282
nakok_addr_byte_nack	4109	1			T11	1		T12	28		T16	2