Unified Coverage Report :: Group :: i2c_env_pkg::i2c_acq_fifo_cg

Group : i2c_env_pkg::i2c_acq_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.acq_fifo_cg	95.83	1	100	1	64	64

---

Group Instance : i2c_env_pkg.acq_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.acq_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	13	1	12	92.31

Variables for Group Instance i2c_env_pkg.acq_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_abyte	5	0	5	100.00	100	1	1	0
cp_action	4	0	4	100.00	100	1	1	0
cp_request_type	2	0	2	100.00	100	1	1	0
cp_target_read_ack_nack	0	0	0				1	0

Crosses for Group Instance i2c_env_pkg.acq_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_abyte_X_cp_action	13	1	12	92.31	100	1	1	0

Summary for Variable cp_abyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_abyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	1810	1			T2	8		T3	5		T7	12
high	81745	1			T2	473		T3	510		T7	411
med	149238	1			T2	936		T3	1133		T7	822
sml	150437	1			T2	942		T3	1137		T7	1293
all_zero	1322	1			T2	7		T3	4		T7	9

---

Summary for Variable cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
rstart	44716	1			T2	132		T3	357		T7	343
start	61057	1			T2	233		T3	480		T7	452
stop	16129	1			T2	101		T3	119		T7	104
none	262650	1			T2	1900		T3	1833		T7	1648

---

Summary for Variable cp_request_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_request_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

write

30210

1

T2

141

T3

244

T7

222

read

30847

1

T2

92

T3

236

T7

230

---

Summary for Variable cp_target_read_ack_nack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	0	0	0

User Defined Bins for cp_target_read_ack_nack

Excluded/Illegal bins

NAME	COUNT	STATUS
read_req_nack_before_rstart	0	Excluded
read_req_ack_before_stop	0	Excluded
read_req_nack_before_stop	0	Excluded
read_req_ack_before_rstart	0	Excluded

---

Summary for Cross cp_abyte_X_cp_action

Samples crossed: cp_abyte cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	1	12	92.31	1
Automatically Generated Cross Bins	10	1	9	90.00	1
User Defined Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for cp_abyte_X_cp_action

Uncovered bins

cp_abyte	cp_action	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[stop]	0	1	1

Covered bins

cp_abyte	cp_action	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	rstart	359	1			T7	4		T17	1		T18	2
high	rstart	9439	1			T2	29		T3	64		T7	67
high	stop	3451	1			T2	21		T3	33		T7	18
med	rstart	17389	1			T2	50		T3	141		T7	124
med	stop	6203	1			T2	42		T3	45		T7	35
sml	rstart	17526	1			T2	53		T3	152		T7	148
sml	stop	6341	1			T2	38		T3	40		T7	49
all_zero	rstart	3	1			T49	1		T210	1		T211	1
all_zero	stop	134	1			T3	1		T7	2		T182	1

User Defined Cross Bins for cp_abyte_X_cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
write_address_byte	61057	1			T2	233		T3	480		T7	452
read_address_byte	61057	1			T2	233		T3	480		T7	452
data_byte	262650	1			T2	1900		T3	1833		T7	1648